[llvm] [AMDGPU] Model structured control-flow lane masks as i1 (PR #209158)

[Petar Avramovic via llvm-commits]

================
@@ -3903,24 +3903,24 @@ def int_amdgcn_cooperative_atomic_store_8x16B : AMDGPUCooperativeAtomicStore<llv
 // convergence control tokens. The corresponding MIR pseudos are marked as
 // having side effects, which is sufficient to prevent optimizations without
 // having to mark them as convergent.
-def int_amdgcn_if : Intrinsic<[llvm_i1_ty, llvm_anyint_ty],
----------------
petar-avramovic wrote:

I assume this should not be done, changing types on existing intrinsics, it might affect other users

https://github.com/llvm/llvm-project/pull/209158