[llvm] [AArch64] Fold CSET + BR_CC into a conditional branch (PR #207398)

[Gaëtan Bossu via llvm-commits]

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@@ -11725,6 +11725,24 @@ SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
                        Overflow);
   }
 
+  // Fold CSET + BR_CC to a conditional branch (rather than keeping the CSET
+  // and emitting a TB[N]Z below).
+  {
+    using namespace llvm::SDPatternMatch;
+    SDValue Flags;
+    uint64_t InvCC;
+    auto m_CSET = m_Node(AArch64ISD::CSINC, m_Zero(), m_Zero(),
+                         m_ConstInt(InvCC), m_Value(Flags));
+    if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isNullConstant(RHS) &&
+        sd_match(LHS, m_AnyOf(m_CSET, m_And(m_CSET, m_One())))) {
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gbossu wrote:

Curious: I guess we need to match `m_And(m_CSET, m_One())` because of how `i1` types get legalised. But for registers that come from a `csinc 0, 0`, could we maybe simplify that `and` away beforehand? At least I think we should add a comment explaining that here it is safe to look through the `and` because we know the upper bits are zero.

https://github.com/llvm/llvm-project/pull/207398