[llvm] 6d026ea - [AMDGPU] Remove option to disable SGPR hazard waits (#208720)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 13 04:01:09 PDT 2026
Author: Carl Ritson
Date: 2026-07-13T20:01:05+09:00
New Revision: 6d026ea1d89795532c7ead1e57676bd1d1018afb
URL: https://github.com/llvm/llvm-project/commit/6d026ea1d89795532c7ead1e57676bd1d1018afb
DIFF: https://github.com/llvm/llvm-project/commit/6d026ea1d89795532c7ead1e57676bd1d1018afb.diff
LOG: [AMDGPU] Remove option to disable SGPR hazard waits (#208720)
This was useful when initially implemented, but probably be removed now.
Added:
Modified:
llvm/docs/AMDGPUUsage.rst
llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir
Removed:
################################################################################
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 9e401bc165b69..c9a44fa1f4fe5 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -2644,9 +2644,6 @@ The AMDGPU backend supports the following LLVM IR attributes.
This is only relevant on targets with AGPRs which support accum_offset (gfx90a+).
- "amdgpu-sgpr-hazard-wait" Disabled SGPR hazard wait insertion if set to 0.
- Exists for testing performance impact of SGPR hazard waits only.
-
"amdgpu-sgpr-hazard-boundary-cull" Enable insertion of SGPR hazard cull sequences at function call boundaries.
Cull sequence reduces future hazard waits, but has a performance cost.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp b/llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
index 1ab11a87518eb..b1491985c5d6b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
@@ -23,10 +23,6 @@ using namespace llvm;
#define DEBUG_TYPE "amdgpu-wait-sgpr-hazards"
-static cl::opt<bool> GlobalEnableSGPRHazardWaits(
- "amdgpu-sgpr-hazard-wait", cl::init(true), cl::Hidden,
- cl::desc("Enable required s_wait_alu on SGPR hazards"));
-
static cl::opt<bool> GlobalCullSGPRHazardsOnFunctionBoundary(
"amdgpu-sgpr-hazard-boundary-cull", cl::init(false), cl::Hidden,
cl::desc("Cull hazards on function boundaries"));
@@ -51,7 +47,6 @@ class AMDGPUWaitSGPRHazards {
const MachineRegisterInfo *MRI;
unsigned DsNopCount;
- bool EnableSGPRHazardWaits;
bool CullSGPRHazardsOnFunctionBoundary;
bool CullSGPRHazardsAtMemWait;
unsigned CullSGPRHazardsMemWaitThreshold;
@@ -448,14 +443,10 @@ class AMDGPUWaitSGPRHazards {
return false;
// Parse settings
- EnableSGPRHazardWaits = GlobalEnableSGPRHazardWaits;
CullSGPRHazardsOnFunctionBoundary = GlobalCullSGPRHazardsOnFunctionBoundary;
CullSGPRHazardsAtMemWait = GlobalCullSGPRHazardsAtMemWait;
CullSGPRHazardsMemWaitThreshold = GlobalCullSGPRHazardsMemWaitThreshold;
- if (!GlobalEnableSGPRHazardWaits.getNumOccurrences())
- EnableSGPRHazardWaits = MF.getFunction().getFnAttributeAsParsedInteger(
- "amdgpu-sgpr-hazard-wait", EnableSGPRHazardWaits);
if (!GlobalCullSGPRHazardsOnFunctionBoundary.getNumOccurrences())
CullSGPRHazardsOnFunctionBoundary =
MF.getFunction().hasFnAttribute("amdgpu-sgpr-hazard-boundary-cull");
@@ -468,10 +459,6 @@ class AMDGPUWaitSGPRHazards {
"amdgpu-sgpr-hazard-mem-wait-cull-threshold",
CullSGPRHazardsMemWaitThreshold);
- // Bail if disabled
- if (!EnableSGPRHazardWaits)
- return false;
-
TII = ST->getInstrInfo();
TRI = ST->getRegisterInfo();
MRI = &MF.getRegInfo();
diff --git a/llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir b/llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir
index bdff78c994852..49d41e608017d 100644
--- a/llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir
+++ b/llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir
@@ -2,8 +2,6 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass post-RA-hazard-rec,amdgpu-wait-sgpr-hazards -o - %s | FileCheck -check-prefix=GCN %s
--- |
- define amdgpu_gs void @hazard_disable() #0 { ret void }
- define amdgpu_gs void @hazard_enable() #1 { ret void }
define amdgpu_cs void @hazard_calls() #2 { ret void }
define void @hazard_callee1() #2 { ret void }
define void @hazard_callee2() #2 { ret void }
@@ -15,44 +13,11 @@
define amdgpu_cs void @hazard_cull_global() #3 { ret void }
define amdgpu_cs void @hazard_nocull_flat() #3 { ret void }
- attributes #0 = { "amdgpu-sgpr-hazard-wait"="0" }
- attributes #1 = { "amdgpu-sgpr-hazard-wait"="1" }
attributes #2 = { "amdgpu-sgpr-hazard-boundary-cull" }
attributes #3 = { "amdgpu-sgpr-hazard-mem-wait-cull" "amdgpu-sgpr-hazard-mem-wait-cull-threshold"="1" }
attributes #4 = { "amdgpu-sgpr-hazard-mem-wait-cull" "amdgpu-sgpr-hazard-mem-wait-cull-threshold"="2" }
...
----
-name: hazard_disable
-body: |
- bb.0:
- ; GCN-LABEL: name: hazard_disable
- ; GCN: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0, implicit $exec
- ; GCN-NEXT: $sgpr0_sgpr1 = S_GETPC_B64
- ; GCN-NEXT: $sgpr3 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
- ; GCN-NEXT: S_ENDPGM 0
- $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0, implicit $exec
- $sgpr0_sgpr1 = S_GETPC_B64
- $sgpr3 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
- S_ENDPGM 0
-...
-
----
-name: hazard_enable
-body: |
- bb.0:
- ; GCN-LABEL: name: hazard_enable
- ; GCN: $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0, implicit $exec
- ; GCN-NEXT: $sgpr0_sgpr1 = S_GETPC_B64
- ; GCN-NEXT: S_WAITCNT_DEPCTR .SaSdst_0
- ; GCN-NEXT: $sgpr3 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
- ; GCN-NEXT: S_ENDPGM 0
- $vgpr1 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr2, $sgpr0, implicit $exec
- $sgpr0_sgpr1 = S_GETPC_B64
- $sgpr3 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
- S_ENDPGM 0
-...
-
---
name: hazard_calls
frameInfo:
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