[llvm] 19f9973 - [NFC][SPIR-V] Remove unused LowLevelType parameter from buildLoadInst (#208428)

[via llvm-commits]

Author: Arseniy Obolenskiy
Date: 2026-07-13T11:55:51+02:00
New Revision: 19f997320131c3d01e8ee32e1f22ee98a1ee0ec7

URL: https://github.com/llvm/llvm-project/commit/19f997320131c3d01e8ee32e1f22ee98a1ee0ec7
DIFF: https://github.com/llvm/llvm-project/commit/19f997320131c3d01e8ee32e1f22ee98a1ee0ec7.diff

LOG: [NFC][SPIR-V] Remove unused LowLevelType parameter from buildLoadInst (#208428)

Added: 
    

Modified: 
    llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 7f01fc37af545..9a6b6e3fd4d7b 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -484,7 +484,7 @@ static bool buildSelectInst(MachineIRBuilder &MIRBuilder,
 /// \p DestinationReg.
 static Register buildLoadInst(SPIRVTypeInst BaseType, Register PtrRegister,
                               MachineIRBuilder &MIRBuilder,
-                              SPIRVGlobalRegistry *GR, LLT LowLevelType,
+                              SPIRVGlobalRegistry *GR,
                               Register DestinationReg = Register(0)) {
   if (!DestinationReg.isValid())
     DestinationReg = createVirtualRegister(BaseType, GR, MIRBuilder);
@@ -521,7 +521,7 @@ static Register buildBuiltinVariableLoad(
 
   // Load the value from the global variable.
   Register LoadedRegister =
-      buildLoadInst(VariableType, Variable, MIRBuilder, GR, LLType, Reg);
+      buildLoadInst(VariableType, Variable, MIRBuilder, GR, Reg);
   MIRBuilder.getMRI()->setType(LoadedRegister, LLType);
   return LoadedRegister;
 }
@@ -783,10 +783,9 @@ static bool buildAtomicCompareExchangeInst(
   if (!ScopeReg.isValid())
     ScopeReg = buildConstantIntReg32(Scope, MIRBuilder, GR);
 
-  Register Expected = IsCmpxchg
-                          ? ExpectedArg
-                          : buildLoadInst(SpvDesiredTy, ExpectedArg, MIRBuilder,
-                                          GR, LLT::scalar(64));
+  Register Expected =
+      IsCmpxchg ? ExpectedArg
+                : buildLoadInst(SpvDesiredTy, ExpectedArg, MIRBuilder, GR);
   MRI->setType(Expected, DesiredLLT);
   Register Tmp = !IsCmpxchg ? MRI->createGenericVirtualRegister(DesiredLLT)
                             : Call->ReturnRegister;