[llvm] Optimize register bank and info emission. (PR #208297)

[Alexis Engelke via llvm-commits]

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@@ -447,6 +447,15 @@ class CodeGenRegisterClass {
     SubClassWithSubReg[SubIdx] = SubRC;
   }
 
+  /// Checks if there are no super-register classes for this SubIdx of this
+  /// class.
+  bool hasNoSuperRegClasses(const CodeGenSubRegIndex *SubIdx) const;
+
+  /// Checks if there is any super-register class for this SubIdx of this
+  /// class.
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aengelke wrote:

The "any" isn't accurate?

https://github.com/llvm/llvm-project/pull/208297