[llvm] 95f1eab - [RISCV] Add getJumpConditionMergingParams to support branch condition merging (#206897)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 13 02:35:37 PDT 2026
Author: Pengcheng Wang
Date: 2026-07-13T09:35:32Z
New Revision: 95f1eab03f35545eb308246376541a7150a7a4e4
URL: https://github.com/llvm/llvm-project/commit/95f1eab03f35545eb308246376541a7150a7a4e4
DIFF: https://github.com/llvm/llvm-project/commit/95f1eab03f35545eb308246376541a7150a7a4e4.diff
LOG: [RISCV] Add getJumpConditionMergingParams to support branch condition merging (#206897)
Override `getJumpConditionMergingParams` so that
`shouldKeepJumpConditionsTogether`
can decide whether to keep `br (and/or cond1, cond2)` merged into a
single
branch or split it into two branches, based on a configurable cost
threshold.
Previously RISC-V used the default cost `{-1, -1, -1}`, which always
split
the conditions. Now it returns a base cost calculated from
`MispredictPenalty`
(via scaling it down by an assumed misprediction rate 25%).
These values are controllable via
`riscv-br-merging-base-cost/-likely-bias/-unlikely-bias`.
This is another approach to #191158 when `TuneJumpIsExpensive` is not
set.
Added:
llvm/test/CodeGen/RISCV/jump-cond-merging-optsize.ll
Modified:
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/lib/Target/SystemZ/SystemZISelLowering.h
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.h
llvm/test/CodeGen/RISCV/double-previous-failure.ll
llvm/test/CodeGen/RISCV/jump-is-expensive.ll
llvm/test/CodeGen/RISCV/or-is-add.ll
llvm/test/CodeGen/RISCV/rvv/pr93587.ll
llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll
llvm/test/CodeGen/RISCV/select-and.ll
llvm/test/CodeGen/RISCV/select-or.ll
llvm/test/CodeGen/RISCV/setcc-logic.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index f7f14fed05393..b8b073962cb29 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -659,9 +659,10 @@ class LLVM_ABI TargetLoweringBase {
// Arg0: The binary op joining the two conditions (and/or).
// Arg1: The first condition (cond1)
// Arg2: The second condition (cond2)
+ // Arg3: The containing function.
virtual CondMergingParams
getJumpConditionMergingParams(Instruction::BinaryOps, const Value *,
- const Value *) const {
+ const Value *, const Function *) const {
// -1 will always result in splitting.
return {-1, -1, -1};
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 27a6cf37807b5..98c91e65b4752 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -2869,7 +2869,7 @@ void SelectionDAGBuilder::visitCondBr(const CondBrInst &I) {
!shouldKeepJumpConditionsTogether(
FuncInfo, I, Opcode, BOp0, BOp1,
DAG.getTargetLoweringInfo().getJumpConditionMergingParams(
- Opcode, BOp0, BOp1))) {
+ Opcode, BOp0, BOp1, FuncInfo.Fn))) {
FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, Opcode,
getEdgeProbability(BrMBB, Succ0MBB),
getEdgeProbability(BrMBB, Succ1MBB),
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index f33d953eec747..4192184480e82 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -32540,7 +32540,8 @@ bool AArch64TargetLowering::
TargetLoweringBase::CondMergingParams
AArch64TargetLowering::getJumpConditionMergingParams(Instruction::BinaryOps Opc,
const Value *Lhs,
- const Value *Rhs) const {
+ const Value *Rhs,
+ const Function *) const {
using namespace llvm::PatternMatch;
// Keep floating-point conditions split rather than folding them into an
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 69013d4010122..6e395e004f519 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -451,7 +451,8 @@ class AArch64TargetLowering : public TargetLowering {
CondMergingParams
getJumpConditionMergingParams(Instruction::BinaryOps Opc, const Value *Lhs,
- const Value *Rhs) const override;
+ const Value *Rhs,
+ const Function *F) const override;
bool shouldTransformSignedTruncationCheck(EVT XVT,
unsigned KeptBits) const override {
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index be538de8cf943..3073f6cf91ed8 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -88,6 +88,41 @@ static cl::opt<bool>
"be combined with a shift"),
cl::init(true));
+static cl::opt<int> BrMergingBaseCostThresh(
+ "riscv-br-merging-base-cost", cl::init(2),
+ cl::desc(
+ "Sets the cost threshold for when multiple conditionals will be merged "
+ "into one branch versus be split in multiple branches. Merging "
+ "conditionals saves branches at the cost of additional instructions. "
+ "This value sets the instruction cost limit, below which conditionals "
+ "will be merged, and above which conditionals will be split. Set to -1 "
+ "to never merge branches."),
+ cl::Hidden);
+
+static cl::opt<int> BrMergingLikelyBias(
+ "riscv-br-merging-likely-bias", cl::init(0),
+ cl::desc(
+ "Increases 'riscv-br-merging-base-cost' in cases that it is "
+ "likely that all conditionals will be executed. For example for "
+ "merging the conditionals (a == b && c > d), if its known that "
+ "a == b is likely, then it is likely that if the conditionals are "
+ "split both sides will be executed, so it may be desirable to "
+ "increase the instruction cost threshold. Set to -1 to never merge "
+ "likely branches."),
+ cl::Hidden);
+
+static cl::opt<int> BrMergingUnlikelyBias(
+ "riscv-br-merging-unlikely-bias", cl::init(-1),
+ cl::desc(
+ "Decreases 'riscv-br-merging-base-cost' in cases that it is unlikely "
+ "that all conditionals will be executed. For example for merging "
+ "the conditionals (a == b && c > d), if its known that a == b is "
+ "unlikely, then it is unlikely that if the conditionals are split "
+ "both sides will be executed, so it may be desirable to decrease "
+ "the instruction cost threshold. Set to -1 to never merge unlikely "
+ "branches."),
+ cl::Hidden);
+
// TODO: Support more ops
static const unsigned ZvfbfaOps[] = {
ISD::FNEG, ISD::FABS, ISD::FCOPYSIGN, ISD::FADD,
@@ -2038,6 +2073,25 @@ EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL,
return VT.changeVectorElementTypeToInteger();
}
+TargetLoweringBase::CondMergingParams
+RISCVTargetLowering::getJumpConditionMergingParams(Instruction::BinaryOps Opc,
+ const Value *LHS,
+ const Value *RHS,
+ const Function *F) const {
+ if (F->hasOptSize())
+ return TargetLowering::getJumpConditionMergingParams(Opc, LHS, RHS, F);
+
+ // Merging conditions eliminates a branch, so the budget we are willing to
+ // spend eagerly computing the RHS condition should scale with how expensive a
+ // mispredicted branch is. A branch only costs the full penalty when actually
+ // mispredicted, so scale it down by an assumed misprediction rate (~25%).
+ int BaseCost = Subtarget.getSchedModel().MispredictPenalty / 4;
+ if (BrMergingBaseCostThresh.getNumOccurrences() > 1)
+ BaseCost = BrMergingBaseCostThresh;
+
+ return {BaseCost, BrMergingLikelyBias, BrMergingUnlikelyBias};
+}
+
MVT RISCVTargetLowering::getVPExplicitVectorLengthTy() const {
return Subtarget.getXLenVT();
}
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 4e7912ed815dd..f8a99d38e2691 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -202,6 +202,11 @@ class RISCVTargetLowering : public TargetLowering {
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
EVT VT) const override;
+ CondMergingParams
+ getJumpConditionMergingParams(Instruction::BinaryOps Opc, const Value *LHS,
+ const Value *RHS,
+ const Function *F) const override;
+
bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
bool MathUsed) const override {
if (VT == MVT::i8 || VT == MVT::i16)
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 388e44af29aab..42d100cd4f574 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -8965,7 +8965,8 @@ static bool combineCCMask(SDValue &CCReg, int &CCValid, int &CCMask,
TargetLoweringBase::CondMergingParams
SystemZTargetLowering::getJumpConditionMergingParams(Instruction::BinaryOps Opc,
const Value *Lhs,
- const Value *Rhs) const {
+ const Value *Rhs,
+ const Function *) const {
const auto isFlagOutOpCC = [](const Value *V) {
using namespace llvm::PatternMatch;
const Value *RHSVal;
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
index 7facd3a27d97c..a4c38d41b4880 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.h
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
@@ -159,7 +159,8 @@ class SystemZTargetLowering : public TargetLowering {
// This function currently returns cost for srl/ipm/cc sequence for merging.
CondMergingParams
getJumpConditionMergingParams(Instruction::BinaryOps Opc, const Value *Lhs,
- const Value *Rhs) const override;
+ const Value *Rhs,
+ const Function *F) const override;
// Handle Lowering flag assembly outputs.
SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag,
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 46edb6c001955..7bcd9d6b80d1c 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -3832,7 +3832,8 @@ unsigned X86TargetLowering::preferedOpcodeForCmpEqPiecesOfOperand(
TargetLoweringBase::CondMergingParams
X86TargetLowering::getJumpConditionMergingParams(Instruction::BinaryOps Opc,
const Value *Lhs,
- const Value *Rhs) const {
+ const Value *Rhs,
+ const Function *) const {
using namespace llvm::PatternMatch;
int BaseCost = BrMergingBaseCostThresh.getValue();
// With CCMP, branches can be merged in a more efficient way.
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index 7710cd06dcd28..798050028c15a 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -276,7 +276,8 @@ namespace llvm {
CondMergingParams
getJumpConditionMergingParams(Instruction::BinaryOps Opc, const Value *Lhs,
- const Value *Rhs) const override;
+ const Value *Rhs,
+ const Function *F) const override;
bool shouldFoldConstantShiftPairToMask(const SDNode *N) const override;
diff --git a/llvm/test/CodeGen/RISCV/double-previous-failure.ll b/llvm/test/CodeGen/RISCV/double-previous-failure.ll
index c0993faa9584a..652ad13025458 100644
--- a/llvm/test/CodeGen/RISCV/double-previous-failure.ll
+++ b/llvm/test/CodeGen/RISCV/double-previous-failure.ll
@@ -31,17 +31,16 @@ define i32 @main() nounwind {
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IFD-NEXT: fld fa5, 0(sp)
; RV32IFD-NEXT: fld fa4, %lo(.LCPI1_0)(a0)
-; RV32IFD-NEXT: flt.d a0, fa5, fa4
-; RV32IFD-NEXT: bnez a0, .LBB1_3
-; RV32IFD-NEXT: # %bb.1: # %entry
; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1)
-; RV32IFD-NEXT: fld fa4, %lo(.LCPI1_1)(a0)
-; RV32IFD-NEXT: flt.d a0, fa4, fa5
-; RV32IFD-NEXT: bnez a0, .LBB1_3
-; RV32IFD-NEXT: # %bb.2: # %if.end
-; RV32IFD-NEXT: call exit
-; RV32IFD-NEXT: .LBB1_3: # %if.then
+; RV32IFD-NEXT: fld fa3, %lo(.LCPI1_1)(a0)
+; RV32IFD-NEXT: flt.d a0, fa5, fa4
+; RV32IFD-NEXT: flt.d a1, fa3, fa5
+; RV32IFD-NEXT: or a0, a0, a1
+; RV32IFD-NEXT: beqz a0, .LBB1_2
+; RV32IFD-NEXT: # %bb.1: # %if.then
; RV32IFD-NEXT: call abort
+; RV32IFD-NEXT: .LBB1_2: # %if.end
+; RV32IFD-NEXT: call exit
;
; RV32IZFINXZDINX-LABEL: main:
; RV32IZFINXZDINX: # %bb.0: # %entry
@@ -53,20 +52,19 @@ define i32 @main() nounwind {
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_0)
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI1_0)(a2)
; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI1_0)
+; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI1_1)
; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
-; RV32IZFINXZDINX-NEXT: flt.d a2, a0, a4
-; RV32IZFINXZDINX-NEXT: bnez a2, .LBB1_3
-; RV32IZFINXZDINX-NEXT: # %bb.1: # %entry
-; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_1)
-; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI1_1)(a2)
-; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI1_1)
-; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
-; RV32IZFINXZDINX-NEXT: flt.d a0, a4, a0
-; RV32IZFINXZDINX-NEXT: bnez a0, .LBB1_3
-; RV32IZFINXZDINX-NEXT: # %bb.2: # %if.end
-; RV32IZFINXZDINX-NEXT: call exit
-; RV32IZFINXZDINX-NEXT: .LBB1_3: # %if.then
+; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI1_1)(a3)
+; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI1_1)
+; RV32IZFINXZDINX-NEXT: lw a3, 4(a3)
+; RV32IZFINXZDINX-NEXT: flt.d a4, a0, a4
+; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a0
+; RV32IZFINXZDINX-NEXT: or a0, a4, a0
+; RV32IZFINXZDINX-NEXT: beqz a0, .LBB1_2
+; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.then
; RV32IZFINXZDINX-NEXT: call abort
+; RV32IZFINXZDINX-NEXT: .LBB1_2: # %if.end
+; RV32IZFINXZDINX-NEXT: call exit
entry:
%call = call double @test(double 2.000000e+00)
%cmp = fcmp olt double %call, 2.400000e-01
diff --git a/llvm/test/CodeGen/RISCV/jump-cond-merging-optsize.ll b/llvm/test/CodeGen/RISCV/jump-cond-merging-optsize.ll
new file mode 100644
index 0000000000000..5c545d4530e68
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/jump-cond-merging-optsize.ll
@@ -0,0 +1,68 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: sed 's/ATTRS//g' %s | llc -mtriple=riscv64 -verify-machineinstrs \
+; RUN: | FileCheck %s --check-prefix=DEFAULT
+; RUN: sed 's/ATTRS/optsize/g' %s | llc -mtriple=riscv64 -verify-machineinstrs \
+; RUN: | FileCheck %s --check-prefix=OPTSIZE
+
+declare void @foo()
+declare void @bar()
+
+define void @or_cmp(i64 %a, i64 %b, i64 %c, i64 %d) ATTRS {
+; DEFAULT-LABEL: or_cmp:
+; DEFAULT: # %bb.0: # %entry
+; DEFAULT-NEXT: addi sp, sp, -16
+; DEFAULT-NEXT: .cfi_def_cfa_offset 16
+; DEFAULT-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; DEFAULT-NEXT: .cfi_offset ra, -8
+; DEFAULT-NEXT: xor a0, a0, a1
+; DEFAULT-NEXT: xor a2, a2, a3
+; DEFAULT-NEXT: snez a0, a0
+; DEFAULT-NEXT: snez a1, a2
+; DEFAULT-NEXT: and a0, a0, a1
+; DEFAULT-NEXT: bnez a0, .LBB0_2
+; DEFAULT-NEXT: # %bb.1: # %if.then
+; DEFAULT-NEXT: call foo
+; DEFAULT-NEXT: j .LBB0_3
+; DEFAULT-NEXT: .LBB0_2: # %if.else
+; DEFAULT-NEXT: call bar
+; DEFAULT-NEXT: .LBB0_3: # %if.then
+; DEFAULT-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; DEFAULT-NEXT: .cfi_restore ra
+; DEFAULT-NEXT: addi sp, sp, 16
+; DEFAULT-NEXT: .cfi_def_cfa_offset 0
+; DEFAULT-NEXT: ret
+;
+; OPTSIZE-LABEL: or_cmp:
+; OPTSIZE: # %bb.0: # %entry
+; OPTSIZE-NEXT: addi sp, sp, -16
+; OPTSIZE-NEXT: .cfi_def_cfa_offset 16
+; OPTSIZE-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; OPTSIZE-NEXT: .cfi_offset ra, -8
+; OPTSIZE-NEXT: beq a0, a1, .LBB0_3
+; OPTSIZE-NEXT: # %bb.1: # %entry
+; OPTSIZE-NEXT: beq a2, a3, .LBB0_3
+; OPTSIZE-NEXT: # %bb.2: # %if.else
+; OPTSIZE-NEXT: call bar
+; OPTSIZE-NEXT: j .LBB0_4
+; OPTSIZE-NEXT: .LBB0_3: # %if.then
+; OPTSIZE-NEXT: call foo
+; OPTSIZE-NEXT: .LBB0_4: # %if.then
+; OPTSIZE-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; OPTSIZE-NEXT: .cfi_restore ra
+; OPTSIZE-NEXT: addi sp, sp, 16
+; OPTSIZE-NEXT: .cfi_def_cfa_offset 0
+; OPTSIZE-NEXT: ret
+entry:
+ %cmp0 = icmp eq i64 %a, %b
+ %cmp1 = icmp eq i64 %c, %d
+ %or = or i1 %cmp0, %cmp1
+ br i1 %or, label %if.then, label %if.else
+
+if.then:
+ call void @foo()
+ ret void
+
+if.else:
+ call void @bar()
+ ret void
+}
diff --git a/llvm/test/CodeGen/RISCV/jump-is-expensive.ll b/llvm/test/CodeGen/RISCV/jump-is-expensive.ll
index 6778223181e2c..13e86057983b2 100644
--- a/llvm/test/CodeGen/RISCV/jump-is-expensive.ll
+++ b/llvm/test/CodeGen/RISCV/jump-is-expensive.ll
@@ -6,16 +6,16 @@
define void @foo(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHEAP-LABEL: foo:
; CHEAP: # %bb.0: # %entry
-; CHEAP-NEXT: li a2, 5
; CHEAP-NEXT: sext.w a1, a1
-; CHEAP-NEXT: blt a1, a2, .LBB0_3
-; CHEAP-NEXT: # %bb.1: # %entry
; CHEAP-NEXT: sext.w a0, a0
-; CHEAP-NEXT: beqz a0, .LBB0_3
-; CHEAP-NEXT: # %bb.2: # %UnifiedReturnBlock
-; CHEAP-NEXT: ret
-; CHEAP-NEXT: .LBB0_3: # %cond_true
+; CHEAP-NEXT: seqz a0, a0
+; CHEAP-NEXT: slti a1, a1, 5
+; CHEAP-NEXT: or a0, a0, a1
+; CHEAP-NEXT: beqz a0, .LBB0_2
+; CHEAP-NEXT: # %bb.1: # %cond_true
; CHEAP-NEXT: tail bar
+; CHEAP-NEXT: .LBB0_2: # %UnifiedReturnBlock
+; CHEAP-NEXT: ret
;
; EXPENSIVE-LABEL: foo:
; EXPENSIVE: # %bb.0: # %entry
diff --git a/llvm/test/CodeGen/RISCV/or-is-add.ll b/llvm/test/CodeGen/RISCV/or-is-add.ll
index cf3260fbee37a..32ae5b4eacbab 100644
--- a/llvm/test/CodeGen/RISCV/or-is-add.ll
+++ b/llvm/test/CodeGen/RISCV/or-is-add.ll
@@ -128,20 +128,22 @@ define void @pr128468(ptr %0, i32 signext %1, i32 signext %2) {
; RV32: # %bb.0:
; RV32-NEXT: slli a3, a1, 3
; RV32-NEXT: add a3, a0, a3
-; RV32-NEXT: lw a2, 4(a3)
-; RV32-NEXT: bgez a2, .LBB7_6
-; RV32-NEXT: # %bb.1:
+; RV32-NEXT: lw a4, 4(a3)
; RV32-NEXT: slli a2, a1, 1
; RV32-NEXT: addi a2, a2, 1
-; RV32-NEXT: beq a2, a1, .LBB7_6
-; RV32-NEXT: # %bb.2: # %.preheader
+; RV32-NEXT: xor a5, a2, a1
+; RV32-NEXT: srli a4, a4, 31
+; RV32-NEXT: snez a5, a5
+; RV32-NEXT: and a4, a5, a4
+; RV32-NEXT: beqz a4, .LBB7_5
+; RV32-NEXT: # %bb.1: # %.preheader
; RV32-NEXT: addi a3, a3, 4
-; RV32-NEXT: j .LBB7_4
-; RV32-NEXT: .LBB7_3: # in Loop: Header=BB7_4 Depth=1
+; RV32-NEXT: j .LBB7_3
+; RV32-NEXT: .LBB7_2: # in Loop: Header=BB7_3 Depth=1
; RV32-NEXT: mv a2, a1
; RV32-NEXT: addi a3, a3, 4
-; RV32-NEXT: beq a1, a1, .LBB7_6
-; RV32-NEXT: .LBB7_4: # =>This Inner Loop Header: Depth=1
+; RV32-NEXT: beq a1, a1, .LBB7_5
+; RV32-NEXT: .LBB7_3: # =>This Inner Loop Header: Depth=1
; RV32-NEXT: mv a4, a1
; RV32-NEXT: mv a1, a2
; RV32-NEXT: slli a4, a4, 2
@@ -151,13 +153,13 @@ define void @pr128468(ptr %0, i32 signext %1, i32 signext %2) {
; RV32-NEXT: sw a2, 0(a3)
; RV32-NEXT: add a3, a0, a4
; RV32-NEXT: lw a2, 4(a3)
-; RV32-NEXT: bgez a2, .LBB7_3
-; RV32-NEXT: # %bb.5: # in Loop: Header=BB7_4 Depth=1
+; RV32-NEXT: bgez a2, .LBB7_2
+; RV32-NEXT: # %bb.4: # in Loop: Header=BB7_3 Depth=1
; RV32-NEXT: slli a2, a1, 1
; RV32-NEXT: addi a2, a2, 1
; RV32-NEXT: addi a3, a3, 4
-; RV32-NEXT: bne a2, a1, .LBB7_4
-; RV32-NEXT: .LBB7_6:
+; RV32-NEXT: bne a2, a1, .LBB7_3
+; RV32-NEXT: .LBB7_5:
; RV32-NEXT: ret
;
; RV64-LABEL: pr128468:
@@ -166,18 +168,20 @@ define void @pr128468(ptr %0, i32 signext %1, i32 signext %2) {
; RV64-NEXT: slli a3, a2, 2
; RV64-NEXT: add a3, a0, a3
; RV64-NEXT: lw a4, 4(a3)
-; RV64-NEXT: bgez a4, .LBB7_6
-; RV64-NEXT: # %bb.1:
; RV64-NEXT: addiw a2, a2, 1
-; RV64-NEXT: beq a2, a1, .LBB7_6
-; RV64-NEXT: # %bb.2: # %.preheader
+; RV64-NEXT: xor a5, a2, a1
+; RV64-NEXT: srli a4, a4, 63
+; RV64-NEXT: snez a5, a5
+; RV64-NEXT: and a4, a5, a4
+; RV64-NEXT: beqz a4, .LBB7_5
+; RV64-NEXT: # %bb.1: # %.preheader
; RV64-NEXT: addi a3, a3, 4
-; RV64-NEXT: j .LBB7_4
-; RV64-NEXT: .LBB7_3: # in Loop: Header=BB7_4 Depth=1
+; RV64-NEXT: j .LBB7_3
+; RV64-NEXT: .LBB7_2: # in Loop: Header=BB7_3 Depth=1
; RV64-NEXT: mv a2, a1
; RV64-NEXT: addi a3, a3, 4
-; RV64-NEXT: beq a1, a1, .LBB7_6
-; RV64-NEXT: .LBB7_4: # =>This Inner Loop Header: Depth=1
+; RV64-NEXT: beq a1, a1, .LBB7_5
+; RV64-NEXT: .LBB7_3: # =>This Inner Loop Header: Depth=1
; RV64-NEXT: mv a4, a1
; RV64-NEXT: mv a1, a2
; RV64-NEXT: slli a4, a4, 2
@@ -188,12 +192,12 @@ define void @pr128468(ptr %0, i32 signext %1, i32 signext %2) {
; RV64-NEXT: sw a4, 0(a3)
; RV64-NEXT: add a3, a0, a5
; RV64-NEXT: lw a4, 4(a3)
-; RV64-NEXT: bgez a4, .LBB7_3
-; RV64-NEXT: # %bb.5: # in Loop: Header=BB7_4 Depth=1
+; RV64-NEXT: bgez a4, .LBB7_2
+; RV64-NEXT: # %bb.4: # in Loop: Header=BB7_3 Depth=1
; RV64-NEXT: addiw a2, a2, 1
; RV64-NEXT: addi a3, a3, 4
-; RV64-NEXT: bne a2, a1, .LBB7_4
-; RV64-NEXT: .LBB7_6:
+; RV64-NEXT: bne a2, a1, .LBB7_3
+; RV64-NEXT: .LBB7_5:
; RV64-NEXT: ret
%4 = shl nsw i32 %1, 1
%5 = or disjoint i32 %4, 1
diff --git a/llvm/test/CodeGen/RISCV/rvv/pr93587.ll b/llvm/test/CodeGen/RISCV/rvv/pr93587.ll
index c2998bf20fa0a..38b79ee2fec14 100644
--- a/llvm/test/CodeGen/RISCV/rvv/pr93587.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/pr93587.ll
@@ -14,12 +14,10 @@ define i16 @f() {
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; CHECK-NEXT: j .LBB0_1
-; CHECK-NEXT: # %bb.2: # %BB1
-; CHECK-NEXT: li a0, 0
+; CHECK-NEXT: li a0, 1
; CHECK-NEXT: bnez a0, .LBB0_1
-; CHECK-NEXT: j .LBB0_3
-; CHECK-NEXT: .LBB0_3: # %BB2
+; CHECK-NEXT: j .LBB0_2
+; CHECK-NEXT: .LBB0_2: # %BB2
; CHECK-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: .cfi_def_cfa_offset 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll b/llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll
index ff5c4e52bb586..b4b5ce9f4e960 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll
@@ -76,14 +76,15 @@ define dso_local void @test_store1(ptr nocapture noundef writeonly %dst, ptr noc
; RV64: # %bb.0: # %entry
; RV64-NEXT: blez a3, .LBB0_6
; RV64-NEXT: # %bb.1: # %for.body.preheader
-; RV64-NEXT: li a5, 8
+; RV64-NEXT: sub a4, a0, a1
+; RV64-NEXT: sltiu a5, a3, 8
+; RV64-NEXT: sltiu a4, a4, 32
+; RV64-NEXT: or a4, a5, a4
+; RV64-NEXT: beqz a4, .LBB0_3
+; RV64-NEXT: # %bb.2:
; RV64-NEXT: li a4, 0
-; RV64-NEXT: bltu a3, a5, .LBB0_7
-; RV64-NEXT: # %bb.2: # %for.body.preheader
-; RV64-NEXT: sub a5, a0, a1
-; RV64-NEXT: li a6, 31
-; RV64-NEXT: bgeu a6, a5, .LBB0_7
-; RV64-NEXT: # %bb.3: # %vector.ph
+; RV64-NEXT: j .LBB0_7
+; RV64-NEXT: .LBB0_3: # %vector.ph
; RV64-NEXT: lui a4, 524288
; RV64-NEXT: addiw a4, a4, -8
; RV64-NEXT: and a4, a3, a4
diff --git a/llvm/test/CodeGen/RISCV/select-and.ll b/llvm/test/CodeGen/RISCV/select-and.ll
index 2c9d0a8b56425..7a5f5d62cabba 100644
--- a/llvm/test/CodeGen/RISCV/select-and.ll
+++ b/llvm/test/CodeGen/RISCV/select-and.ll
@@ -48,15 +48,14 @@ define signext i32 @if_of_and(i1 zeroext %a, i1 zeroext %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: beqz a0, .LBB1_3
-; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: beqz a1, .LBB1_3
-; RV32I-NEXT: # %bb.2: # %if.then
+; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB1_2
+; RV32I-NEXT: # %bb.1: # %if.then
; RV32I-NEXT: call both
-; RV32I-NEXT: j .LBB1_4
-; RV32I-NEXT: .LBB1_3: # %if.else
+; RV32I-NEXT: j .LBB1_3
+; RV32I-NEXT: .LBB1_2: # %if.else
; RV32I-NEXT: call neither
-; RV32I-NEXT: .LBB1_4: # %if.end
+; RV32I-NEXT: .LBB1_3: # %if.end
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -65,15 +64,14 @@ define signext i32 @if_of_and(i1 zeroext %a, i1 zeroext %b) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: beqz a0, .LBB1_3
-; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: beqz a1, .LBB1_3
-; RV64I-NEXT: # %bb.2: # %if.then
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB1_2
+; RV64I-NEXT: # %bb.1: # %if.then
; RV64I-NEXT: call both
-; RV64I-NEXT: j .LBB1_4
-; RV64I-NEXT: .LBB1_3: # %if.else
+; RV64I-NEXT: j .LBB1_3
+; RV64I-NEXT: .LBB1_2: # %if.else
; RV64I-NEXT: call neither
-; RV64I-NEXT: .LBB1_4: # %if.end
+; RV64I-NEXT: .LBB1_3: # %if.end
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
@@ -82,15 +80,14 @@ define signext i32 @if_of_and(i1 zeroext %a, i1 zeroext %b) nounwind {
; RV64I-CCMOV: # %bb.0:
; RV64I-CCMOV-NEXT: addi sp, sp, -16
; RV64I-CCMOV-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-CCMOV-NEXT: beqz a0, .LBB1_3
-; RV64I-CCMOV-NEXT: # %bb.1:
-; RV64I-CCMOV-NEXT: beqz a1, .LBB1_3
-; RV64I-CCMOV-NEXT: # %bb.2: # %if.then
+; RV64I-CCMOV-NEXT: and a0, a0, a1
+; RV64I-CCMOV-NEXT: beqz a0, .LBB1_2
+; RV64I-CCMOV-NEXT: # %bb.1: # %if.then
; RV64I-CCMOV-NEXT: call both
-; RV64I-CCMOV-NEXT: j .LBB1_4
-; RV64I-CCMOV-NEXT: .LBB1_3: # %if.else
+; RV64I-CCMOV-NEXT: j .LBB1_3
+; RV64I-CCMOV-NEXT: .LBB1_2: # %if.else
; RV64I-CCMOV-NEXT: call neither
-; RV64I-CCMOV-NEXT: .LBB1_4: # %if.end
+; RV64I-CCMOV-NEXT: .LBB1_3: # %if.end
; RV64I-CCMOV-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-CCMOV-NEXT: addi sp, sp, 16
; RV64I-CCMOV-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/select-or.ll b/llvm/test/CodeGen/RISCV/select-or.ll
index 091c8b1a11e71..6dbe291f8ed99 100644
--- a/llvm/test/CodeGen/RISCV/select-or.ll
+++ b/llvm/test/CodeGen/RISCV/select-or.ll
@@ -48,15 +48,14 @@ define signext i32 @if_of_or(i1 zeroext %a, i1 zeroext %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: bnez a0, .LBB1_3
-; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: bnez a1, .LBB1_3
-; RV32I-NEXT: # %bb.2: # %if.else
-; RV32I-NEXT: call neither
-; RV32I-NEXT: j .LBB1_4
-; RV32I-NEXT: .LBB1_3: # %if.then
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: beqz a0, .LBB1_2
+; RV32I-NEXT: # %bb.1: # %if.then
; RV32I-NEXT: call either
-; RV32I-NEXT: .LBB1_4: # %if.end
+; RV32I-NEXT: j .LBB1_3
+; RV32I-NEXT: .LBB1_2: # %if.else
+; RV32I-NEXT: call neither
+; RV32I-NEXT: .LBB1_3: # %if.end
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -65,15 +64,14 @@ define signext i32 @if_of_or(i1 zeroext %a, i1 zeroext %b) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: bnez a0, .LBB1_3
-; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: bnez a1, .LBB1_3
-; RV64I-NEXT: # %bb.2: # %if.else
-; RV64I-NEXT: call neither
-; RV64I-NEXT: j .LBB1_4
-; RV64I-NEXT: .LBB1_3: # %if.then
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: beqz a0, .LBB1_2
+; RV64I-NEXT: # %bb.1: # %if.then
; RV64I-NEXT: call either
-; RV64I-NEXT: .LBB1_4: # %if.end
+; RV64I-NEXT: j .LBB1_3
+; RV64I-NEXT: .LBB1_2: # %if.else
+; RV64I-NEXT: call neither
+; RV64I-NEXT: .LBB1_3: # %if.end
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
@@ -82,15 +80,14 @@ define signext i32 @if_of_or(i1 zeroext %a, i1 zeroext %b) nounwind {
; RV64I-CCMOV: # %bb.0:
; RV64I-CCMOV-NEXT: addi sp, sp, -16
; RV64I-CCMOV-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-CCMOV-NEXT: bnez a0, .LBB1_3
-; RV64I-CCMOV-NEXT: # %bb.1:
-; RV64I-CCMOV-NEXT: bnez a1, .LBB1_3
-; RV64I-CCMOV-NEXT: # %bb.2: # %if.else
-; RV64I-CCMOV-NEXT: call neither
-; RV64I-CCMOV-NEXT: j .LBB1_4
-; RV64I-CCMOV-NEXT: .LBB1_3: # %if.then
+; RV64I-CCMOV-NEXT: or a0, a0, a1
+; RV64I-CCMOV-NEXT: beqz a0, .LBB1_2
+; RV64I-CCMOV-NEXT: # %bb.1: # %if.then
; RV64I-CCMOV-NEXT: call either
-; RV64I-CCMOV-NEXT: .LBB1_4: # %if.end
+; RV64I-CCMOV-NEXT: j .LBB1_3
+; RV64I-CCMOV-NEXT: .LBB1_2: # %if.else
+; RV64I-CCMOV-NEXT: call neither
+; RV64I-CCMOV-NEXT: .LBB1_3: # %if.end
; RV64I-CCMOV-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-CCMOV-NEXT: addi sp, sp, 16
; RV64I-CCMOV-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/setcc-logic.ll b/llvm/test/CodeGen/RISCV/setcc-logic.ll
index 4e14893290ca8..68415bade0d97 100644
--- a/llvm/test/CodeGen/RISCV/setcc-logic.ll
+++ b/llvm/test/CodeGen/RISCV/setcc-logic.ll
@@ -297,22 +297,26 @@ declare void @bar(...)
define void @and_sge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: and_sge_eq:
; RV32I: # %bb.0:
-; RV32I-NEXT: blt a0, a1, .LBB13_3
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: slt a0, a0, a1
+; RV32I-NEXT: snez a1, a2
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: bnez a0, .LBB13_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: bne a2, a3, .LBB13_3
-; RV32I-NEXT: # %bb.2:
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB13_3:
+; RV32I-NEXT: .LBB13_2:
; RV32I-NEXT: tail bar
;
; RV64I-LABEL: and_sge_eq:
; RV64I: # %bb.0:
-; RV64I-NEXT: blt a0, a1, .LBB13_3
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: slt a0, a0, a1
+; RV64I-NEXT: snez a1, a2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: bnez a0, .LBB13_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: bne a2, a3, .LBB13_3
-; RV64I-NEXT: # %bb.2:
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB13_3:
+; RV64I-NEXT: .LBB13_2:
; RV64I-NEXT: tail bar
%5 = icmp sge i32 %0, %1
%6 = icmp eq i32 %2, %3
@@ -330,22 +334,26 @@ define void @and_sge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign
define void @and_sle_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: and_sle_eq:
; RV32I: # %bb.0:
-; RV32I-NEXT: blt a1, a0, .LBB14_3
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: slt a0, a1, a0
+; RV32I-NEXT: snez a1, a2
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: bnez a0, .LBB14_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: bne a2, a3, .LBB14_3
-; RV32I-NEXT: # %bb.2:
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB14_3:
+; RV32I-NEXT: .LBB14_2:
; RV32I-NEXT: tail bar
;
; RV64I-LABEL: and_sle_eq:
; RV64I: # %bb.0:
-; RV64I-NEXT: blt a1, a0, .LBB14_3
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: slt a0, a1, a0
+; RV64I-NEXT: snez a1, a2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: bnez a0, .LBB14_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: bne a2, a3, .LBB14_3
-; RV64I-NEXT: # %bb.2:
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB14_3:
+; RV64I-NEXT: .LBB14_2:
; RV64I-NEXT: tail bar
%5 = icmp sle i32 %0, %1
%6 = icmp eq i32 %2, %3
@@ -363,22 +371,26 @@ define void @and_sle_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign
define void @and_uge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: and_uge_eq:
; RV32I: # %bb.0:
-; RV32I-NEXT: bltu a0, a1, .LBB15_3
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: sltu a0, a0, a1
+; RV32I-NEXT: snez a1, a2
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: bnez a0, .LBB15_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: bne a2, a3, .LBB15_3
-; RV32I-NEXT: # %bb.2:
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB15_3:
+; RV32I-NEXT: .LBB15_2:
; RV32I-NEXT: tail bar
;
; RV64I-LABEL: and_uge_eq:
; RV64I: # %bb.0:
-; RV64I-NEXT: bltu a0, a1, .LBB15_3
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: sltu a0, a0, a1
+; RV64I-NEXT: snez a1, a2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: bnez a0, .LBB15_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: bne a2, a3, .LBB15_3
-; RV64I-NEXT: # %bb.2:
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB15_3:
+; RV64I-NEXT: .LBB15_2:
; RV64I-NEXT: tail bar
%5 = icmp uge i32 %0, %1
%6 = icmp eq i32 %2, %3
@@ -396,22 +408,26 @@ define void @and_uge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign
define void @and_ule_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: and_ule_eq:
; RV32I: # %bb.0:
-; RV32I-NEXT: bltu a1, a0, .LBB16_3
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: sltu a0, a1, a0
+; RV32I-NEXT: snez a1, a2
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: bnez a0, .LBB16_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: bne a2, a3, .LBB16_3
-; RV32I-NEXT: # %bb.2:
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB16_3:
+; RV32I-NEXT: .LBB16_2:
; RV32I-NEXT: tail bar
;
; RV64I-LABEL: and_ule_eq:
; RV64I: # %bb.0:
-; RV64I-NEXT: bltu a1, a0, .LBB16_3
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: sltu a0, a1, a0
+; RV64I-NEXT: snez a1, a2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: bnez a0, .LBB16_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: bne a2, a3, .LBB16_3
-; RV64I-NEXT: # %bb.2:
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB16_3:
+; RV64I-NEXT: .LBB16_2:
; RV64I-NEXT: tail bar
%5 = icmp ule i32 %0, %1
%6 = icmp eq i32 %2, %3
@@ -429,22 +445,26 @@ define void @and_ule_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign
define void @and_sge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: and_sge_ne:
; RV32I: # %bb.0:
-; RV32I-NEXT: blt a0, a1, .LBB17_3
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: slt a0, a0, a1
+; RV32I-NEXT: seqz a1, a2
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: bnez a0, .LBB17_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: beq a2, a3, .LBB17_3
-; RV32I-NEXT: # %bb.2:
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB17_3:
+; RV32I-NEXT: .LBB17_2:
; RV32I-NEXT: tail bar
;
; RV64I-LABEL: and_sge_ne:
; RV64I: # %bb.0:
-; RV64I-NEXT: blt a0, a1, .LBB17_3
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: slt a0, a0, a1
+; RV64I-NEXT: seqz a1, a2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: bnez a0, .LBB17_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: beq a2, a3, .LBB17_3
-; RV64I-NEXT: # %bb.2:
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB17_3:
+; RV64I-NEXT: .LBB17_2:
; RV64I-NEXT: tail bar
%5 = icmp sge i32 %0, %1
%6 = icmp ne i32 %2, %3
@@ -462,22 +482,26 @@ define void @and_sge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign
define void @and_sle_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: and_sle_ne:
; RV32I: # %bb.0:
-; RV32I-NEXT: blt a1, a0, .LBB18_3
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: slt a0, a1, a0
+; RV32I-NEXT: seqz a1, a2
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: bnez a0, .LBB18_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: beq a2, a3, .LBB18_3
-; RV32I-NEXT: # %bb.2:
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB18_3:
+; RV32I-NEXT: .LBB18_2:
; RV32I-NEXT: tail bar
;
; RV64I-LABEL: and_sle_ne:
; RV64I: # %bb.0:
-; RV64I-NEXT: blt a1, a0, .LBB18_3
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: slt a0, a1, a0
+; RV64I-NEXT: seqz a1, a2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: bnez a0, .LBB18_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: beq a2, a3, .LBB18_3
-; RV64I-NEXT: # %bb.2:
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB18_3:
+; RV64I-NEXT: .LBB18_2:
; RV64I-NEXT: tail bar
%5 = icmp sle i32 %0, %1
%6 = icmp ne i32 %2, %3
@@ -495,22 +519,26 @@ define void @and_sle_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign
define void @and_uge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: and_uge_ne:
; RV32I: # %bb.0:
-; RV32I-NEXT: bltu a0, a1, .LBB19_3
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: sltu a0, a0, a1
+; RV32I-NEXT: seqz a1, a2
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: bnez a0, .LBB19_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: beq a2, a3, .LBB19_3
-; RV32I-NEXT: # %bb.2:
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB19_3:
+; RV32I-NEXT: .LBB19_2:
; RV32I-NEXT: tail bar
;
; RV64I-LABEL: and_uge_ne:
; RV64I: # %bb.0:
-; RV64I-NEXT: bltu a0, a1, .LBB19_3
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: sltu a0, a0, a1
+; RV64I-NEXT: seqz a1, a2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: bnez a0, .LBB19_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: beq a2, a3, .LBB19_3
-; RV64I-NEXT: # %bb.2:
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB19_3:
+; RV64I-NEXT: .LBB19_2:
; RV64I-NEXT: tail bar
%5 = icmp uge i32 %0, %1
%6 = icmp ne i32 %2, %3
@@ -528,22 +556,26 @@ define void @and_uge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign
define void @and_ule_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: and_ule_ne:
; RV32I: # %bb.0:
-; RV32I-NEXT: bltu a1, a0, .LBB20_3
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: sltu a0, a1, a0
+; RV32I-NEXT: seqz a1, a2
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: bnez a0, .LBB20_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: beq a2, a3, .LBB20_3
-; RV32I-NEXT: # %bb.2:
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB20_3:
+; RV32I-NEXT: .LBB20_2:
; RV32I-NEXT: tail bar
;
; RV64I-LABEL: and_ule_ne:
; RV64I: # %bb.0:
-; RV64I-NEXT: bltu a1, a0, .LBB20_3
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: sltu a0, a1, a0
+; RV64I-NEXT: seqz a1, a2
+; RV64I-NEXT: or a0, a1, a0
+; RV64I-NEXT: bnez a0, .LBB20_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: beq a2, a3, .LBB20_3
-; RV64I-NEXT: # %bb.2:
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB20_3:
+; RV64I-NEXT: .LBB20_2:
; RV64I-NEXT: tail bar
%5 = icmp ule i32 %0, %1
%6 = icmp ne i32 %2, %3
@@ -561,23 +593,27 @@ define void @and_ule_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign
define void @or_sge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: or_sge_eq:
; RV32I: # %bb.0:
-; RV32I-NEXT: bge a0, a1, .LBB21_3
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: slt a0, a0, a1
+; RV32I-NEXT: snez a1, a2
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: bnez a0, .LBB21_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: beq a2, a3, .LBB21_3
-; RV32I-NEXT: # %bb.2:
-; RV32I-NEXT: tail bar
-; RV32I-NEXT: .LBB21_3:
; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB21_2:
+; RV32I-NEXT: tail bar
;
; RV64I-LABEL: or_sge_eq:
; RV64I: # %bb.0:
-; RV64I-NEXT: bge a0, a1, .LBB21_3
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: slt a0, a0, a1
+; RV64I-NEXT: snez a1, a2
+; RV64I-NEXT: and a0, a1, a0
+; RV64I-NEXT: bnez a0, .LBB21_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: beq a2, a3, .LBB21_3
-; RV64I-NEXT: # %bb.2:
-; RV64I-NEXT: tail bar
-; RV64I-NEXT: .LBB21_3:
; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB21_2:
+; RV64I-NEXT: tail bar
%5 = icmp sge i32 %0, %1
%6 = icmp eq i32 %2, %3
%7 = or i1 %5, %6
@@ -594,23 +630,27 @@ define void @or_sge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signe
define void @or_sle_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: or_sle_eq:
; RV32I: # %bb.0:
-; RV32I-NEXT: bge a1, a0, .LBB22_3
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: slt a0, a1, a0
+; RV32I-NEXT: snez a1, a2
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: bnez a0, .LBB22_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: beq a2, a3, .LBB22_3
-; RV32I-NEXT: # %bb.2:
-; RV32I-NEXT: tail bar
-; RV32I-NEXT: .LBB22_3:
; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB22_2:
+; RV32I-NEXT: tail bar
;
; RV64I-LABEL: or_sle_eq:
; RV64I: # %bb.0:
-; RV64I-NEXT: bge a1, a0, .LBB22_3
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: slt a0, a1, a0
+; RV64I-NEXT: snez a1, a2
+; RV64I-NEXT: and a0, a1, a0
+; RV64I-NEXT: bnez a0, .LBB22_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: beq a2, a3, .LBB22_3
-; RV64I-NEXT: # %bb.2:
-; RV64I-NEXT: tail bar
-; RV64I-NEXT: .LBB22_3:
; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB22_2:
+; RV64I-NEXT: tail bar
%5 = icmp sle i32 %0, %1
%6 = icmp eq i32 %2, %3
%7 = or i1 %5, %6
@@ -627,23 +667,27 @@ define void @or_sle_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signe
define void @or_uge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: or_uge_eq:
; RV32I: # %bb.0:
-; RV32I-NEXT: bgeu a0, a1, .LBB23_3
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: sltu a0, a0, a1
+; RV32I-NEXT: snez a1, a2
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: bnez a0, .LBB23_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: beq a2, a3, .LBB23_3
-; RV32I-NEXT: # %bb.2:
-; RV32I-NEXT: tail bar
-; RV32I-NEXT: .LBB23_3:
; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB23_2:
+; RV32I-NEXT: tail bar
;
; RV64I-LABEL: or_uge_eq:
; RV64I: # %bb.0:
-; RV64I-NEXT: bgeu a0, a1, .LBB23_3
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: sltu a0, a0, a1
+; RV64I-NEXT: snez a1, a2
+; RV64I-NEXT: and a0, a1, a0
+; RV64I-NEXT: bnez a0, .LBB23_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: beq a2, a3, .LBB23_3
-; RV64I-NEXT: # %bb.2:
-; RV64I-NEXT: tail bar
-; RV64I-NEXT: .LBB23_3:
; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB23_2:
+; RV64I-NEXT: tail bar
%5 = icmp uge i32 %0, %1
%6 = icmp eq i32 %2, %3
%7 = or i1 %5, %6
@@ -660,23 +704,27 @@ define void @or_uge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signe
define void @or_ule_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: or_ule_eq:
; RV32I: # %bb.0:
-; RV32I-NEXT: bgeu a1, a0, .LBB24_3
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: sltu a0, a1, a0
+; RV32I-NEXT: snez a1, a2
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: bnez a0, .LBB24_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: beq a2, a3, .LBB24_3
-; RV32I-NEXT: # %bb.2:
-; RV32I-NEXT: tail bar
-; RV32I-NEXT: .LBB24_3:
; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB24_2:
+; RV32I-NEXT: tail bar
;
; RV64I-LABEL: or_ule_eq:
; RV64I: # %bb.0:
-; RV64I-NEXT: bgeu a1, a0, .LBB24_3
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: sltu a0, a1, a0
+; RV64I-NEXT: snez a1, a2
+; RV64I-NEXT: and a0, a1, a0
+; RV64I-NEXT: bnez a0, .LBB24_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: beq a2, a3, .LBB24_3
-; RV64I-NEXT: # %bb.2:
-; RV64I-NEXT: tail bar
-; RV64I-NEXT: .LBB24_3:
; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB24_2:
+; RV64I-NEXT: tail bar
%5 = icmp ule i32 %0, %1
%6 = icmp eq i32 %2, %3
%7 = or i1 %5, %6
@@ -693,23 +741,27 @@ define void @or_ule_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signe
define void @or_sge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: or_sge_ne:
; RV32I: # %bb.0:
-; RV32I-NEXT: bge a0, a1, .LBB25_3
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: slt a0, a0, a1
+; RV32I-NEXT: seqz a1, a2
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: bnez a0, .LBB25_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: bne a2, a3, .LBB25_3
-; RV32I-NEXT: # %bb.2:
-; RV32I-NEXT: tail bar
-; RV32I-NEXT: .LBB25_3:
; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB25_2:
+; RV32I-NEXT: tail bar
;
; RV64I-LABEL: or_sge_ne:
; RV64I: # %bb.0:
-; RV64I-NEXT: bge a0, a1, .LBB25_3
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: slt a0, a0, a1
+; RV64I-NEXT: seqz a1, a2
+; RV64I-NEXT: and a0, a1, a0
+; RV64I-NEXT: bnez a0, .LBB25_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: bne a2, a3, .LBB25_3
-; RV64I-NEXT: # %bb.2:
-; RV64I-NEXT: tail bar
-; RV64I-NEXT: .LBB25_3:
; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB25_2:
+; RV64I-NEXT: tail bar
%5 = icmp sge i32 %0, %1
%6 = icmp ne i32 %2, %3
%7 = or i1 %5, %6
@@ -726,23 +778,27 @@ define void @or_sge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signe
define void @or_sle_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: or_sle_ne:
; RV32I: # %bb.0:
-; RV32I-NEXT: bge a1, a0, .LBB26_3
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: slt a0, a1, a0
+; RV32I-NEXT: seqz a1, a2
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: bnez a0, .LBB26_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: bne a2, a3, .LBB26_3
-; RV32I-NEXT: # %bb.2:
-; RV32I-NEXT: tail bar
-; RV32I-NEXT: .LBB26_3:
; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB26_2:
+; RV32I-NEXT: tail bar
;
; RV64I-LABEL: or_sle_ne:
; RV64I: # %bb.0:
-; RV64I-NEXT: bge a1, a0, .LBB26_3
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: slt a0, a1, a0
+; RV64I-NEXT: seqz a1, a2
+; RV64I-NEXT: and a0, a1, a0
+; RV64I-NEXT: bnez a0, .LBB26_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: bne a2, a3, .LBB26_3
-; RV64I-NEXT: # %bb.2:
-; RV64I-NEXT: tail bar
-; RV64I-NEXT: .LBB26_3:
; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB26_2:
+; RV64I-NEXT: tail bar
%5 = icmp sle i32 %0, %1
%6 = icmp ne i32 %2, %3
%7 = or i1 %5, %6
@@ -759,23 +815,27 @@ define void @or_sle_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signe
define void @or_uge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: or_uge_ne:
; RV32I: # %bb.0:
-; RV32I-NEXT: bgeu a0, a1, .LBB27_3
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: sltu a0, a0, a1
+; RV32I-NEXT: seqz a1, a2
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: bnez a0, .LBB27_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: bne a2, a3, .LBB27_3
-; RV32I-NEXT: # %bb.2:
-; RV32I-NEXT: tail bar
-; RV32I-NEXT: .LBB27_3:
; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB27_2:
+; RV32I-NEXT: tail bar
;
; RV64I-LABEL: or_uge_ne:
; RV64I: # %bb.0:
-; RV64I-NEXT: bgeu a0, a1, .LBB27_3
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: sltu a0, a0, a1
+; RV64I-NEXT: seqz a1, a2
+; RV64I-NEXT: and a0, a1, a0
+; RV64I-NEXT: bnez a0, .LBB27_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: bne a2, a3, .LBB27_3
-; RV64I-NEXT: # %bb.2:
-; RV64I-NEXT: tail bar
-; RV64I-NEXT: .LBB27_3:
; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB27_2:
+; RV64I-NEXT: tail bar
%5 = icmp uge i32 %0, %1
%6 = icmp ne i32 %2, %3
%7 = or i1 %5, %6
@@ -792,23 +852,27 @@ define void @or_uge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signe
define void @or_ule_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: or_ule_ne:
; RV32I: # %bb.0:
-; RV32I-NEXT: bgeu a1, a0, .LBB28_3
+; RV32I-NEXT: xor a2, a2, a3
+; RV32I-NEXT: sltu a0, a1, a0
+; RV32I-NEXT: seqz a1, a2
+; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: bnez a0, .LBB28_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: bne a2, a3, .LBB28_3
-; RV32I-NEXT: # %bb.2:
-; RV32I-NEXT: tail bar
-; RV32I-NEXT: .LBB28_3:
; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB28_2:
+; RV32I-NEXT: tail bar
;
; RV64I-LABEL: or_ule_ne:
; RV64I: # %bb.0:
-; RV64I-NEXT: bgeu a1, a0, .LBB28_3
+; RV64I-NEXT: xor a2, a2, a3
+; RV64I-NEXT: sltu a0, a1, a0
+; RV64I-NEXT: seqz a1, a2
+; RV64I-NEXT: and a0, a1, a0
+; RV64I-NEXT: bnez a0, .LBB28_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: bne a2, a3, .LBB28_3
-; RV64I-NEXT: # %bb.2:
-; RV64I-NEXT: tail bar
-; RV64I-NEXT: .LBB28_3:
; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB28_2:
+; RV64I-NEXT: tail bar
%5 = icmp ule i32 %0, %1
%6 = icmp ne i32 %2, %3
%7 = or i1 %5, %6
@@ -825,22 +889,26 @@ define void @or_ule_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signe
define void @and_eq_sge(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: and_eq_sge:
; RV32I: # %bb.0:
-; RV32I-NEXT: bne a0, a1, .LBB29_3
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: snez a0, a0
+; RV32I-NEXT: slt a1, a2, a3
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: bnez a0, .LBB29_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: blt a2, a3, .LBB29_3
-; RV32I-NEXT: # %bb.2:
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB29_3:
+; RV32I-NEXT: .LBB29_2:
; RV32I-NEXT: tail bar
;
; RV64I-LABEL: and_eq_sge:
; RV64I: # %bb.0:
-; RV64I-NEXT: bne a0, a1, .LBB29_3
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: snez a0, a0
+; RV64I-NEXT: slt a1, a2, a3
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: bnez a0, .LBB29_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: blt a2, a3, .LBB29_3
-; RV64I-NEXT: # %bb.2:
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB29_3:
+; RV64I-NEXT: .LBB29_2:
; RV64I-NEXT: tail bar
%5 = icmp eq i32 %0, %1
%6 = icmp sge i32 %2, %3
@@ -858,22 +926,26 @@ define void @and_eq_sge(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign
define void @and_eq_sle(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: and_eq_sle:
; RV32I: # %bb.0:
-; RV32I-NEXT: bne a0, a1, .LBB30_3
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: snez a0, a0
+; RV32I-NEXT: slt a1, a3, a2
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: bnez a0, .LBB30_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: blt a3, a2, .LBB30_3
-; RV32I-NEXT: # %bb.2:
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB30_3:
+; RV32I-NEXT: .LBB30_2:
; RV32I-NEXT: tail bar
;
; RV64I-LABEL: and_eq_sle:
; RV64I: # %bb.0:
-; RV64I-NEXT: bne a0, a1, .LBB30_3
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: snez a0, a0
+; RV64I-NEXT: slt a1, a3, a2
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: bnez a0, .LBB30_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: blt a3, a2, .LBB30_3
-; RV64I-NEXT: # %bb.2:
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB30_3:
+; RV64I-NEXT: .LBB30_2:
; RV64I-NEXT: tail bar
%5 = icmp eq i32 %0, %1
%6 = icmp sle i32 %2, %3
@@ -891,22 +963,26 @@ define void @and_eq_sle(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign
define void @and_eq_uge(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: and_eq_uge:
; RV32I: # %bb.0:
-; RV32I-NEXT: bne a0, a1, .LBB31_3
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: snez a0, a0
+; RV32I-NEXT: sltu a1, a2, a3
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: bnez a0, .LBB31_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: bltu a2, a3, .LBB31_3
-; RV32I-NEXT: # %bb.2:
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB31_3:
+; RV32I-NEXT: .LBB31_2:
; RV32I-NEXT: tail bar
;
; RV64I-LABEL: and_eq_uge:
; RV64I: # %bb.0:
-; RV64I-NEXT: bne a0, a1, .LBB31_3
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: snez a0, a0
+; RV64I-NEXT: sltu a1, a2, a3
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: bnez a0, .LBB31_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: bltu a2, a3, .LBB31_3
-; RV64I-NEXT: # %bb.2:
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB31_3:
+; RV64I-NEXT: .LBB31_2:
; RV64I-NEXT: tail bar
%5 = icmp eq i32 %0, %1
%6 = icmp uge i32 %2, %3
@@ -924,22 +1000,26 @@ define void @and_eq_uge(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign
define void @and_eq_ule(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: and_eq_ule:
; RV32I: # %bb.0:
-; RV32I-NEXT: bne a0, a1, .LBB32_3
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: snez a0, a0
+; RV32I-NEXT: sltu a1, a3, a2
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: bnez a0, .LBB32_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: bltu a3, a2, .LBB32_3
-; RV32I-NEXT: # %bb.2:
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB32_3:
+; RV32I-NEXT: .LBB32_2:
; RV32I-NEXT: tail bar
;
; RV64I-LABEL: and_eq_ule:
; RV64I: # %bb.0:
-; RV64I-NEXT: bne a0, a1, .LBB32_3
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: snez a0, a0
+; RV64I-NEXT: sltu a1, a3, a2
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: bnez a0, .LBB32_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: bltu a3, a2, .LBB32_3
-; RV64I-NEXT: # %bb.2:
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB32_3:
+; RV64I-NEXT: .LBB32_2:
; RV64I-NEXT: tail bar
%5 = icmp eq i32 %0, %1
%6 = icmp ule i32 %2, %3
@@ -957,22 +1037,26 @@ define void @and_eq_ule(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign
define void @and_ne_sge(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: and_ne_sge:
; RV32I: # %bb.0:
-; RV32I-NEXT: beq a0, a1, .LBB33_3
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: slt a1, a2, a3
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: bnez a0, .LBB33_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: blt a2, a3, .LBB33_3
-; RV32I-NEXT: # %bb.2:
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB33_3:
+; RV32I-NEXT: .LBB33_2:
; RV32I-NEXT: tail bar
;
; RV64I-LABEL: and_ne_sge:
; RV64I: # %bb.0:
-; RV64I-NEXT: beq a0, a1, .LBB33_3
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: slt a1, a2, a3
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: bnez a0, .LBB33_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: blt a2, a3, .LBB33_3
-; RV64I-NEXT: # %bb.2:
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB33_3:
+; RV64I-NEXT: .LBB33_2:
; RV64I-NEXT: tail bar
%5 = icmp ne i32 %0, %1
%6 = icmp sge i32 %2, %3
@@ -990,22 +1074,26 @@ define void @and_ne_sge(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign
define void @and_ne_sle(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: and_ne_sle:
; RV32I: # %bb.0:
-; RV32I-NEXT: beq a0, a1, .LBB34_3
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: slt a1, a3, a2
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: bnez a0, .LBB34_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: blt a3, a2, .LBB34_3
-; RV32I-NEXT: # %bb.2:
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB34_3:
+; RV32I-NEXT: .LBB34_2:
; RV32I-NEXT: tail bar
;
; RV64I-LABEL: and_ne_sle:
; RV64I: # %bb.0:
-; RV64I-NEXT: beq a0, a1, .LBB34_3
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: slt a1, a3, a2
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: bnez a0, .LBB34_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: blt a3, a2, .LBB34_3
-; RV64I-NEXT: # %bb.2:
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB34_3:
+; RV64I-NEXT: .LBB34_2:
; RV64I-NEXT: tail bar
%5 = icmp ne i32 %0, %1
%6 = icmp sle i32 %2, %3
@@ -1023,22 +1111,26 @@ define void @and_ne_sle(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign
define void @and_ne_uge(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: and_ne_uge:
; RV32I: # %bb.0:
-; RV32I-NEXT: beq a0, a1, .LBB35_3
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: sltu a1, a2, a3
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: bnez a0, .LBB35_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: bltu a2, a3, .LBB35_3
-; RV32I-NEXT: # %bb.2:
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB35_3:
+; RV32I-NEXT: .LBB35_2:
; RV32I-NEXT: tail bar
;
; RV64I-LABEL: and_ne_uge:
; RV64I: # %bb.0:
-; RV64I-NEXT: beq a0, a1, .LBB35_3
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: sltu a1, a2, a3
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: bnez a0, .LBB35_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: bltu a2, a3, .LBB35_3
-; RV64I-NEXT: # %bb.2:
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB35_3:
+; RV64I-NEXT: .LBB35_2:
; RV64I-NEXT: tail bar
%5 = icmp ne i32 %0, %1
%6 = icmp uge i32 %2, %3
@@ -1056,22 +1148,26 @@ define void @and_ne_uge(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign
define void @and_ne_ule(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; RV32I-LABEL: and_ne_ule:
; RV32I: # %bb.0:
-; RV32I-NEXT: beq a0, a1, .LBB36_3
+; RV32I-NEXT: xor a0, a0, a1
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: sltu a1, a3, a2
+; RV32I-NEXT: or a0, a0, a1
+; RV32I-NEXT: bnez a0, .LBB36_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: bltu a3, a2, .LBB36_3
-; RV32I-NEXT: # %bb.2:
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB36_3:
+; RV32I-NEXT: .LBB36_2:
; RV32I-NEXT: tail bar
;
; RV64I-LABEL: and_ne_ule:
; RV64I: # %bb.0:
-; RV64I-NEXT: beq a0, a1, .LBB36_3
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: seqz a0, a0
+; RV64I-NEXT: sltu a1, a3, a2
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: bnez a0, .LBB36_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: bltu a3, a2, .LBB36_3
-; RV64I-NEXT: # %bb.2:
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB36_3:
+; RV64I-NEXT: .LBB36_2:
; RV64I-NEXT: tail bar
%5 = icmp ne i32 %0, %1
%6 = icmp ule i32 %2, %3
@@ -1089,22 +1185,24 @@ define void @and_ne_ule(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign
define void @and_sge_gt0(i32 signext %0, i32 signext %1, i32 signext %2) {
; RV32I-LABEL: and_sge_gt0:
; RV32I: # %bb.0:
-; RV32I-NEXT: blt a0, a1, .LBB37_3
+; RV32I-NEXT: slti a2, a2, 1
+; RV32I-NEXT: slt a0, a0, a1
+; RV32I-NEXT: or a0, a2, a0
+; RV32I-NEXT: bnez a0, .LBB37_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: blez a2, .LBB37_3
-; RV32I-NEXT: # %bb.2:
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB37_3:
+; RV32I-NEXT: .LBB37_2:
; RV32I-NEXT: tail bar
;
; RV64I-LABEL: and_sge_gt0:
; RV64I: # %bb.0:
-; RV64I-NEXT: blt a0, a1, .LBB37_3
+; RV64I-NEXT: slti a2, a2, 1
+; RV64I-NEXT: slt a0, a0, a1
+; RV64I-NEXT: or a0, a2, a0
+; RV64I-NEXT: bnez a0, .LBB37_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: blez a2, .LBB37_3
-; RV64I-NEXT: # %bb.2:
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB37_3:
+; RV64I-NEXT: .LBB37_2:
; RV64I-NEXT: tail bar
%4 = icmp sge i32 %0, %1
%5 = icmp sgt i32 %2, 0
@@ -1122,22 +1220,24 @@ define void @and_sge_gt0(i32 signext %0, i32 signext %1, i32 signext %2) {
define void @and_sle_lt1(i32 signext %0, i32 signext %1, i32 signext %2) {
; RV32I-LABEL: and_sle_lt1:
; RV32I: # %bb.0:
-; RV32I-NEXT: blt a1, a0, .LBB38_3
+; RV32I-NEXT: sgtz a2, a2
+; RV32I-NEXT: slt a0, a1, a0
+; RV32I-NEXT: or a0, a2, a0
+; RV32I-NEXT: bnez a0, .LBB38_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: bgtz a2, .LBB38_3
-; RV32I-NEXT: # %bb.2:
; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB38_3:
+; RV32I-NEXT: .LBB38_2:
; RV32I-NEXT: tail bar
;
; RV64I-LABEL: and_sle_lt1:
; RV64I: # %bb.0:
-; RV64I-NEXT: blt a1, a0, .LBB38_3
+; RV64I-NEXT: sgtz a2, a2
+; RV64I-NEXT: slt a0, a1, a0
+; RV64I-NEXT: or a0, a2, a0
+; RV64I-NEXT: bnez a0, .LBB38_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: bgtz a2, .LBB38_3
-; RV64I-NEXT: # %bb.2:
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB38_3:
+; RV64I-NEXT: .LBB38_2:
; RV64I-NEXT: tail bar
%4 = icmp sle i32 %0, %1
%5 = icmp slt i32 %2, 1
@@ -1155,23 +1255,25 @@ define void @and_sle_lt1(i32 signext %0, i32 signext %1, i32 signext %2) {
define void @or_uge_gt0(i32 signext %0, i32 signext %1, i32 signext %2) {
; RV32I-LABEL: or_uge_gt0:
; RV32I: # %bb.0:
-; RV32I-NEXT: bgeu a0, a1, .LBB39_3
+; RV32I-NEXT: slti a2, a2, 1
+; RV32I-NEXT: sltu a0, a0, a1
+; RV32I-NEXT: and a0, a2, a0
+; RV32I-NEXT: bnez a0, .LBB39_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: bgtz a2, .LBB39_3
-; RV32I-NEXT: # %bb.2:
-; RV32I-NEXT: tail bar
-; RV32I-NEXT: .LBB39_3:
; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB39_2:
+; RV32I-NEXT: tail bar
;
; RV64I-LABEL: or_uge_gt0:
; RV64I: # %bb.0:
-; RV64I-NEXT: bgeu a0, a1, .LBB39_3
+; RV64I-NEXT: slti a2, a2, 1
+; RV64I-NEXT: sltu a0, a0, a1
+; RV64I-NEXT: and a0, a2, a0
+; RV64I-NEXT: bnez a0, .LBB39_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: bgtz a2, .LBB39_3
-; RV64I-NEXT: # %bb.2:
-; RV64I-NEXT: tail bar
-; RV64I-NEXT: .LBB39_3:
; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB39_2:
+; RV64I-NEXT: tail bar
%4 = icmp uge i32 %0, %1
%5 = icmp sgt i32 %2, 0
%6 = or i1 %4, %5
@@ -1188,23 +1290,25 @@ define void @or_uge_gt0(i32 signext %0, i32 signext %1, i32 signext %2) {
define void @or_ule_lt1(i32 signext %0, i32 signext %1, i32 signext %2) {
; RV32I-LABEL: or_ule_lt1:
; RV32I: # %bb.0:
-; RV32I-NEXT: bgeu a1, a0, .LBB40_3
+; RV32I-NEXT: sgtz a2, a2
+; RV32I-NEXT: sltu a0, a1, a0
+; RV32I-NEXT: and a0, a2, a0
+; RV32I-NEXT: bnez a0, .LBB40_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: blez a2, .LBB40_3
-; RV32I-NEXT: # %bb.2:
-; RV32I-NEXT: tail bar
-; RV32I-NEXT: .LBB40_3:
; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB40_2:
+; RV32I-NEXT: tail bar
;
; RV64I-LABEL: or_ule_lt1:
; RV64I: # %bb.0:
-; RV64I-NEXT: bgeu a1, a0, .LBB40_3
+; RV64I-NEXT: sgtz a2, a2
+; RV64I-NEXT: sltu a0, a1, a0
+; RV64I-NEXT: and a0, a2, a0
+; RV64I-NEXT: bnez a0, .LBB40_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: blez a2, .LBB40_3
-; RV64I-NEXT: # %bb.2:
-; RV64I-NEXT: tail bar
-; RV64I-NEXT: .LBB40_3:
; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB40_2:
+; RV64I-NEXT: tail bar
%4 = icmp ule i32 %0, %1
%5 = icmp slt i32 %2, 1
%6 = or i1 %4, %5
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