[llvm] [NFC][SPIR-V] Add constrainSelectedInstRegOperands helper to dedup repeating pattern in global registry (PR #208703)

[Juan Manuel Martinez Caamaño via llvm-commits]

https://github.com/jmmartinez commented:

I'm ok with this. But maybe add another reviewer.

We could also use the `MachineInstrBuilder::constrainAllUses(const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)`.

I wonder if we should add these members to the `GlobalRegistry` in the same way as it is done to `SPIRVInstructionSelector`:

```cpp
  const SPIRVSubtarget &STI;
  const SPIRVInstrInfo &TII;
  const SPIRVRegisterInfo &TRI;
  const RegisterBankInfo &RBI;
```

* The subtarget we use it in the `GlobalRegistry` also every time we want to check anything about the extensions.
* `SPIRVInstrInfo` we use it for several helpers that create instructions.
* `SPIRVRegisterInfo` every time we want to create a generic virtual register (either though `MF.getRegInfo` or `MachineIRBuilder::getMRI`).
* `RegisterBankInfo` is harder to justify.

We could add this fields, reduce a bit the redundancy in the code, and maybe we realize the helper is not even needed anymore because we end up with something much more compact:

```cpp
MIB.constrainAllUses(TII, TRI, ST.getRegBankInfo());
```

---

On a totally different level, I've always wondered what if we removed all the calls to `constrainSelectedInstRegOperands` / `constrainAllUses` ?

SPIRV is the backend that is calling these in the most number of places; but it is also the one where I'd expect the least amount of copies between register classes.

```bash
$ grep -r -E "constrainAllUses|constrainSelectedInstRegOperands" | cut -d":" -f1 | uniq -c | sort -n
      1 lib/Target/Mips/MipsLegalizerInfo.cpp
      2 include/llvm/CodeGen/MachineInstrBuilder.h
      2 lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
      2 lib/Target/SPIRV/SPIRVCallLowering.cpp
      2 lib/Target/SPIRV/SPIRVISelLowering.cpp
      6 lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
     18 lib/Target/ARM/ARMInstructionSelector.cpp
     18 lib/Target/X86/GISel/X86InstructionSelector.cpp
     33 lib/Target/Mips/MipsInstructionSelector.cpp
     36 lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
     38 lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
     42 lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
     96 lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    191 lib/Target/SPIRV/SPIRVInstructionSelector.cpp
```

https://github.com/llvm/llvm-project/pull/208703