[llvm] [RISCV][P-ext] Replace lowerBuildVectorAsRV32PNarrowingShift with shuffle lowering. (PR #209088)

[Hongyu Chen via llvm-commits]

================
@@ -6424,6 +6377,58 @@ static SDValue lowerVECTOR_SHUFFLEAsPUnzip(ShuffleVectorSDNode *SVN,
   return DAG.getNode(Opc, DL, VT, V1, V2);
 }
 
+// Match a legalized single-source deinterleave shuffle where the source
+// vector was split into two extract_subvectors of the same vector, e.g.
+//   t20: v4i8 = extract_subvector t5, 0
+//   t19: v4i8 = extract_subvector t5, 4
+//   t21: v4i8 = vector_shuffle<0,2,4,6> t20, t19
+// and lower it to an RV32 P narrowing shift on the original source.
+static SDValue
+lowerVECTOR_SHUFFLEAsRV32PNarrowingShift(ShuffleVectorSDNode *SVN,
+                                         SelectionDAG &DAG) {
+  MVT VT = SVN->getSimpleValueType(0);
+  if (VT != MVT::v4i8 && VT != MVT::v2i16)
+    return SDValue();
+
+  SDValue V1 = SVN->getOperand(0);
+  SDValue V2 = SVN->getOperand(1);
+  if (V1.getOpcode() != ISD::EXTRACT_SUBVECTOR ||
+      V2.getOpcode() != ISD::EXTRACT_SUBVECTOR ||
+      V1.getOperand(0) != V2.getOperand(0))
+    return SDValue();
+
+  SDValue Src = V1.getOperand(0);
+  MVT SrcVT = VT == MVT::v4i8 ? MVT::v8i8 : MVT::v4i16;
+  if (Src.getSimpleValueType() != SrcVT)
+    return SDValue();
+
+  unsigned NumElts = VT.getVectorNumElements();
+  unsigned V1Index = V1.getConstantOperandVal(1);
+  unsigned V2Index = V2.getConstantOperandVal(1);
+  if ((V1Index != 0 || V2Index != NumElts) &&
----------------
XChy wrote:

Is this the correctness check or the profitability check? The pattern below is also equivalent to a deinterleave shuffle.
```
t20: v4i8 = extract_subvector t5, 1
t19: v4i8 = extract_subvector t5, 4
t21: v4i8 = vector_shuffle<0,2,5,7> t20, t19
```

https://github.com/llvm/llvm-project/pull/209088