[llvm] [SCEV][NFC] Address post-merge comments on precommit test (PR #209094)
Aleksandr Popov via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 13 01:00:43 PDT 2026
https://github.com/aleks-tmb updated https://github.com/llvm/llvm-project/pull/209094
>From f79bd3743723821e1b4b68e4a99e4f155f529c07 Mon Sep 17 00:00:00 2001
From: Aleksandr Popov <apopov at azul.com>
Date: Mon, 13 Jul 2026 06:49:14 +0000
Subject: [PATCH] [SCEV][NFC] Address post-merge comments on precommit test
Drop unnecessary atomic/unordered loads, unify block label naming, and
regenerate CHECK lines with update_test_checks.py v6.
Follow-up to b33af86b032e (#208784).
---
.../single_early_exit_zext_trip_count.ll | 98 +++++++++----------
1 file changed, 49 insertions(+), 49 deletions(-)
diff --git a/llvm/test/Transforms/LoopVectorize/single_early_exit_zext_trip_count.ll b/llvm/test/Transforms/LoopVectorize/single_early_exit_zext_trip_count.ll
index 2ea1fc2e34729..59fe0321c0112 100644
--- a/llvm/test/Transforms/LoopVectorize/single_early_exit_zext_trip_count.ll
+++ b/llvm/test/Transforms/LoopVectorize/single_early_exit_zext_trip_count.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 4
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
; RUN: opt -S < %s -p loop-vectorize -force-vector-width=4 | FileCheck %s
; assume(dereferenceable(p, zext(len + 8)));
@@ -17,36 +17,36 @@
define void @test1(ptr %p) {
; CHECK-LABEL: define void @test1(
; CHECK-SAME: ptr [[P:%.*]]) {
-; CHECK-NEXT: entry:
+; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[BASE:%.*]] = getelementptr inbounds nuw i8, ptr [[P]], i64 8
-; CHECK-NEXT: [[LEN:%.*]] = load atomic i32, ptr [[BASE]] unordered, align 4, !range [[RNG0:![0-9]+]]
+; CHECK-NEXT: [[LEN:%.*]] = load i32, ptr [[BASE]], align 4, !range [[RNG0:![0-9]+]]
; CHECK-NEXT: [[LEN_PLUS_8:%.*]] = add nuw nsw i32 [[LEN]], 8
; CHECK-NEXT: [[LEN_PLUS_8_WIDE:%.*]] = zext i32 [[LEN_PLUS_8]] to i64
; CHECK-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(ptr [[P]], i64 [[LEN_PLUS_8_WIDE]]) ]
; CHECK-NEXT: [[LEN_IS_ZERO:%.*]] = icmp eq i32 [[LEN]], 0
-; CHECK-NEXT: br i1 [[LEN_IS_ZERO]], label [[RET:%.*]], label [[PREHEADER:%.*]]
-; CHECK: preheader:
+; CHECK-NEXT: br i1 [[LEN_IS_ZERO]], label %[[RET:.*]], label %[[PREHEADER:.*]]
+; CHECK: [[PREHEADER]]:
; CHECK-NEXT: [[EXIT_32:%.*]] = add nsw i32 [[LEN]], -1
; CHECK-NEXT: [[EXIT:%.*]] = zext i32 [[EXIT_32]] to i64
-; CHECK-NEXT: br label [[LOOP:%.*]]
-; CHECK: loop:
-; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ], [ 0, [[PREHEADER]] ]
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ], [ 0, %[[PREHEADER]] ]
; CHECK-NEXT: [[ELEM_PTR:%.*]] = getelementptr inbounds nuw i8, ptr [[BASE]], i64 [[IV]]
; CHECK-NEXT: [[ELEM:%.*]] = load i8, ptr [[ELEM_PTR]], align 1
; CHECK-NEXT: [[IS_TARGET:%.*]] = icmp eq i8 [[ELEM]], 0
-; CHECK-NEXT: br i1 [[IS_TARGET]], label [[DEOPT:%.*]], label [[LATCH]]
-; CHECK: latch:
+; CHECK-NEXT: br i1 [[IS_TARGET]], label %[[RET_LOOPEXIT:.*]], label %[[LATCH]]
+; CHECK: [[LATCH]]:
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ult i64 [[IV]], [[EXIT]]
-; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[DEOPT]]
-; CHECK: ret.loopexit:
-; CHECK-NEXT: br label [[RET]]
-; CHECK: ret:
+; CHECK-NEXT: br i1 [[LOOP_COND]], label %[[LOOP]], label %[[RET_LOOPEXIT]]
+; CHECK: [[RET_LOOPEXIT]]:
+; CHECK-NEXT: br label %[[RET]]
+; CHECK: [[RET]]:
; CHECK-NEXT: ret void
;
entry:
%base = getelementptr inbounds nuw i8, ptr %p, i64 8
- %len = load atomic i32, ptr %base unordered, align 4, !range !0
+ %len = load i32, ptr %base, align 4, !range !0
%len.plus.8 = add nuw nsw i32 %len, 8
%len.plus.8.wide = zext i32 %len.plus.8 to i64
call void @llvm.assume(i1 true) [ "dereferenceable"(ptr %p, i64 %len.plus.8.wide) ]
@@ -97,66 +97,66 @@ ret:
define void @test2(ptr %p, i32 %A) {
; CHECK-LABEL: define void @test2(
; CHECK-SAME: ptr [[P:%.*]], i32 [[A:%.*]]) {
-; CHECK-NEXT: entry:
+; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[BASE:%.*]] = getelementptr inbounds nuw i8, ptr [[P]], i64 8
-; CHECK-NEXT: [[LEN:%.*]] = load atomic i32, ptr [[BASE]] unordered, align 4, !range [[RNG0]]
+; CHECK-NEXT: [[LEN:%.*]] = load i32, ptr [[BASE]], align 4, !range [[RNG0]]
; CHECK-NEXT: [[LEN_64:%.*]] = zext i32 [[LEN]] to i64
; CHECK-NEXT: [[LEN_PLUS_8:%.*]] = add nuw nsw i64 [[LEN_64]], 8
; CHECK-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(ptr [[P]], i64 [[LEN_PLUS_8]]) ]
; CHECK-NEXT: [[LEN_NONZERO:%.*]] = icmp ne i32 [[LEN]], 0
-; CHECK-NEXT: br i1 [[LEN_NONZERO]], label [[PREHEADER:%.*]], label [[RET2:%.*]]
-; CHECK: preheader:
+; CHECK-NEXT: br i1 [[LEN_NONZERO]], label %[[PREHEADER:.*]], label %[[RET:.*]]
+; CHECK: [[PREHEADER]]:
; CHECK-NEXT: [[LEN_MINUS_1:%.*]] = add nsw i32 [[LEN]], -1
; CHECK-NEXT: [[EXIT_MAINLOOP_AT:%.*]] = call i32 @llvm.umin.i32(i32 [[A]], i32 [[LEN_MINUS_1]])
; CHECK-NEXT: [[EXIT_UMIN:%.*]] = zext nneg i32 [[EXIT_MAINLOOP_AT]] to i64
; CHECK-NEXT: [[ENTRY_COND:%.*]] = icmp ult i64 1, [[EXIT_UMIN]]
-; CHECK-NEXT: br i1 [[ENTRY_COND]], label [[LOOP2_PREHEADER:%.*]], label [[RET2]]
-; CHECK: loop2.preheader:
-; CHECK-NEXT: br label [[LOOP2:%.*]]
-; CHECK: loop2:
-; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ [[IV2_NEXT:%.*]], [[LATCH2:%.*]] ], [ 0, [[LOOP2_PREHEADER]] ]
-; CHECK-NEXT: [[ELEM_PTR2:%.*]] = getelementptr inbounds nuw i8, ptr [[BASE]], i64 [[IV2]]
-; CHECK-NEXT: [[ELEM2:%.*]] = load i8, ptr [[ELEM_PTR2]], align 1
-; CHECK-NEXT: [[IS_TARGET2:%.*]] = icmp eq i8 [[ELEM2]], 0
-; CHECK-NEXT: br i1 [[IS_TARGET2]], label [[DEOPT2:%.*]], label [[LATCH2]]
-; CHECK: latch2:
-; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i64 [[IV2]], 1
-; CHECK-NEXT: [[LOOP_COND2:%.*]] = icmp ult i64 [[IV2]], [[EXIT_UMIN]]
-; CHECK-NEXT: br i1 [[LOOP_COND2]], label [[LOOP2]], label [[DEOPT2]]
-; CHECK: ret2.loopexit:
-; CHECK-NEXT: br label [[RET2]]
-; CHECK: ret2:
+; CHECK-NEXT: br i1 [[ENTRY_COND]], label %[[LOOP_PREHEADER:.*]], label %[[RET]]
+; CHECK: [[LOOP_PREHEADER]]:
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ], [ 0, %[[LOOP_PREHEADER]] ]
+; CHECK-NEXT: [[ELEM_PTR:%.*]] = getelementptr inbounds nuw i8, ptr [[BASE]], i64 [[IV]]
+; CHECK-NEXT: [[ELEM:%.*]] = load i8, ptr [[ELEM_PTR]], align 1
+; CHECK-NEXT: [[IS_TARGET:%.*]] = icmp eq i8 [[ELEM]], 0
+; CHECK-NEXT: br i1 [[IS_TARGET]], label %[[RET_LOOPEXIT:.*]], label %[[LATCH]]
+; CHECK: [[LATCH]]:
+; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ult i64 [[IV]], [[EXIT_UMIN]]
+; CHECK-NEXT: br i1 [[LOOP_COND]], label %[[LOOP]], label %[[RET_LOOPEXIT]]
+; CHECK: [[RET_LOOPEXIT]]:
+; CHECK-NEXT: br label %[[RET]]
+; CHECK: [[RET]]:
; CHECK-NEXT: ret void
;
entry:
%base = getelementptr inbounds nuw i8, ptr %p, i64 8
- %len = load atomic i32, ptr %base unordered, align 4, !range !0
+ %len = load i32, ptr %base, align 4, !range !0
%len.64 = zext i32 %len to i64
%len.plus.8 = add nuw nsw i64 %len.64, 8
call void @llvm.assume(i1 true) [ "dereferenceable"(ptr %p, i64 %len.plus.8) ]
%len.nonzero = icmp ne i32 %len, 0
- br i1 %len.nonzero, label %preheader, label %ret2
+ br i1 %len.nonzero, label %preheader, label %ret
preheader:
%len.minus.1 = add nsw i32 %len, -1
%exit.mainloop.at = call i32 @llvm.umin.i32(i32 %A, i32 %len.minus.1)
%exit.umin = zext nneg i32 %exit.mainloop.at to i64
%entry.cond = icmp ult i64 1, %exit.umin
- br i1 %entry.cond, label %loop2, label %ret2
+ br i1 %entry.cond, label %loop, label %ret
-loop2:
- %iv2 = phi i64 [ %iv2.next, %latch2 ], [ 0, %preheader ]
- %elem.ptr2 = getelementptr inbounds nuw i8, ptr %base, i64 %iv2
- %elem2 = load i8, ptr %elem.ptr2, align 1
- %is.target2 = icmp eq i8 %elem2, 0
- br i1 %is.target2, label %ret2, label %latch2
+loop:
+ %iv = phi i64 [ %iv.next, %latch ], [ 0, %preheader ]
+ %elem.ptr = getelementptr inbounds nuw i8, ptr %base, i64 %iv
+ %elem = load i8, ptr %elem.ptr, align 1
+ %is.target = icmp eq i8 %elem, 0
+ br i1 %is.target, label %ret, label %latch
-latch2:
- %iv2.next = add nuw nsw i64 %iv2, 1
- %loop.cond2 = icmp ult i64 %iv2, %exit.umin
- br i1 %loop.cond2, label %loop2, label %ret2
+latch:
+ %iv.next = add nuw nsw i64 %iv, 1
+ %loop.cond = icmp ult i64 %iv, %exit.umin
+ br i1 %loop.cond, label %loop, label %ret
-ret2:
+ret:
ret void
}
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