[llvm] ca970f3 - [VPlan] Simplify reverses through unary ops (fneg) (#208257)

[via llvm-commits]

Author: Luke Lau
Date: 2026-07-13T07:02:50Z
New Revision: ca970f3bb3ce41365dfc85049db44489c88cb0a5

URL: https://github.com/llvm/llvm-project/commit/ca970f3bb3ce41365dfc85049db44489c88cb0a5
DIFF: https://github.com/llvm/llvm-project/commit/ca970f3bb3ce41365dfc85049db44489c88cb0a5.diff

LOG: [VPlan] Simplify reverses through unary ops (fneg) (#208257)

By marking fneg as elementwise

Added: 
    

Modified: 
    llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
    llvm/test/Transforms/LoopVectorize/simplify-reverse-reverse.ll

Removed: 
    


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diff  --git a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
index 708e7de8669eb..205fc18a86c78 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
@@ -388,7 +388,7 @@ bool vputils::isElementwise(const VPValue *V) {
                             [](auto *R) { return R->getOpcode(); })
                         .Default([](auto *) { return 0; });
   // TODO: Handle more opcodes and recipes.
-  return Instruction::isBinaryOp(Opcode);
+  return Instruction::isUnaryOp(Opcode) || Instruction::isBinaryOp(Opcode);
 }
 
 bool vputils::isSingleScalar(const VPValue *VPV) {

diff  --git a/llvm/test/Transforms/LoopVectorize/simplify-reverse-reverse.ll b/llvm/test/Transforms/LoopVectorize/simplify-reverse-reverse.ll
index c085e82378be6..a76a01574c59b 100644
--- a/llvm/test/Transforms/LoopVectorize/simplify-reverse-reverse.ll
+++ b/llvm/test/Transforms/LoopVectorize/simplify-reverse-reverse.ll
@@ -149,11 +149,9 @@ define void @reverse_fneg(ptr noalias %src, ptr noalias %dst, i32 %n) {
 ; CHECK-NEXT:    [[TMP5:%.*]] = getelementptr float, ptr [[SRC]], i32 [[TMP4]]
 ; CHECK-NEXT:    [[TMP6:%.*]] = getelementptr float, ptr [[TMP5]], i64 -3
 ; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP6]], align 4
-; CHECK-NEXT:    [[REVERSE:%.*]] = shufflevector <4 x float> [[WIDE_LOAD]], <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
-; CHECK-NEXT:    [[TMP7:%.*]] = fneg <4 x float> [[REVERSE]]
+; CHECK-NEXT:    [[REVERSE1:%.*]] = fneg <4 x float> [[WIDE_LOAD]]
 ; CHECK-NEXT:    [[TMP8:%.*]] = getelementptr float, ptr [[DST]], i32 [[TMP4]]
 ; CHECK-NEXT:    [[TMP9:%.*]] = getelementptr float, ptr [[TMP8]], i64 -3
-; CHECK-NEXT:    [[REVERSE1:%.*]] = shufflevector <4 x float> [[TMP7]], <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
 ; CHECK-NEXT:    store <4 x float> [[REVERSE1]], ptr [[TMP9]], align 4
 ; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
 ; CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]