[llvm] [AArch64][llvm][tablegen] Restrict luti6 assembly (4 regs, 8-bit) to 0 <= Zn <= 7 (PR #200751)

[Jonathan Thackray via llvm-commits]

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@@ -1429,6 +1425,30 @@ class ZPRVectorListMul<int ElementWidth, int NumRegs, string RegClassSuffix = ""
                                  # "AArch64::ZPR" # RegClassSuffix # "RegClassID" # ">";
 }
 
+class ZPRVectorListMinMax<int ElementWidth, int NumRegs, int Min, int Max,
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jthackray wrote:

I've looked into doing this. `ZPRVectorListMul` calls `isTypedVectorListMultiple()` and `ZPRVectorListMinMax` calls `isTypedVectorListMinMax()`. I can combine them using a common shared class, with thin wrappers for `Mul` and `MinMax` around this, but it doesn't reduce the amount of code. We have to pass in a predicate arg for these function calls. Happy to implement, but not sure it's better than what we have.

https://github.com/llvm/llvm-project/pull/200751