[llvm] [AArch64][llvm][tablegen] Restrict luti6 assembly (4 regs, 8-bit) to 0 <= Zn <= 7 (PR #200751)

[Jonathan Thackray via llvm-commits]

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@@ -74,6 +74,19 @@ DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
   return Success;
 }
 
+template <unsigned RegClassID, unsigned Multiple, unsigned Min, unsigned Max>
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jthackray wrote:

Now unified.

https://github.com/llvm/llvm-project/pull/200751