[llvm] BPF: Fix misfolding subregisters (PR #208244)

[via llvm-commits]

yonghong-song wrote:

Looks like the following patch can fix the issue:
```
diff --git a/llvm/lib/Target/BPF/BPFMIPeephole.cpp b/llvm/lib/Target/BPF/BPFMIPeephole.cpp
index 637872ee2ebb..737bca4d2b75 100644
--- a/llvm/lib/Target/BPF/BPFMIPeephole.cpp
+++ b/llvm/lib/Target/BPF/BPFMIPeephole.cpp
@@ -161,7 +161,11 @@ bool BPFMIPeephole::isInsnFrom32Def(MachineInstr *DefInsn)
 
 bool BPFMIPeephole::isMovFrom32Def(MachineInstr *MovMI)
 {
-  MachineInstr *DefInsn = MRI->getVRegDef(MovMI->getOperand(1).getReg());
+  MachineOperand &Opnd = MovMI->getOperand(1);
+  if (Opnd.getSubReg())
+    return false;
+
+  MachineInstr *DefInsn = MRI->getVRegDef(Opnd.getReg());
 
   LLVM_DEBUG(dbgs() << "  Def of Mov Src:");
   LLVM_DEBUG(DefInsn->dump());
```

The new correct result from the selftest (using original MOV_32_64 insn)
```
body:             |                                                                                                          
  bb.0:                                                                                                                      
    liveins: $r1                                                                                                             
                                                                                                                             
    %0:gpr = LD_imm64 0                                                                                                      
    %1:gpr = MOV_32_64 %0.sub_32                                                                                             
    $r0 = COPY %1                                                                                                            
    RET implicit $r0                                                                                                         
...
```

For a `MOV_32_64 %0` where `%0:gpr32 = ...` should work as before.

The only issue is for `MOV_32_64 %0.sub_32` transforming to SUBREG_TO_REG. This will cause the incorrect codegen issue in
```
        BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::SUBREG_TO_REG), DstReg)
            .addReg(SubReg)
            .addImm(BPF::sub_32);
```
where SubReg is actually the full 64bit register like
 ```
    %0:gpr = LD_imm64 0                                                                                                      
    %1:gpr = SUBREG_TO_REG %0, %subreg.sub_32
```
which will fail for validation.

https://github.com/llvm/llvm-project/pull/208244