[llvm] [VPlan] Simplify reverses through casts (PR #208262)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 8 09:50:50 PDT 2026
https://github.com/lukel97 updated https://github.com/llvm/llvm-project/pull/208262
>From 2a26a46bb444f23945480f94c83b4cad7b26f87f Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Thu, 9 Jul 2026 00:36:22 +0800
Subject: [PATCH 1/2] Precommit tests
---
.../RISCV/simplify-reverse-reverse.ll | 38 +++++++++++
.../LoopVectorize/simplify-reverse-reverse.ll | 67 +++++++++++++++++++
2 files changed, 105 insertions(+)
create mode 100644 llvm/test/Transforms/LoopVectorize/RISCV/simplify-reverse-reverse.ll
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/simplify-reverse-reverse.ll b/llvm/test/Transforms/LoopVectorize/RISCV/simplify-reverse-reverse.ll
new file mode 100644
index 0000000000000..90aa9c28b7e6b
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/simplify-reverse-reverse.ll
@@ -0,0 +1,38 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
+; RUN: opt -p loop-vectorize -mtriple riscv64 -mattr=+v < %s -S | FileCheck %s
+
+define void @reverse_zext(ptr noalias %src, ptr noalias %dst, i32 %n) {
+; CHECK-LABEL: define void @reverse_zext(
+; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[VECTOR_PH:.*]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[TMP3:%.*]] = phi i32 [ [[N]], %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP4]] = add nsw i32 [[TMP3]], -1
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[SRC]], i32 [[TMP4]]
+; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP5]], align 4
+; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i64, ptr [[DST]], i32 [[TMP4]]
+; CHECK-NEXT: store i64 [[TMP6]], ptr [[TMP11]], align 8
+; CHECK-NEXT: [[EC:%.*]] = icmp sgt i32 [[TMP4]], 0
+; CHECK-NEXT: br i1 [[EC]], label %[[VECTOR_BODY]], label %[[EXIT:.*]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i32 [%n, %entry], [%iv.next, %loop]
+ %iv.next = add nsw i32 %iv, -1
+ %gep.src = getelementptr i32, ptr %src, i32 %iv.next
+ %x = load i32, ptr %gep.src
+ %y = zext i32 %x to i64
+ %gep.dst = getelementptr i64, ptr %dst, i32 %iv.next
+ store i64 %y, ptr %gep.dst
+ %ec = icmp sgt i32 %iv.next, 0
+ br i1 %ec, label %loop, label %exit
+
+exit:
+ ret void
+}
diff --git a/llvm/test/Transforms/LoopVectorize/simplify-reverse-reverse.ll b/llvm/test/Transforms/LoopVectorize/simplify-reverse-reverse.ll
index c085e82378be6..0438e79fff893 100644
--- a/llvm/test/Transforms/LoopVectorize/simplify-reverse-reverse.ll
+++ b/llvm/test/Transforms/LoopVectorize/simplify-reverse-reverse.ll
@@ -194,3 +194,70 @@ loop:
exit:
ret void
}
+
+define void @reverse_zext(ptr noalias %src, ptr noalias %dst, i32 %n) {
+; CHECK-LABEL: define void @reverse_zext(
+; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], i32 [[N:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[TMP0:%.*]] = add nsw i32 [[N]], -1
+; CHECK-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP0]], i32 0)
+; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[N]], [[SMIN]]
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP1]], 4
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP1]], 4
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP1]], [[N_MOD_VF]]
+; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[N]], [[N_VEC]]
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[N]], [[INDEX]]
+; CHECK-NEXT: [[TMP4:%.*]] = add nsw i32 [[TMP3]], -1
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[SRC]], i32 [[TMP4]]
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[TMP5]], i64 -3
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 4
+; CHECK-NEXT: [[REVERSE:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT: [[TMP7:%.*]] = zext <4 x i32> [[REVERSE]] to <4 x i64>
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[DST]], i32 [[TMP4]]
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[TMP8]], i64 -3
+; CHECK-NEXT: [[REVERSE1:%.*]] = shufflevector <4 x i64> [[TMP7]], <4 x i64> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT: store <4 x i64> [[REVERSE1]], ptr [[TMP9]], align 4
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
+; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP1]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ [[N]], %[[ENTRY]] ]
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[IV_NEXT]] = add nsw i32 [[IV]], -1
+; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr i32, ptr [[SRC]], i32 [[IV_NEXT]]
+; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[GEP_SRC]], align 4
+; CHECK-NEXT: [[Y:%.*]] = zext i32 [[X]] to i64
+; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr i64, ptr [[DST]], i32 [[IV_NEXT]]
+; CHECK-NEXT: store i64 [[Y]], ptr [[GEP_DST]], align 4
+; CHECK-NEXT: [[EC:%.*]] = icmp sgt i32 [[IV_NEXT]], 0
+; CHECK-NEXT: br i1 [[EC]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP9:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i32 [%n, %entry], [%iv.next, %loop]
+ %iv.next = add nsw i32 %iv, -1
+ %gep.src = getelementptr i32, ptr %src, i32 %iv.next
+ %x = load i32, ptr %gep.src
+ %y = zext i32 %x to i64
+ %gep.dst = getelementptr i64, ptr %dst, i32 %iv.next
+ store i64 %y, ptr %gep.dst
+ %ec = icmp sgt i32 %iv.next, 0
+ br i1 %ec, label %loop, label %exit
+
+exit:
+ ret void
+}
>From 2d011f3aa12e5bde7ed5b52a61b25abbdcb89a33 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Thu, 9 Jul 2026 00:41:27 +0800
Subject: [PATCH 2/2] [VPlan] Simplify reverses through casts
By handling VPWidenCastRecipe in isElementwise
---
llvm/lib/Transforms/Vectorize/VPlanUtils.cpp | 4 +--
.../RISCV/simplify-reverse-reverse.ll | 31 ++++++++++++++-----
.../LoopVectorize/simplify-reverse-reverse.ll | 4 +--
3 files changed, 27 insertions(+), 12 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
index f2748afa01b87..ea46cc9622147 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
@@ -421,11 +421,11 @@ static bool preservesUniformity(unsigned Opcode) {
bool vputils::isElementwise(const VPValue *V) {
unsigned Opcode = TypeSwitch<const VPValue *, unsigned>(V)
- .Case<VPInstruction, VPWidenRecipe>(
+ .Case<VPInstruction, VPWidenRecipe, VPWidenCastRecipe>(
[](auto *R) { return R->getOpcode(); })
.Default([](auto *) { return 0; });
// TODO: Handle more opcodes and recipes.
- return Instruction::isBinaryOp(Opcode);
+ return Instruction::isBinaryOp(Opcode) || Instruction::isCast(Opcode);
}
bool vputils::isSingleScalar(const VPValue *VPV) {
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/simplify-reverse-reverse.ll b/llvm/test/Transforms/LoopVectorize/RISCV/simplify-reverse-reverse.ll
index 90aa9c28b7e6b..c120162bcdbef 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/simplify-reverse-reverse.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/simplify-reverse-reverse.ll
@@ -4,19 +4,36 @@
define void @reverse_zext(ptr noalias %src, ptr noalias %dst, i32 %n) {
; CHECK-LABEL: define void @reverse_zext(
; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
-; CHECK-NEXT: [[VECTOR_PH:.*]]:
+; CHECK-NEXT: [[VECTOR_PH:.*:]]
+; CHECK-NEXT: [[TMP0:%.*]] = add nsw i32 [[N]], -1
+; CHECK-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP0]], i32 0)
+; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[N]], [[SMIN]]
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
-; CHECK-NEXT: [[TMP3:%.*]] = phi i32 [ [[N]], %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP4]] = add nsw i32 [[TMP3]], -1
+; CHECK-NEXT: br label %[[VECTOR_BODY1:.*]]
+; CHECK: [[VECTOR_BODY1]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_BODY]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY1]] ]
+; CHECK-NEXT: [[AVL:%.*]] = phi i32 [ [[TMP1]], %[[VECTOR_BODY]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY1]] ]
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[AVL]], i32 2, i1 true)
+; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[N]], [[INDEX]]
+; CHECK-NEXT: [[TMP4:%.*]] = add nsw i32 [[TMP3]], -1
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[SRC]], i32 [[TMP4]]
-; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP5]], align 4
; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP7:%.*]] = sub nuw nsw i64 [[TMP6]], 1
+; CHECK-NEXT: [[TMP8:%.*]] = sub i64 0, [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[TMP5]], i64 [[TMP8]]
+; CHECK-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 2 x i32> @llvm.vp.load.nxv2i32.p0(ptr align 4 [[TMP9]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP2]])
+; CHECK-NEXT: [[TMP10:%.*]] = zext <vscale x 2 x i32> [[VP_OP_LOAD]] to <vscale x 2 x i64>
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i64, ptr [[DST]], i32 [[TMP4]]
-; CHECK-NEXT: store i64 [[TMP6]], ptr [[TMP11]], align 8
-; CHECK-NEXT: [[EC:%.*]] = icmp sgt i32 [[TMP4]], 0
-; CHECK-NEXT: br i1 [[EC]], label %[[VECTOR_BODY]], label %[[EXIT:.*]]
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i64, ptr [[TMP11]], i64 [[TMP8]]
+; CHECK-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP10]], ptr align 8 [[TMP12]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP2]])
+; CHECK-NEXT: [[CURRENT_ITERATION_NEXT]] = add nuw i32 [[TMP2]], [[INDEX]]
+; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i32 [[AVL]], [[TMP2]]
+; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i32 [[AVL_NEXT]], 0
+; CHECK-NEXT: br i1 [[TMP13]], label %[[EXIT:.*]], label %[[VECTOR_BODY1]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: [[EXIT]]:
+; CHECK-NEXT: br label %[[EXIT1:.*]]
+; CHECK: [[EXIT1]]:
; CHECK-NEXT: ret void
;
entry:
diff --git a/llvm/test/Transforms/LoopVectorize/simplify-reverse-reverse.ll b/llvm/test/Transforms/LoopVectorize/simplify-reverse-reverse.ll
index 0438e79fff893..7f7279ec4eb55 100644
--- a/llvm/test/Transforms/LoopVectorize/simplify-reverse-reverse.ll
+++ b/llvm/test/Transforms/LoopVectorize/simplify-reverse-reverse.ll
@@ -216,11 +216,9 @@ define void @reverse_zext(ptr noalias %src, ptr noalias %dst, i32 %n) {
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[SRC]], i32 [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[TMP5]], i64 -3
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 4
-; CHECK-NEXT: [[REVERSE:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
-; CHECK-NEXT: [[TMP7:%.*]] = zext <4 x i32> [[REVERSE]] to <4 x i64>
+; CHECK-NEXT: [[REVERSE1:%.*]] = zext <4 x i32> [[WIDE_LOAD]] to <4 x i64>
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[DST]], i32 [[TMP4]]
; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[TMP8]], i64 -3
-; CHECK-NEXT: [[REVERSE1:%.*]] = shufflevector <4 x i64> [[TMP7]], <4 x i64> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT: store <4 x i64> [[REVERSE1]], ptr [[TMP9]], align 4
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
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