[llvm] [PeepholeOptimizer] Add REG_SEQUENCE subregister use optimization (PR #205795)

[Matt Arsenault via llvm-commits]

================
@@ -63,6 +63,23 @@
 //   =>
 //     b = bitcast A <-- cross-bank copy
 //     C = copy A    <-- same-bank copy
+//
+// - Optimize REG_SEQUENCE subregister uses:
+//
+//     Create COPYs for uses that extract subregisters from a REG_SEQUENCE
+//     output, exposing the original sources to target-specific folding
+//     passes.
+//
+//     Example:
+//       A = REG_SEQUENCE B, sub0, C, sub1
+//       D = ADD A.sub0, E
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arsenm wrote:

I spent yesterday rebasing my patch which caused me to open this issue in the first place. I'll need to spend more time looking at the overall problem.

I think there's a phase ordering problem to be solved here. WIth the current state, isel rarely produces target instructions with subregister references. There are some select cases from EmitInstrWithCustomInserter which do manually build MIR with subregs. We could change those to not do that, and then we have simple to handle COPY everywhere.

However, my WIP patch will likely increase the number of direct subreg references at a point between isel and here


https://github.com/llvm/llvm-project/pull/205795