[llvm] [AArch64][llvm][tablegen] Restrict luti6 assembly (4 regs, 8-bit) to 0 <= Zn <= 7 (PR #200751)

[via llvm-commits]

================
@@ -2578,10 +2578,22 @@ void CodeGenRegBank::inferMatchingSuperRegClass(
         }
       }
 
-      auto [SubSetRC, Inserted] = getOrCreateSubClass(
-          RC, &SubSetVec,
-          RC->getName() + "_with_" + CompositeSubIdx->getName() + "_in_" +
-              CompositeSubRC->getName());
+      std::string Name =
+          (Twine(RC->getName()) + "_with_" + CompositeSubIdx->getName() +
----------------
Lukacma wrote:

Why is this being cast into twine ?

https://github.com/llvm/llvm-project/pull/200751