[llvm] [AArch64][llvm][tablegen] Restrict luti6 assembly (4 regs, 8-bit) to 0 <= Zn <= 7 (PR #200751)

[via llvm-commits]

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@@ -2578,10 +2578,22 @@ void CodeGenRegBank::inferMatchingSuperRegClass(
         }
       }
 
-      auto [SubSetRC, Inserted] = getOrCreateSubClass(
-          RC, &SubSetVec,
-          RC->getName() + "_with_" + CompositeSubIdx->getName() + "_in_" +
-              CompositeSubRC->getName());
+      std::string Name =
+          (Twine(RC->getName()) + "_with_" + CompositeSubIdx->getName() +
+           "_in_" + CompositeSubRC->getName())
+              .str();
+
+      auto HasRegClassNamed = [&](StringRef Candidate) {
+        return llvm::any_of(RegClasses, [&](const CodeGenRegisterClass &RC) {
+          return RC.getName() == Candidate;
+        });
+      };
+      if (HasRegClassNamed(Name) && &SubRC != CompositeSubRC)
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Lukacma wrote:

Why is the 2nd part of the if statement necessary ?

https://github.com/llvm/llvm-project/pull/200751