[llvm] [RISCV][MCA] Avoid deriving EMUL without SEW (PR #207986)

[Zeyi Xu via llvm-commits]

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@@ -1,12 +1,26 @@
 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
 
+# LLVM-MCA-BEGIN memory
+# LLVM-MCA-RISCV-LMUL M1
+vle8.v v8, (a0)
+vluxei8.v v8, (a0), v0
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN div
 # Test LMUL but no SEW falls back to worst case.
 vsetvli zero, a0, e8, m1, tu, mu
 # LLVM-MCA-RISCV-LMUL M1
 vdiv.vv v8, v8, v12
 # LLVM-MCA-RISCV-SEW E8
 vdiv.vv v8, v8, v12
+# LLVM-MCA-END
+
+# CHECK:      Code Region - memory
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zeyi2 wrote:

Fixed, thanks for reviewing!

https://github.com/llvm/llvm-project/pull/207986