[llvm] [RISCV][MCA] Avoid deriving EMUL without SEW (PR #207986)

[Zeyi Xu via llvm-commits]

https://github.com/zeyi2 updated https://github.com/llvm/llvm-project/pull/207986

>From 22bba98585755d8c157efd9e52ecc689fd40657f Mon Sep 17 00:00:00 2001
From: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: Tue, 7 Jul 2026 20:04:31 +0800
Subject: [PATCH 1/2] [RISCV][MCA] Avoid deriving EMUL without SEW

---
 llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp |  6 ++++++
 .../RISCV/SiFiveX280/needs-sew-but-only-lmul.s     | 14 ++++++++++++++
 2 files changed, 20 insertions(+)

diff --git a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
index 1270cdd8189d9..8f8af225ce686 100644
--- a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
+++ b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
@@ -265,6 +265,9 @@ unsigned RISCVInstrumentManager::getSchedClassID(
 
   std::optional<unsigned> VPOpcode;
   if (const auto *VXMO = RISCV::getVXMemOpInfo(Opcode)) {
+    if (!SEW)
+      return SchedClassID;
+
     // Calculate the expected index EMUL. For indexed operations,
     // the DataEEW and DataEMUL are equal to SEW and LMUL, respectively.
     unsigned IndexEMUL = ((1 << VXMO->Log2IdxEEW) * LMUL) / SEW;
@@ -297,6 +300,9 @@ unsigned RISCVInstrumentManager::getSchedClassID(
       }
     }
   } else if (opcodeHasEEWAndEMULInfo(Opcode)) {
+    if (!SEW)
+      return SchedClassID;
+
     RISCVVType::VLMUL VLMUL = static_cast<RISCVVType::VLMUL>(LMUL);
     auto [EEW, EMUL] = getEEWAndEMUL(Opcode, VLMUL, SEW);
     if (const auto *RVV =
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveX280/needs-sew-but-only-lmul.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveX280/needs-sew-but-only-lmul.s
index 747cfca51e4dc..9fec908e73a51 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveX280/needs-sew-but-only-lmul.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveX280/needs-sew-but-only-lmul.s
@@ -1,12 +1,26 @@
 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
 
+# LLVM-MCA-BEGIN memory
+# LLVM-MCA-RISCV-LMUL M1
+vle8.v v8, (a0)
+vluxei8.v v8, (a0), v0
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN div
 # Test LMUL but no SEW falls back to worst case.
 vsetvli zero, a0, e8, m1, tu, mu
 # LLVM-MCA-RISCV-LMUL M1
 vdiv.vv v8, v8, v12
 # LLVM-MCA-RISCV-SEW E8
 vdiv.vv v8, v8, v12
+# LLVM-MCA-END
+
+# CHECK:      Code Region - memory
+# CHECK:      Iterations:        1
+# CHECK-NEXT: Instructions:      2
+# CHECK:      vle8.v	v8, (a0)
+# CHECK:      vluxei8.v	v8, (a0), v0
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      3

>From d299fc86e7999075d21ae5bf4e0af1b58bf4d27e Mon Sep 17 00:00:00 2001
From: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: Wed, 8 Jul 2026 09:37:36 +0800
Subject: [PATCH 2/2] address feedback

---
 .../RISCV/SiFiveX280/needs-sew-but-only-lmul.s        | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveX280/needs-sew-but-only-lmul.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveX280/needs-sew-but-only-lmul.s
index 9fec908e73a51..a48a65a7528f3 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveX280/needs-sew-but-only-lmul.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveX280/needs-sew-but-only-lmul.s
@@ -19,8 +19,15 @@ vdiv.vv v8, v8, v12
 # CHECK:      Code Region - memory
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      2
-# CHECK:      vle8.v	v8, (a0)
-# CHECK:      vluxei8.v	v8, (a0), v0
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      4     16.00   *                   vle8.v	v8, (a0)
+# CHECK-NEXT:  1      515   512.00  *                   vluxei8.v	v8, (a0), v0
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
+# CHECK-NEXT:  -      -      -      -      -     1.00   17.00   -     vle8.v	v8, (a0)
+# CHECK-NEXT:  -      -      -      -      -     1.00   513.00  -     vluxei8.v	v8, (a0), v0
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      3