[llvm] [X86] Add ISD::VECREDUCE_MUL lowering instead of matching in DAG (PR #207593)

[Phoebe Wang via llvm-commits]

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@@ -47972,6 +47948,38 @@ static SDValue combineExtractVectorElt(SDNode *N, SelectionDAG &DAG,
   return SDValue();
 }
 
+static SDValue combineVECREDUCE_MUL(SDNode *N, SelectionDAG &DAG,
+                                    const X86Subtarget &Subtarget) {
+  SDValue Src = N->getOperand(0);
+  EVT SrcVT = Src.getValueType();
+  unsigned NumElts = SrcVT.getVectorNumElements();
+  SDLoc DL(N);
+
+  // vXi8 mul reduction - promote to vXi16 mul reduction.
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phoebewang wrote:

No, just wondered why not see them in the diff.

https://github.com/llvm/llvm-project/pull/207593