[llvm] [X86] Add ISD::VECREDUCE_MUL lowering instead of matching in DAG (PR #207593)

[Simon Pilgrim via llvm-commits]

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@@ -34351,6 +34355,7 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   case ISD::VECREDUCE_AND:
   case ISD::VECREDUCE_OR:
   case ISD::VECREDUCE_XOR:      return LowerVECREDUCE(Op, Subtarget, DAG, true);
+  case ISD::VECREDUCE_MUL:      return LowerVECREDUCE(Op, Subtarget, DAG, false);
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RKSimon wrote:

to avoid mul(extract(x,0),extract(x,1)) scalarizations of the last stage

https://github.com/llvm/llvm-project/pull/207593