[llvm] [AArch64][DAG] Port adde and sube combine to AArch64 (PR #202227)

[Ricardo Jesus via llvm-commits]

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@@ -23065,6 +23065,29 @@ static SDValue foldADCToCINC(SDNode *N, SelectionDAG &DAG) {
   return DAG.getNode(AArch64ISD::CSINC, DL, VT, LHS, LHS, CC, Cond);
 }
 
+static SDValue performAddSubCarryCombine(SDNode *N, SelectionDAG &DAG,
+                                         unsigned NewOpcode) {
+  SDValue RHS = N->getOperand(1);
+  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
+    APInt Imm = C->getAPIntValue();
+    APInt NotImm = ~Imm;
+
+    // Note: We always allow -1 as it maps to 0 (which can use wzr/xzr).
+    if (Imm.isAllOnes() ||
+        (numberOfInstrToLoadImm(Imm) > numberOfInstrToLoadImm(NotImm) &&
+         C->hasOneUse())) {
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rj-jesus wrote:

It looks like the tests pass without `numberOfInstrToLoadImm(Imm) > numberOfInstrToLoadImm(NotImm) && C->hasOneUse()`. Do you have a case where expanding ~Imm is preferable to Imm? This either needs testing or is probably better removed.

https://github.com/llvm/llvm-project/pull/202227