[llvm] [X86] Attempt to narrow XMM->i64 (v)movq -> (v)movd if the upper 32-bits are known to be zero (PR #207615)
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Sun Jul 5 14:48:09 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: Simon Pilgrim (RKSimon)
<details>
<summary>Changes</summary>
Add a custom 'X86upperzero' tablegen pattern to match vectors where the upper half bits of every element is known zero.
Saves 1 byte by using (V)MOVD instead of (V)MOVQ - and avoids differences in X86/X64 codegen that was bloating diffs in some upcoming VECREDUCE_ADD work.
I've added an extra psadbw.ll test to ensure that the extractstore pattern isn't being affected.
Cleanup for the upcoming VECREDUCE_ADD handling which will be using PSADBW more aggressively (v2i64 result type but only 16 active bits for element).
---
Patch is 56.89 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/207615.diff
16 Files Affected:
- (modified) llvm/lib/Target/X86/X86InstrAVX512.td (+9)
- (modified) llvm/lib/Target/X86/X86InstrFragmentsSIMD.td (+9)
- (modified) llvm/lib/Target/X86/X86InstrSSE.td (+13)
- (modified) llvm/test/CodeGen/X86/divrem-by-select.ll (+8-8)
- (modified) llvm/test/CodeGen/X86/insertelement-zero.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/legalize-vec-assertzext.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/psadbw.ll (+30-2)
- (modified) llvm/test/CodeGen/X86/sad_variations.ll (+6-6)
- (modified) llvm/test/CodeGen/X86/trunc-subvector.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/ucmp.ll (+175-173)
- (modified) llvm/test/CodeGen/X86/udiv_fix.ll (+5-5)
- (modified) llvm/test/CodeGen/X86/udiv_fix_sat.ll (+3-3)
- (modified) llvm/test/CodeGen/X86/vector-compress.ll (+6-6)
- (modified) llvm/test/CodeGen/X86/vector-reduce-add-mask.ll (+16-16)
- (modified) llvm/test/CodeGen/X86/vector-reduce-add-zext.ll (+10-10)
- (modified) llvm/test/CodeGen/X86/vector-reduce-ctpop.ll (+21-21)
``````````diff
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index 1584c828f73d4..36bbd53c95817 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -3914,6 +3914,15 @@ let Predicates = [HasAVX512] in {
(VMOVPQI2QIZmr addr:$dst, VR128X:$src)>;
}
+//===---------------------------------------------------------------------===//
+// If the upper 32 bits of v2i64 elements are zero, we can use (v)movd instead.
+let AddedComplexity = 10 in {
+ let Predicates = [HasAVX512] in {
+ def : Pat<(i64 (extractelt (X86upperzero<v2i64, VR128X>:$src), (iPTR 0))),
+ (SUBREG_TO_REG (VMOVPDI2DIZrr VR128:$src), sub_32bit)>;
+ }
+}
+
// Move Scalar Single to Double Int
//
let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in {
diff --git a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
index 572309941c204..ee870669b05cf 100644
--- a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
+++ b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
@@ -1377,6 +1377,15 @@ def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
+// Match node if each vector elements' upper half bits are zero.
+class X86upperzero <ValueType vt, RegisterClass rc> : PatLeaf<(vt rc:$src), [{
+ unsigned EltBits = Op.getScalarValueSizeInBits();
+ APInt UpperMask = APInt::getHighBitsSet(EltBits, EltBits / 2);
+ return CurDAG->MaskedValueIsZero(Op, UpperMask);
+}]> {
+ let GISelPredicateCode = [{return false;}]; // TODO
+}
+
// Match node that has known zeros in every element except the lowest.
class X86vzelts <ValueType vt, RegisterClass rc> : PatLeaf<(vt rc:$src), [{
unsigned NumElts = Op.getValueType().getVectorNumElements();
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index f53a79fb2f9f9..fbabffc9a6f98 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -4249,6 +4249,19 @@ def MOVPQIto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
Sched<[WriteVecStore]>;
} // ExeDomain = SSEPackedInt
+//===---------------------------------------------------------------------===//
+// If the upper 32 bits of v2i64 elements are zero, we can use (v)movd instead.
+let AddedComplexity = 10 in {
+ let Predicates = [UseAVX] in {
+ def : Pat<(i64 (extractelt (X86upperzero<v2i64, VR128>:$src), (iPTR 0))),
+ (SUBREG_TO_REG (VMOVPDI2DIrr VR128:$src), sub_32bit)>;
+ }
+ let Predicates = [UseSSE2] in {
+ def : Pat<(i64 (extractelt (X86upperzero<v2i64, VR128>:$src), (iPTR 0))),
+ (SUBREG_TO_REG (MOVPDI2DIrr VR128:$src), sub_32bit)>;
+ }
+}
+
//===---------------------------------------------------------------------===//
// Bitcast FR64 <-> GR64
//
diff --git a/llvm/test/CodeGen/X86/divrem-by-select.ll b/llvm/test/CodeGen/X86/divrem-by-select.ll
index f9582bb7343ba..b80531881fa65 100644
--- a/llvm/test/CodeGen/X86/divrem-by-select.ll
+++ b/llvm/test/CodeGen/X86/divrem-by-select.ll
@@ -148,7 +148,7 @@ define <2 x i64> @udiv_indentity_zero(<2 x i1> %c, <2 x i64> %x) {
; CHECK-X64-V3-NEXT: divq %rcx
; CHECK-X64-V3-NEXT: movq %rax, %rcx
; CHECK-X64-V3-NEXT: vmovq %xmm1, %rax
-; CHECK-X64-V3-NEXT: vmovq %xmm0, %rsi
+; CHECK-X64-V3-NEXT: vmovd %xmm0, %esi
; CHECK-X64-V3-NEXT: xorl %edx, %edx
; CHECK-X64-V3-NEXT: divq %rsi
; CHECK-X64-V3-NEXT: vmovq %rcx, %xmm0
@@ -168,7 +168,7 @@ define <2 x i64> @udiv_indentity_zero(<2 x i1> %c, <2 x i64> %x) {
; CHECK-X64-V4-NEXT: divq %rcx
; CHECK-X64-V4-NEXT: movq %rax, %rcx
; CHECK-X64-V4-NEXT: vmovq %xmm1, %rax
-; CHECK-X64-V4-NEXT: vmovq %xmm0, %rsi
+; CHECK-X64-V4-NEXT: vmovd %xmm0, %esi
; CHECK-X64-V4-NEXT: xorl %edx, %edx
; CHECK-X64-V4-NEXT: divq %rsi
; CHECK-X64-V4-NEXT: vmovq %rcx, %xmm0
@@ -257,7 +257,7 @@ define <2 x i64> @urem_identity_const(<2 x i1> %c, <2 x i64> %x) {
; CHECK-X64-V4-NEXT: xorl %edx, %edx
; CHECK-X64-V4-NEXT: divq %rcx
; CHECK-X64-V4-NEXT: movq %rdx, %rcx
-; CHECK-X64-V4-NEXT: vmovq %xmm0, %rsi
+; CHECK-X64-V4-NEXT: vmovd %xmm0, %esi
; CHECK-X64-V4-NEXT: vmovq %xmm1, %rax
; CHECK-X64-V4-NEXT: xorl %edx, %edx
; CHECK-X64-V4-NEXT: divq %rsi
@@ -302,7 +302,7 @@ define <2 x i64> @sdiv_identity_const(<2 x i1> %c, <2 x i64> %x) {
; CHECK-X64-V4-NEXT: cqto
; CHECK-X64-V4-NEXT: idivq %rcx
; CHECK-X64-V4-NEXT: movq %rax, %rcx
-; CHECK-X64-V4-NEXT: vmovq %xmm0, %rsi
+; CHECK-X64-V4-NEXT: vmovd %xmm0, %esi
; CHECK-X64-V4-NEXT: vmovq %xmm1, %rax
; CHECK-X64-V4-NEXT: cqto
; CHECK-X64-V4-NEXT: idivq %rsi
@@ -347,7 +347,7 @@ define <2 x i64> @sdiv_identity_const_todo_better_nonzero(<2 x i1> %c, <2 x i64>
; CHECK-X64-V4-NEXT: cqto
; CHECK-X64-V4-NEXT: idivq %rcx
; CHECK-X64-V4-NEXT: movq %rax, %rcx
-; CHECK-X64-V4-NEXT: vmovq %xmm0, %rsi
+; CHECK-X64-V4-NEXT: vmovd %xmm0, %esi
; CHECK-X64-V4-NEXT: vmovq %xmm1, %rax
; CHECK-X64-V4-NEXT: cqto
; CHECK-X64-V4-NEXT: idivq %rsi
@@ -392,7 +392,7 @@ define <2 x i64> @srem_identity_const(<2 x i1> %c, <2 x i64> %x) {
; CHECK-X64-V4-NEXT: cqto
; CHECK-X64-V4-NEXT: idivq %rcx
; CHECK-X64-V4-NEXT: movq %rdx, %rcx
-; CHECK-X64-V4-NEXT: vmovq %xmm0, %rsi
+; CHECK-X64-V4-NEXT: vmovd %xmm0, %esi
; CHECK-X64-V4-NEXT: vmovq %xmm1, %rax
; CHECK-X64-V4-NEXT: cqto
; CHECK-X64-V4-NEXT: idivq %rsi
@@ -443,7 +443,7 @@ define <2 x i64> @udivrem_identity_const(<2 x i1> %c, <2 x i64> %x) {
; CHECK-X64-V4-NEXT: divq %rcx
; CHECK-X64-V4-NEXT: movq %rax, %rcx
; CHECK-X64-V4-NEXT: movq %rdx, %rsi
-; CHECK-X64-V4-NEXT: vmovq %xmm0, %rdi
+; CHECK-X64-V4-NEXT: vmovd %xmm0, %edi
; CHECK-X64-V4-NEXT: vmovq %xmm1, %rax
; CHECK-X64-V4-NEXT: xorl %edx, %edx
; CHECK-X64-V4-NEXT: divq %rdi
@@ -500,7 +500,7 @@ define <2 x i64> @sdivrem_identity_const(<2 x i1> %c, <2 x i64> %x) {
; CHECK-X64-V4-NEXT: idivq %rcx
; CHECK-X64-V4-NEXT: movq %rax, %rcx
; CHECK-X64-V4-NEXT: movq %rdx, %rsi
-; CHECK-X64-V4-NEXT: vmovq %xmm0, %rdi
+; CHECK-X64-V4-NEXT: vmovd %xmm0, %edi
; CHECK-X64-V4-NEXT: vmovq %xmm1, %rax
; CHECK-X64-V4-NEXT: cqto
; CHECK-X64-V4-NEXT: idivq %rdi
diff --git a/llvm/test/CodeGen/X86/insertelement-zero.ll b/llvm/test/CodeGen/X86/insertelement-zero.ll
index e1c8cefa73d8a..de1b51b14db6a 100644
--- a/llvm/test/CodeGen/X86/insertelement-zero.ll
+++ b/llvm/test/CodeGen/X86/insertelement-zero.ll
@@ -570,7 +570,7 @@ define i64 @fold_insertelement_to_and(i32 noundef %arg) {
; AVX2-NEXT: vpaddq %xmm0, %xmm0, %xmm1
; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vmovq %xmm0, %rax
+; AVX2-NEXT: vmovd %xmm0, %eax
; AVX2-NEXT: retq
%i = shufflevector <8 x i64> zeroinitializer, <8 x i64> splat (i64 77), <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 4, i32 8, i32 6, i32 10>
%i1 = insertelement <8 x i64> %i, i64 0, i64 0
diff --git a/llvm/test/CodeGen/X86/legalize-vec-assertzext.ll b/llvm/test/CodeGen/X86/legalize-vec-assertzext.ll
index b1d8243f26a0f..121f1bbb20daf 100644
--- a/llvm/test/CodeGen/X86/legalize-vec-assertzext.ll
+++ b/llvm/test/CodeGen/X86/legalize-vec-assertzext.ll
@@ -25,7 +25,7 @@ define i64 @widen_assertzext(ptr %x) nounwind {
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovdqa64 %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: vextracti32x4 $3, %zmm0, %xmm0
-; CHECK-NEXT: vmovq %xmm0, %rax
+; CHECK-NEXT: vmovd %xmm0, %eax
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
@@ -43,7 +43,7 @@ define i64 @widen_assertzext_range_attr(ptr %x) nounwind {
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovdqa64 %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: vextracti32x4 $3, %zmm0, %xmm0
-; CHECK-NEXT: vmovq %xmm0, %rax
+; CHECK-NEXT: vmovd %xmm0, %eax
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/psadbw.ll b/llvm/test/CodeGen/X86/psadbw.ll
index 354fb8b92e9d2..ccfb46a204800 100644
--- a/llvm/test/CodeGen/X86/psadbw.ll
+++ b/llvm/test/CodeGen/X86/psadbw.ll
@@ -31,13 +31,13 @@ define i64 @combine_psadbw_demandedelt(<16 x i8> %0, <16 x i8> %1) nounwind {
; X64-SSE-LABEL: combine_psadbw_demandedelt:
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: psadbw %xmm1, %xmm0
-; X64-SSE-NEXT: movq %xmm0, %rax
+; X64-SSE-NEXT: movd %xmm0, %eax
; X64-SSE-NEXT: retq
;
; AVX2-LABEL: combine_psadbw_demandedelt:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vmovq %xmm0, %rax
+; AVX2-NEXT: vmovd %xmm0, %eax
; AVX2-NEXT: retq
%3 = shufflevector <16 x i8> %0, <16 x i8> %0, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11>
%4 = shufflevector <16 x i8> %1, <16 x i8> %1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11>
@@ -46,6 +46,34 @@ define i64 @combine_psadbw_demandedelt(<16 x i8> %0, <16 x i8> %1) nounwind {
ret i64 %6
}
+; Ensure movq->movd narrowing doesn't affect the i64 store.
+define void @combine_psadbw_demandedelt_store(<16 x i8> %0, <16 x i8> %1, ptr %p0) nounwind {
+; X86-SSE-LABEL: combine_psadbw_demandedelt_store:
+; X86-SSE: # %bb.0:
+; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-SSE-NEXT: psadbw %xmm1, %xmm0
+; X86-SSE-NEXT: movq %xmm0, (%eax)
+; X86-SSE-NEXT: retl
+;
+; X64-SSE-LABEL: combine_psadbw_demandedelt_store:
+; X64-SSE: # %bb.0:
+; X64-SSE-NEXT: psadbw %xmm1, %xmm0
+; X64-SSE-NEXT: movq %xmm0, (%rdi)
+; X64-SSE-NEXT: retq
+;
+; AVX2-LABEL: combine_psadbw_demandedelt_store:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
+; AVX2-NEXT: vmovq %xmm0, (%rdi)
+; AVX2-NEXT: retq
+ %3 = shufflevector <16 x i8> %0, <16 x i8> %0, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11>
+ %4 = shufflevector <16 x i8> %1, <16 x i8> %1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11>
+ %5 = tail call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %3, <16 x i8> %4)
+ %6 = extractelement <2 x i64> %5, i32 0
+ store i64 %6, ptr %p0
+ ret void
+}
+
; TODO: Each PSADBW source element has a maximum value of 3 - so max sum-of-diffs for each <8 x i8> should be 24.
define <2 x i64> @combine_psadbw_cmp_knownbits(<16 x i8> %a0) nounwind {
; X86-SSE-LABEL: combine_psadbw_cmp_knownbits:
diff --git a/llvm/test/CodeGen/X86/sad_variations.ll b/llvm/test/CodeGen/X86/sad_variations.ll
index 749bf1cccfa18..ce040ab779bc8 100644
--- a/llvm/test/CodeGen/X86/sad_variations.ll
+++ b/llvm/test/CodeGen/X86/sad_variations.ll
@@ -144,7 +144,7 @@ define i64 @sad8_64bit_icmp_sext_slt(ptr nocapture readonly %cur, ptr nocapture
; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; SSE2-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
; SSE2-NEXT: psadbw %xmm0, %xmm1
-; SSE2-NEXT: movq %xmm1, %rax
+; SSE2-NEXT: movd %xmm1, %eax
; SSE2-NEXT: retq
;
; AVX-LABEL: sad8_64bit_icmp_sext_slt:
@@ -152,7 +152,7 @@ define i64 @sad8_64bit_icmp_sext_slt(ptr nocapture readonly %cur, ptr nocapture
; AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; AVX-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
; AVX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vmovq %xmm0, %rax
+; AVX-NEXT: vmovd %xmm0, %eax
; AVX-NEXT: retq
entry:
br label %for.body
@@ -177,7 +177,7 @@ define i64 @sad8_64bit_icmp_zext_slt(ptr nocapture readonly %cur, ptr nocapture
; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; SSE2-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
; SSE2-NEXT: psadbw %xmm0, %xmm1
-; SSE2-NEXT: movq %xmm1, %rax
+; SSE2-NEXT: movd %xmm1, %eax
; SSE2-NEXT: retq
;
; AVX-LABEL: sad8_64bit_icmp_zext_slt:
@@ -185,7 +185,7 @@ define i64 @sad8_64bit_icmp_zext_slt(ptr nocapture readonly %cur, ptr nocapture
; AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; AVX-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
; AVX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vmovq %xmm0, %rax
+; AVX-NEXT: vmovd %xmm0, %eax
; AVX-NEXT: retq
entry:
br label %for.body
@@ -210,7 +210,7 @@ define i64 @sad8_early_64bit_icmp_zext_slt(ptr nocapture readonly %cur, ptr noca
; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; SSE2-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
; SSE2-NEXT: psadbw %xmm0, %xmm1
-; SSE2-NEXT: movq %xmm1, %rax
+; SSE2-NEXT: movd %xmm1, %eax
; SSE2-NEXT: retq
;
; AVX-LABEL: sad8_early_64bit_icmp_zext_slt:
@@ -218,7 +218,7 @@ define i64 @sad8_early_64bit_icmp_zext_slt(ptr nocapture readonly %cur, ptr noca
; AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; AVX-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
; AVX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vmovq %xmm0, %rax
+; AVX-NEXT: vmovd %xmm0, %eax
; AVX-NEXT: retq
entry:
br label %for.body
diff --git a/llvm/test/CodeGen/X86/trunc-subvector.ll b/llvm/test/CodeGen/X86/trunc-subvector.ll
index 9db2f6ba1e810..563e7315e2e9a 100644
--- a/llvm/test/CodeGen/X86/trunc-subvector.ll
+++ b/llvm/test/CodeGen/X86/trunc-subvector.ll
@@ -189,7 +189,7 @@ define <2 x i32> @test10(<8 x i32> %v) {
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpextrq $1, %xmm1, %rax
; AVX512-NEXT: vextracti32x4 $2, %zmm0, %xmm0
-; AVX512-NEXT: vmovq %xmm0, %rcx
+; AVX512-NEXT: vmovd %xmm0, %ecx
; AVX512-NEXT: vmovd %eax, %xmm0
; AVX512-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
; AVX512-NEXT: vzeroupper
diff --git a/llvm/test/CodeGen/X86/ucmp.ll b/llvm/test/CodeGen/X86/ucmp.ll
index 1aa86a38274be..65836384894ef 100644
--- a/llvm/test/CodeGen/X86/ucmp.ll
+++ b/llvm/test/CodeGen/X86/ucmp.ll
@@ -1493,7 +1493,8 @@ define <17 x i2> @ucmp_uncommon_vectors(<17 x i71> %x, <17 x i71> %y) nounwind {
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm3
; SSE4-NEXT: pshufd {{.*#+}} xmm3 = xmm3[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm3
-; SSE4-NEXT: movq %xmm3, %rbx
+; SSE4-NEXT: movd %xmm3, %eax
+; SSE4-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm3
; SSE4-NEXT: pshufd {{.*#+}} xmm3 = xmm3[2,3,2,3]
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm4
@@ -1502,7 +1503,7 @@ define <17 x i2> @ucmp_uncommon_vectors(<17 x i71> %x, <17 x i71> %y) nounwind {
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm5
; SSE4-NEXT: pshufd {{.*#+}} xmm5 = xmm5[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm5
-; SSE4-NEXT: movq %xmm5, %r13
+; SSE4-NEXT: movd %xmm5, %ebx
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm5
; SSE4-NEXT: pshufd {{.*#+}} xmm5 = xmm5[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm5
@@ -1511,7 +1512,7 @@ define <17 x i2> @ucmp_uncommon_vectors(<17 x i71> %x, <17 x i71> %y) nounwind {
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm7
; SSE4-NEXT: pshufd {{.*#+}} xmm7 = xmm7[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm7
-; SSE4-NEXT: movq %xmm7, %rcx
+; SSE4-NEXT: movd %xmm7, %r10d
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm7
; SSE4-NEXT: pshufd {{.*#+}} xmm7 = xmm7[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm7
@@ -1521,7 +1522,7 @@ define <17 x i2> @ucmp_uncommon_vectors(<17 x i71> %x, <17 x i71> %y) nounwind {
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm9
; SSE4-NEXT: pshufd {{.*#+}} xmm9 = xmm9[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm9
-; SSE4-NEXT: movq %xmm9, %rax
+; SSE4-NEXT: movd %xmm9, %ecx
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm9
; SSE4-NEXT: pshufd {{.*#+}} xmm9 = xmm9[2,3,2,3]
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm10
@@ -1530,11 +1531,11 @@ define <17 x i2> @ucmp_uncommon_vectors(<17 x i71> %x, <17 x i71> %y) nounwind {
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm11
; SSE4-NEXT: pshufd {{.*#+}} xmm11 = xmm11[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm11
-; SSE4-NEXT: movq %xmm11, %rbp
+; SSE4-NEXT: movd %xmm11, %r13d
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm11
; SSE4-NEXT: pshufd {{.*#+}} xmm11 = xmm11[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm11
-; SSE4-NEXT: movq %xmm11, %r10
+; SSE4-NEXT: movd %xmm11, %ebp
; SSE4-NEXT: andl $127, %edx
; SSE4-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; SSE4-NEXT: andl $127, %r8d
@@ -1544,266 +1545,267 @@ define <17 x i2> @ucmp_uncommon_vectors(<17 x i71> %x, <17 x i71> %y) nounwind {
; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r11
; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r14
; SSE4-NEXT: cmpq %r11, %r14
-; SSE4-NEXT: movq %r10, %r15
-; SSE4-NEXT: sbbq %rbp, %r15
-; SSE4-NEXT: movq %xmm10, %r15
+; SSE4-NEXT: movq %rbp, %r15
+; SSE4-NEXT: sbbq %r13, %r15
+; SSE4-NEXT: movd %xmm10, %r15d
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm10
; SSE4-NEXT: pshufd {{.*#+}} xmm10 = xmm10[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm10
-; SSE4-NEXT: setb %dl
+; SSE4-NEXT: setb %al
; SSE4-NEXT: cmpq %r14, %r11
-; SSE4-NEXT: movq %xmm10, %r11
-; SSE4-NEXT: sbbq %r10, %rbp
+; SSE4-NEXT: movd %xmm10, %r11d
+; SSE4-NEXT: sbbq %rbp, %r13
+; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rdx
; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r8
-; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r10
-; SSE4-NEXT: sbbb $0, %dl
-; SSE4-NEXT: movb %dl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill
-; SSE4-NEXT: cmpq %r8, %r10
+; SSE4-NEXT: sbbb $0, %al
+; SSE4-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill
+; SSE4-NEXT: cmpq %rdx, %r8
; SSE4-NEXT: movq %r11, %r14
; SSE4-NEXT: sbbq %r15, %r14
; SSE4-NEXT: pand %xmm0, %xmm9
-; SSE4-NEXT: setb %dl
-; SSE4-NEXT: cmpq %r10, %r8
-; SSE4-NEXT: movq %xmm9, %r8
-; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; SSE4-NEXT: setb %al
+; SSE4-NEXT: cmpq %r8, %rdx
+; SSE4-NEXT: movd %xmm9, %edx
+; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r8
; SSE4-NEXT: sbbq %r11, %r15
; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r11
-; SSE4-NEXT: sbbb $0, %dl
-; SSE4-NEXT: movb %dl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill
-; SSE4-NEXT: cmpq %r10, %r11
-; SSE4-NEXT: movq %r8, %r14
-; SSE4-NEXT: sbbq %rax, %r14
-; SSE4-NEXT: movq %xmm8, %r14
+; SSE4-NEXT: sbbb $0, %al
+; SSE4-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill
+; SSE4-NEXT: cmpq %r8, %r11
+; SSE4-NEXT: movq %rdx, %r14
+; SSE4-NEXT: sbbq %rcx, %r14
+; SSE4-NEXT: movd %xmm8, %r14d
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm8
; SSE4-NEXT: pshufd {{.*#+}} xmm8 = xmm8[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm8
-; SSE4-NEXT: setb %bpl
-; SSE4-NEXT: cmpq %r11, %r10
-; SSE4-NEXT: movq %xmm8, %r10
+; SSE4-NEXT: setb %al
+; SSE4-NEXT: cmpq %r11, %r8
+; SSE4-NEXT: movd %xmm8, %r8d
; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r11
-; SSE4-NEXT: sbbq %r8, %rax
-; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rdx
-; SSE4-NEXT: sbbb $0, %bpl
-; SSE4-NEXT: movb %bpl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill
-; SSE4-NEXT: cmpq %r11, %rdx
-; SSE4-NEXT: movq %r10, %r8
-; SSE4-NEXT: sbbq %r14, %r8
+; SSE4-NEXT: sbbq %rdx, %rcx
+; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rcx
+; SSE4-NEXT: sbbb $0, %al
+; SSE4-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill
+; SSE4-NEXT: cmpq %r11, %rcx
+; SSE4-NEXT: movq %r8, %rdx
+; SSE4-NEXT: sbbq %r14, %rdx
; SSE4-NEXT: setb %al
-; SSE4-NEXT: cmpq %rdx, %r11
-; SSE4-NEXT: movq %xmm7, %rdx
-; SSE4-NEXT: sbbq %r10, %r14
+; SSE4-NEXT: cmpq %rcx, %r11
+; SSE4-NEXT: movd %xmm7, %ecx
+; SSE4-NEXT: sbbq %r8, %r14
+; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rdx
; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r8
-; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r10
; SSE4-NEXT: sbbb $0, %al
; SSE4-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill
-; SSE4-NEXT: cmpq %r8, %r10
-; SSE4-NEXT: movq %rdx, %r11
-; SSE4-NEXT: sbbq %rcx, %r11
+; SSE4-NEXT: cmpq %rdx, %r8
+; SSE4-NEXT: movq %rcx, %r11
+; SSE4-NEXT: sbbq %r10, %r11
; SSE4-NEXT: pand %xmm0, %xmm6
-; SSE4-NEXT: movq %xmm6, %r11
+; SSE4-NEXT: movd %xmm6, %r11d
; SSE4-NEXT...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/207615
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