[llvm] [X86] Attempt to narrow XMM->i64 (v)movq -> (v)movd if the upper 32-bits are known to be zero (PR #207615)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 5 14:47:38 PDT 2026
https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/207615
Add a custom 'X86upperzero' tablegen pattern to match vectors where the upper half bits of every element is known zero.
Saves 1 byte by using (V)MOVD instead of (V)MOVQ - and avoids differences in X86/X64 codegen that was bloating diffs in some upcoming VECREDUCE_ADD work.
I've added an extra psadbw.ll test to ensure that the extractstore pattern isn't being affected.
Cleanup for the upcoming VECREDUCE_ADD handling which will be using PSADBW more aggressively (v2i64 result type but only 16 active bits for element).
>From aff711a6e3e10022dbb08cfc423ea98f7551a647 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Sun, 5 Jul 2026 22:46:06 +0100
Subject: [PATCH] [X86] Attempt to narrow XMM->i64 (v)movq -> (v)movd if the
upper 32-bits are known to be zero
Add a custom 'X86upperzero' tablegen pattern to match vectors where the upper half bits of every element is known zero.
Saves 1 byte by using (V)MOVD instead of (V)MOVQ - and avoids differences in X86/X64 codegen that was bloating diffs in some upcoming VECREDUCE_ADD work.
I've added an extra psadbw.ll test to ensure that the extractstore pattern isn't being affected.
Cleanup for the upcoming VECREDUCE_ADD handling which will be using PSADBW more aggressively (v2i64 result type but only 16 active bits for element).
---
llvm/lib/Target/X86/X86InstrAVX512.td | 9 +
llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 9 +
llvm/lib/Target/X86/X86InstrSSE.td | 13 +
llvm/test/CodeGen/X86/divrem-by-select.ll | 16 +-
llvm/test/CodeGen/X86/insertelement-zero.ll | 2 +-
.../CodeGen/X86/legalize-vec-assertzext.ll | 4 +-
llvm/test/CodeGen/X86/psadbw.ll | 32 +-
llvm/test/CodeGen/X86/sad_variations.ll | 12 +-
llvm/test/CodeGen/X86/trunc-subvector.ll | 2 +-
llvm/test/CodeGen/X86/ucmp.ll | 348 +++++++++---------
llvm/test/CodeGen/X86/udiv_fix.ll | 10 +-
llvm/test/CodeGen/X86/udiv_fix_sat.ll | 6 +-
llvm/test/CodeGen/X86/vector-compress.ll | 12 +-
.../CodeGen/X86/vector-reduce-add-mask.ll | 32 +-
.../CodeGen/X86/vector-reduce-add-zext.ll | 20 +-
llvm/test/CodeGen/X86/vector-reduce-ctpop.ll | 42 +--
16 files changed, 315 insertions(+), 254 deletions(-)
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index 1584c828f73d4..36bbd53c95817 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -3914,6 +3914,15 @@ let Predicates = [HasAVX512] in {
(VMOVPQI2QIZmr addr:$dst, VR128X:$src)>;
}
+//===---------------------------------------------------------------------===//
+// If the upper 32 bits of v2i64 elements are zero, we can use (v)movd instead.
+let AddedComplexity = 10 in {
+ let Predicates = [HasAVX512] in {
+ def : Pat<(i64 (extractelt (X86upperzero<v2i64, VR128X>:$src), (iPTR 0))),
+ (SUBREG_TO_REG (VMOVPDI2DIZrr VR128:$src), sub_32bit)>;
+ }
+}
+
// Move Scalar Single to Double Int
//
let ExeDomain = SSEPackedInt, isCodeGenOnly = 1 in {
diff --git a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
index 572309941c204..ee870669b05cf 100644
--- a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
+++ b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
@@ -1377,6 +1377,15 @@ def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
+// Match node if each vector elements' upper half bits are zero.
+class X86upperzero <ValueType vt, RegisterClass rc> : PatLeaf<(vt rc:$src), [{
+ unsigned EltBits = Op.getScalarValueSizeInBits();
+ APInt UpperMask = APInt::getHighBitsSet(EltBits, EltBits / 2);
+ return CurDAG->MaskedValueIsZero(Op, UpperMask);
+}]> {
+ let GISelPredicateCode = [{return false;}]; // TODO
+}
+
// Match node that has known zeros in every element except the lowest.
class X86vzelts <ValueType vt, RegisterClass rc> : PatLeaf<(vt rc:$src), [{
unsigned NumElts = Op.getValueType().getVectorNumElements();
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index f53a79fb2f9f9..fbabffc9a6f98 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -4249,6 +4249,19 @@ def MOVPQIto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
Sched<[WriteVecStore]>;
} // ExeDomain = SSEPackedInt
+//===---------------------------------------------------------------------===//
+// If the upper 32 bits of v2i64 elements are zero, we can use (v)movd instead.
+let AddedComplexity = 10 in {
+ let Predicates = [UseAVX] in {
+ def : Pat<(i64 (extractelt (X86upperzero<v2i64, VR128>:$src), (iPTR 0))),
+ (SUBREG_TO_REG (VMOVPDI2DIrr VR128:$src), sub_32bit)>;
+ }
+ let Predicates = [UseSSE2] in {
+ def : Pat<(i64 (extractelt (X86upperzero<v2i64, VR128>:$src), (iPTR 0))),
+ (SUBREG_TO_REG (MOVPDI2DIrr VR128:$src), sub_32bit)>;
+ }
+}
+
//===---------------------------------------------------------------------===//
// Bitcast FR64 <-> GR64
//
diff --git a/llvm/test/CodeGen/X86/divrem-by-select.ll b/llvm/test/CodeGen/X86/divrem-by-select.ll
index f9582bb7343ba..b80531881fa65 100644
--- a/llvm/test/CodeGen/X86/divrem-by-select.ll
+++ b/llvm/test/CodeGen/X86/divrem-by-select.ll
@@ -148,7 +148,7 @@ define <2 x i64> @udiv_indentity_zero(<2 x i1> %c, <2 x i64> %x) {
; CHECK-X64-V3-NEXT: divq %rcx
; CHECK-X64-V3-NEXT: movq %rax, %rcx
; CHECK-X64-V3-NEXT: vmovq %xmm1, %rax
-; CHECK-X64-V3-NEXT: vmovq %xmm0, %rsi
+; CHECK-X64-V3-NEXT: vmovd %xmm0, %esi
; CHECK-X64-V3-NEXT: xorl %edx, %edx
; CHECK-X64-V3-NEXT: divq %rsi
; CHECK-X64-V3-NEXT: vmovq %rcx, %xmm0
@@ -168,7 +168,7 @@ define <2 x i64> @udiv_indentity_zero(<2 x i1> %c, <2 x i64> %x) {
; CHECK-X64-V4-NEXT: divq %rcx
; CHECK-X64-V4-NEXT: movq %rax, %rcx
; CHECK-X64-V4-NEXT: vmovq %xmm1, %rax
-; CHECK-X64-V4-NEXT: vmovq %xmm0, %rsi
+; CHECK-X64-V4-NEXT: vmovd %xmm0, %esi
; CHECK-X64-V4-NEXT: xorl %edx, %edx
; CHECK-X64-V4-NEXT: divq %rsi
; CHECK-X64-V4-NEXT: vmovq %rcx, %xmm0
@@ -257,7 +257,7 @@ define <2 x i64> @urem_identity_const(<2 x i1> %c, <2 x i64> %x) {
; CHECK-X64-V4-NEXT: xorl %edx, %edx
; CHECK-X64-V4-NEXT: divq %rcx
; CHECK-X64-V4-NEXT: movq %rdx, %rcx
-; CHECK-X64-V4-NEXT: vmovq %xmm0, %rsi
+; CHECK-X64-V4-NEXT: vmovd %xmm0, %esi
; CHECK-X64-V4-NEXT: vmovq %xmm1, %rax
; CHECK-X64-V4-NEXT: xorl %edx, %edx
; CHECK-X64-V4-NEXT: divq %rsi
@@ -302,7 +302,7 @@ define <2 x i64> @sdiv_identity_const(<2 x i1> %c, <2 x i64> %x) {
; CHECK-X64-V4-NEXT: cqto
; CHECK-X64-V4-NEXT: idivq %rcx
; CHECK-X64-V4-NEXT: movq %rax, %rcx
-; CHECK-X64-V4-NEXT: vmovq %xmm0, %rsi
+; CHECK-X64-V4-NEXT: vmovd %xmm0, %esi
; CHECK-X64-V4-NEXT: vmovq %xmm1, %rax
; CHECK-X64-V4-NEXT: cqto
; CHECK-X64-V4-NEXT: idivq %rsi
@@ -347,7 +347,7 @@ define <2 x i64> @sdiv_identity_const_todo_better_nonzero(<2 x i1> %c, <2 x i64>
; CHECK-X64-V4-NEXT: cqto
; CHECK-X64-V4-NEXT: idivq %rcx
; CHECK-X64-V4-NEXT: movq %rax, %rcx
-; CHECK-X64-V4-NEXT: vmovq %xmm0, %rsi
+; CHECK-X64-V4-NEXT: vmovd %xmm0, %esi
; CHECK-X64-V4-NEXT: vmovq %xmm1, %rax
; CHECK-X64-V4-NEXT: cqto
; CHECK-X64-V4-NEXT: idivq %rsi
@@ -392,7 +392,7 @@ define <2 x i64> @srem_identity_const(<2 x i1> %c, <2 x i64> %x) {
; CHECK-X64-V4-NEXT: cqto
; CHECK-X64-V4-NEXT: idivq %rcx
; CHECK-X64-V4-NEXT: movq %rdx, %rcx
-; CHECK-X64-V4-NEXT: vmovq %xmm0, %rsi
+; CHECK-X64-V4-NEXT: vmovd %xmm0, %esi
; CHECK-X64-V4-NEXT: vmovq %xmm1, %rax
; CHECK-X64-V4-NEXT: cqto
; CHECK-X64-V4-NEXT: idivq %rsi
@@ -443,7 +443,7 @@ define <2 x i64> @udivrem_identity_const(<2 x i1> %c, <2 x i64> %x) {
; CHECK-X64-V4-NEXT: divq %rcx
; CHECK-X64-V4-NEXT: movq %rax, %rcx
; CHECK-X64-V4-NEXT: movq %rdx, %rsi
-; CHECK-X64-V4-NEXT: vmovq %xmm0, %rdi
+; CHECK-X64-V4-NEXT: vmovd %xmm0, %edi
; CHECK-X64-V4-NEXT: vmovq %xmm1, %rax
; CHECK-X64-V4-NEXT: xorl %edx, %edx
; CHECK-X64-V4-NEXT: divq %rdi
@@ -500,7 +500,7 @@ define <2 x i64> @sdivrem_identity_const(<2 x i1> %c, <2 x i64> %x) {
; CHECK-X64-V4-NEXT: idivq %rcx
; CHECK-X64-V4-NEXT: movq %rax, %rcx
; CHECK-X64-V4-NEXT: movq %rdx, %rsi
-; CHECK-X64-V4-NEXT: vmovq %xmm0, %rdi
+; CHECK-X64-V4-NEXT: vmovd %xmm0, %edi
; CHECK-X64-V4-NEXT: vmovq %xmm1, %rax
; CHECK-X64-V4-NEXT: cqto
; CHECK-X64-V4-NEXT: idivq %rdi
diff --git a/llvm/test/CodeGen/X86/insertelement-zero.ll b/llvm/test/CodeGen/X86/insertelement-zero.ll
index e1c8cefa73d8a..de1b51b14db6a 100644
--- a/llvm/test/CodeGen/X86/insertelement-zero.ll
+++ b/llvm/test/CodeGen/X86/insertelement-zero.ll
@@ -570,7 +570,7 @@ define i64 @fold_insertelement_to_and(i32 noundef %arg) {
; AVX2-NEXT: vpaddq %xmm0, %xmm0, %xmm1
; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vmovq %xmm0, %rax
+; AVX2-NEXT: vmovd %xmm0, %eax
; AVX2-NEXT: retq
%i = shufflevector <8 x i64> zeroinitializer, <8 x i64> splat (i64 77), <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 4, i32 8, i32 6, i32 10>
%i1 = insertelement <8 x i64> %i, i64 0, i64 0
diff --git a/llvm/test/CodeGen/X86/legalize-vec-assertzext.ll b/llvm/test/CodeGen/X86/legalize-vec-assertzext.ll
index b1d8243f26a0f..121f1bbb20daf 100644
--- a/llvm/test/CodeGen/X86/legalize-vec-assertzext.ll
+++ b/llvm/test/CodeGen/X86/legalize-vec-assertzext.ll
@@ -25,7 +25,7 @@ define i64 @widen_assertzext(ptr %x) nounwind {
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovdqa64 %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: vextracti32x4 $3, %zmm0, %xmm0
-; CHECK-NEXT: vmovq %xmm0, %rax
+; CHECK-NEXT: vmovd %xmm0, %eax
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
@@ -43,7 +43,7 @@ define i64 @widen_assertzext_range_attr(ptr %x) nounwind {
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vmovdqa64 %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: vextracti32x4 $3, %zmm0, %xmm0
-; CHECK-NEXT: vmovq %xmm0, %rax
+; CHECK-NEXT: vmovd %xmm0, %eax
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/psadbw.ll b/llvm/test/CodeGen/X86/psadbw.ll
index 354fb8b92e9d2..ccfb46a204800 100644
--- a/llvm/test/CodeGen/X86/psadbw.ll
+++ b/llvm/test/CodeGen/X86/psadbw.ll
@@ -31,13 +31,13 @@ define i64 @combine_psadbw_demandedelt(<16 x i8> %0, <16 x i8> %1) nounwind {
; X64-SSE-LABEL: combine_psadbw_demandedelt:
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: psadbw %xmm1, %xmm0
-; X64-SSE-NEXT: movq %xmm0, %rax
+; X64-SSE-NEXT: movd %xmm0, %eax
; X64-SSE-NEXT: retq
;
; AVX2-LABEL: combine_psadbw_demandedelt:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vmovq %xmm0, %rax
+; AVX2-NEXT: vmovd %xmm0, %eax
; AVX2-NEXT: retq
%3 = shufflevector <16 x i8> %0, <16 x i8> %0, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11>
%4 = shufflevector <16 x i8> %1, <16 x i8> %1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11>
@@ -46,6 +46,34 @@ define i64 @combine_psadbw_demandedelt(<16 x i8> %0, <16 x i8> %1) nounwind {
ret i64 %6
}
+; Ensure movq->movd narrowing doesn't affect the i64 store.
+define void @combine_psadbw_demandedelt_store(<16 x i8> %0, <16 x i8> %1, ptr %p0) nounwind {
+; X86-SSE-LABEL: combine_psadbw_demandedelt_store:
+; X86-SSE: # %bb.0:
+; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-SSE-NEXT: psadbw %xmm1, %xmm0
+; X86-SSE-NEXT: movq %xmm0, (%eax)
+; X86-SSE-NEXT: retl
+;
+; X64-SSE-LABEL: combine_psadbw_demandedelt_store:
+; X64-SSE: # %bb.0:
+; X64-SSE-NEXT: psadbw %xmm1, %xmm0
+; X64-SSE-NEXT: movq %xmm0, (%rdi)
+; X64-SSE-NEXT: retq
+;
+; AVX2-LABEL: combine_psadbw_demandedelt_store:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
+; AVX2-NEXT: vmovq %xmm0, (%rdi)
+; AVX2-NEXT: retq
+ %3 = shufflevector <16 x i8> %0, <16 x i8> %0, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11>
+ %4 = shufflevector <16 x i8> %1, <16 x i8> %1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11>
+ %5 = tail call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %3, <16 x i8> %4)
+ %6 = extractelement <2 x i64> %5, i32 0
+ store i64 %6, ptr %p0
+ ret void
+}
+
; TODO: Each PSADBW source element has a maximum value of 3 - so max sum-of-diffs for each <8 x i8> should be 24.
define <2 x i64> @combine_psadbw_cmp_knownbits(<16 x i8> %a0) nounwind {
; X86-SSE-LABEL: combine_psadbw_cmp_knownbits:
diff --git a/llvm/test/CodeGen/X86/sad_variations.ll b/llvm/test/CodeGen/X86/sad_variations.ll
index 749bf1cccfa18..ce040ab779bc8 100644
--- a/llvm/test/CodeGen/X86/sad_variations.ll
+++ b/llvm/test/CodeGen/X86/sad_variations.ll
@@ -144,7 +144,7 @@ define i64 @sad8_64bit_icmp_sext_slt(ptr nocapture readonly %cur, ptr nocapture
; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; SSE2-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
; SSE2-NEXT: psadbw %xmm0, %xmm1
-; SSE2-NEXT: movq %xmm1, %rax
+; SSE2-NEXT: movd %xmm1, %eax
; SSE2-NEXT: retq
;
; AVX-LABEL: sad8_64bit_icmp_sext_slt:
@@ -152,7 +152,7 @@ define i64 @sad8_64bit_icmp_sext_slt(ptr nocapture readonly %cur, ptr nocapture
; AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; AVX-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
; AVX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vmovq %xmm0, %rax
+; AVX-NEXT: vmovd %xmm0, %eax
; AVX-NEXT: retq
entry:
br label %for.body
@@ -177,7 +177,7 @@ define i64 @sad8_64bit_icmp_zext_slt(ptr nocapture readonly %cur, ptr nocapture
; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; SSE2-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
; SSE2-NEXT: psadbw %xmm0, %xmm1
-; SSE2-NEXT: movq %xmm1, %rax
+; SSE2-NEXT: movd %xmm1, %eax
; SSE2-NEXT: retq
;
; AVX-LABEL: sad8_64bit_icmp_zext_slt:
@@ -185,7 +185,7 @@ define i64 @sad8_64bit_icmp_zext_slt(ptr nocapture readonly %cur, ptr nocapture
; AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; AVX-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
; AVX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vmovq %xmm0, %rax
+; AVX-NEXT: vmovd %xmm0, %eax
; AVX-NEXT: retq
entry:
br label %for.body
@@ -210,7 +210,7 @@ define i64 @sad8_early_64bit_icmp_zext_slt(ptr nocapture readonly %cur, ptr noca
; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; SSE2-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
; SSE2-NEXT: psadbw %xmm0, %xmm1
-; SSE2-NEXT: movq %xmm1, %rax
+; SSE2-NEXT: movd %xmm1, %eax
; SSE2-NEXT: retq
;
; AVX-LABEL: sad8_early_64bit_icmp_zext_slt:
@@ -218,7 +218,7 @@ define i64 @sad8_early_64bit_icmp_zext_slt(ptr nocapture readonly %cur, ptr noca
; AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; AVX-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
; AVX-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX-NEXT: vmovq %xmm0, %rax
+; AVX-NEXT: vmovd %xmm0, %eax
; AVX-NEXT: retq
entry:
br label %for.body
diff --git a/llvm/test/CodeGen/X86/trunc-subvector.ll b/llvm/test/CodeGen/X86/trunc-subvector.ll
index 9db2f6ba1e810..563e7315e2e9a 100644
--- a/llvm/test/CodeGen/X86/trunc-subvector.ll
+++ b/llvm/test/CodeGen/X86/trunc-subvector.ll
@@ -189,7 +189,7 @@ define <2 x i32> @test10(<8 x i32> %v) {
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT: vpextrq $1, %xmm1, %rax
; AVX512-NEXT: vextracti32x4 $2, %zmm0, %xmm0
-; AVX512-NEXT: vmovq %xmm0, %rcx
+; AVX512-NEXT: vmovd %xmm0, %ecx
; AVX512-NEXT: vmovd %eax, %xmm0
; AVX512-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
; AVX512-NEXT: vzeroupper
diff --git a/llvm/test/CodeGen/X86/ucmp.ll b/llvm/test/CodeGen/X86/ucmp.ll
index 1aa86a38274be..65836384894ef 100644
--- a/llvm/test/CodeGen/X86/ucmp.ll
+++ b/llvm/test/CodeGen/X86/ucmp.ll
@@ -1493,7 +1493,8 @@ define <17 x i2> @ucmp_uncommon_vectors(<17 x i71> %x, <17 x i71> %y) nounwind {
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm3
; SSE4-NEXT: pshufd {{.*#+}} xmm3 = xmm3[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm3
-; SSE4-NEXT: movq %xmm3, %rbx
+; SSE4-NEXT: movd %xmm3, %eax
+; SSE4-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm3
; SSE4-NEXT: pshufd {{.*#+}} xmm3 = xmm3[2,3,2,3]
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm4
@@ -1502,7 +1503,7 @@ define <17 x i2> @ucmp_uncommon_vectors(<17 x i71> %x, <17 x i71> %y) nounwind {
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm5
; SSE4-NEXT: pshufd {{.*#+}} xmm5 = xmm5[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm5
-; SSE4-NEXT: movq %xmm5, %r13
+; SSE4-NEXT: movd %xmm5, %ebx
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm5
; SSE4-NEXT: pshufd {{.*#+}} xmm5 = xmm5[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm5
@@ -1511,7 +1512,7 @@ define <17 x i2> @ucmp_uncommon_vectors(<17 x i71> %x, <17 x i71> %y) nounwind {
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm7
; SSE4-NEXT: pshufd {{.*#+}} xmm7 = xmm7[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm7
-; SSE4-NEXT: movq %xmm7, %rcx
+; SSE4-NEXT: movd %xmm7, %r10d
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm7
; SSE4-NEXT: pshufd {{.*#+}} xmm7 = xmm7[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm7
@@ -1521,7 +1522,7 @@ define <17 x i2> @ucmp_uncommon_vectors(<17 x i71> %x, <17 x i71> %y) nounwind {
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm9
; SSE4-NEXT: pshufd {{.*#+}} xmm9 = xmm9[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm9
-; SSE4-NEXT: movq %xmm9, %rax
+; SSE4-NEXT: movd %xmm9, %ecx
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm9
; SSE4-NEXT: pshufd {{.*#+}} xmm9 = xmm9[2,3,2,3]
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm10
@@ -1530,11 +1531,11 @@ define <17 x i2> @ucmp_uncommon_vectors(<17 x i71> %x, <17 x i71> %y) nounwind {
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm11
; SSE4-NEXT: pshufd {{.*#+}} xmm11 = xmm11[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm11
-; SSE4-NEXT: movq %xmm11, %rbp
+; SSE4-NEXT: movd %xmm11, %r13d
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm11
; SSE4-NEXT: pshufd {{.*#+}} xmm11 = xmm11[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm11
-; SSE4-NEXT: movq %xmm11, %r10
+; SSE4-NEXT: movd %xmm11, %ebp
; SSE4-NEXT: andl $127, %edx
; SSE4-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; SSE4-NEXT: andl $127, %r8d
@@ -1544,266 +1545,267 @@ define <17 x i2> @ucmp_uncommon_vectors(<17 x i71> %x, <17 x i71> %y) nounwind {
; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r11
; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r14
; SSE4-NEXT: cmpq %r11, %r14
-; SSE4-NEXT: movq %r10, %r15
-; SSE4-NEXT: sbbq %rbp, %r15
-; SSE4-NEXT: movq %xmm10, %r15
+; SSE4-NEXT: movq %rbp, %r15
+; SSE4-NEXT: sbbq %r13, %r15
+; SSE4-NEXT: movd %xmm10, %r15d
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm10
; SSE4-NEXT: pshufd {{.*#+}} xmm10 = xmm10[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm10
-; SSE4-NEXT: setb %dl
+; SSE4-NEXT: setb %al
; SSE4-NEXT: cmpq %r14, %r11
-; SSE4-NEXT: movq %xmm10, %r11
-; SSE4-NEXT: sbbq %r10, %rbp
+; SSE4-NEXT: movd %xmm10, %r11d
+; SSE4-NEXT: sbbq %rbp, %r13
+; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rdx
; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r8
-; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r10
-; SSE4-NEXT: sbbb $0, %dl
-; SSE4-NEXT: movb %dl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill
-; SSE4-NEXT: cmpq %r8, %r10
+; SSE4-NEXT: sbbb $0, %al
+; SSE4-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill
+; SSE4-NEXT: cmpq %rdx, %r8
; SSE4-NEXT: movq %r11, %r14
; SSE4-NEXT: sbbq %r15, %r14
; SSE4-NEXT: pand %xmm0, %xmm9
-; SSE4-NEXT: setb %dl
-; SSE4-NEXT: cmpq %r10, %r8
-; SSE4-NEXT: movq %xmm9, %r8
-; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; SSE4-NEXT: setb %al
+; SSE4-NEXT: cmpq %r8, %rdx
+; SSE4-NEXT: movd %xmm9, %edx
+; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r8
; SSE4-NEXT: sbbq %r11, %r15
; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r11
-; SSE4-NEXT: sbbb $0, %dl
-; SSE4-NEXT: movb %dl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill
-; SSE4-NEXT: cmpq %r10, %r11
-; SSE4-NEXT: movq %r8, %r14
-; SSE4-NEXT: sbbq %rax, %r14
-; SSE4-NEXT: movq %xmm8, %r14
+; SSE4-NEXT: sbbb $0, %al
+; SSE4-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill
+; SSE4-NEXT: cmpq %r8, %r11
+; SSE4-NEXT: movq %rdx, %r14
+; SSE4-NEXT: sbbq %rcx, %r14
+; SSE4-NEXT: movd %xmm8, %r14d
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm8
; SSE4-NEXT: pshufd {{.*#+}} xmm8 = xmm8[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm8
-; SSE4-NEXT: setb %bpl
-; SSE4-NEXT: cmpq %r11, %r10
-; SSE4-NEXT: movq %xmm8, %r10
+; SSE4-NEXT: setb %al
+; SSE4-NEXT: cmpq %r11, %r8
+; SSE4-NEXT: movd %xmm8, %r8d
; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r11
-; SSE4-NEXT: sbbq %r8, %rax
-; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rdx
-; SSE4-NEXT: sbbb $0, %bpl
-; SSE4-NEXT: movb %bpl, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill
-; SSE4-NEXT: cmpq %r11, %rdx
-; SSE4-NEXT: movq %r10, %r8
-; SSE4-NEXT: sbbq %r14, %r8
+; SSE4-NEXT: sbbq %rdx, %rcx
+; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rcx
+; SSE4-NEXT: sbbb $0, %al
+; SSE4-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill
+; SSE4-NEXT: cmpq %r11, %rcx
+; SSE4-NEXT: movq %r8, %rdx
+; SSE4-NEXT: sbbq %r14, %rdx
; SSE4-NEXT: setb %al
-; SSE4-NEXT: cmpq %rdx, %r11
-; SSE4-NEXT: movq %xmm7, %rdx
-; SSE4-NEXT: sbbq %r10, %r14
+; SSE4-NEXT: cmpq %rcx, %r11
+; SSE4-NEXT: movd %xmm7, %ecx
+; SSE4-NEXT: sbbq %r8, %r14
+; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rdx
; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r8
-; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r10
; SSE4-NEXT: sbbb $0, %al
; SSE4-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill
-; SSE4-NEXT: cmpq %r8, %r10
-; SSE4-NEXT: movq %rdx, %r11
-; SSE4-NEXT: sbbq %rcx, %r11
+; SSE4-NEXT: cmpq %rdx, %r8
+; SSE4-NEXT: movq %rcx, %r11
+; SSE4-NEXT: sbbq %r10, %r11
; SSE4-NEXT: pand %xmm0, %xmm6
-; SSE4-NEXT: movq %xmm6, %r11
+; SSE4-NEXT: movd %xmm6, %r11d
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm6
; SSE4-NEXT: pshufd {{.*#+}} xmm6 = xmm6[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm6
; SSE4-NEXT: setb %al
-; SSE4-NEXT: cmpq %r10, %r8
-; SSE4-NEXT: movq %xmm6, %r8
-; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r10
-; SSE4-NEXT: sbbq %rdx, %rcx
+; SSE4-NEXT: cmpq %r8, %rdx
+; SSE4-NEXT: movd %xmm6, %edx
+; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r8
+; SSE4-NEXT: sbbq %rcx, %r10
; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; SSE4-NEXT: sbbb $0, %al
; SSE4-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill
-; SSE4-NEXT: cmpq %r10, %rcx
-; SSE4-NEXT: movq %r8, %rdx
-; SSE4-NEXT: sbbq %r11, %rdx
+; SSE4-NEXT: cmpq %r8, %rcx
+; SSE4-NEXT: movq %rdx, %r10
+; SSE4-NEXT: sbbq %r11, %r10
; SSE4-NEXT: setb %al
-; SSE4-NEXT: cmpq %rcx, %r10
-; SSE4-NEXT: movq %xmm5, %rcx
-; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rdx
-; SSE4-NEXT: sbbq %r8, %r11
+; SSE4-NEXT: cmpq %rcx, %r8
+; SSE4-NEXT: movd %xmm5, %ecx
; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r8
+; SSE4-NEXT: sbbq %rdx, %r11
+; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rdx
; SSE4-NEXT: sbbb $0, %al
; SSE4-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill
-; SSE4-NEXT: cmpq %rdx, %r8
+; SSE4-NEXT: cmpq %r8, %rdx
; SSE4-NEXT: movq %rcx, %r10
-; SSE4-NEXT: sbbq %r13, %r10
-; SSE4-NEXT: movq %xmm4, %r10
+; SSE4-NEXT: sbbq %rbx, %r10
+; SSE4-NEXT: movd %xmm4, %r11d
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm4
; SSE4-NEXT: pshufd {{.*#+}} xmm4 = xmm4[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm4
; SSE4-NEXT: setb %al
-; SSE4-NEXT: cmpq %r8, %rdx
-; SSE4-NEXT: movq %xmm4, %rdx
-; SSE4-NEXT: sbbq %rcx, %r13
+; SSE4-NEXT: cmpq %rdx, %r8
+; SSE4-NEXT: movd %xmm4, %edx
+; SSE4-NEXT: sbbq %rcx, %rbx
; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r8
; SSE4-NEXT: sbbb $0, %al
; SSE4-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill
; SSE4-NEXT: cmpq %rcx, %r8
-; SSE4-NEXT: movq %rdx, %r11
-; SSE4-NEXT: sbbq %r10, %r11
+; SSE4-NEXT: movq %rdx, %r14
+; SSE4-NEXT: sbbq %r11, %r14
; SSE4-NEXT: pand %xmm0, %xmm3
; SSE4-NEXT: setb %r13b
; SSE4-NEXT: cmpq %r8, %rcx
-; SSE4-NEXT: movq %xmm3, %rcx
-; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r8
-; SSE4-NEXT: sbbq %rdx, %r10
+; SSE4-NEXT: movd %xmm3, %r8d
+; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r14
+; SSE4-NEXT: sbbq %rdx, %r11
; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rdx
; SSE4-NEXT: sbbb $0, %r13b
-; SSE4-NEXT: cmpq %r8, %rdx
-; SSE4-NEXT: movq %rcx, %r10
-; SSE4-NEXT: sbbq %rbx, %r10
-; SSE4-NEXT: movq %xmm2, %r11
+; SSE4-NEXT: cmpq %r14, %rdx
+; SSE4-NEXT: movq %r8, %rcx
+; SSE4-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
+; SSE4-NEXT: sbbq %rax, %rcx
+; SSE4-NEXT: movd %xmm2, %r11d
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm2
; SSE4-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm2
-; SSE4-NEXT: setb %r14b
-; SSE4-NEXT: cmpq %rdx, %r8
-; SSE4-NEXT: movq %xmm2, %rdx
-; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r8
-; SSE4-NEXT: sbbq %rcx, %rbx
-; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rcx
-; SSE4-NEXT: sbbb $0, %r14b
-; SSE4-NEXT: cmpq %r8, %rcx
-; SSE4-NEXT: movq %rdx, %rbx
-; SSE4-NEXT: sbbq %r11, %rbx
-; SSE4-NEXT: setb %bl
-; SSE4-NEXT: cmpq %rcx, %r8
-; SSE4-NEXT: movq %xmm1, %rcx
+; SSE4-NEXT: setb %r10b
+; SSE4-NEXT: cmpq %rdx, %r14
+; SSE4-NEXT: movd %xmm2, %r14d
+; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r15
+; SSE4-NEXT: sbbq %r8, %rax
+; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; SSE4-NEXT: sbbb $0, %r10b
+; SSE4-NEXT: cmpq %r15, %rax
+; SSE4-NEXT: movq %r14, %rdx
+; SSE4-NEXT: sbbq %r11, %rdx
+; SSE4-NEXT: setb %dl
+; SSE4-NEXT: cmpq %rax, %r15
+; SSE4-NEXT: movd %xmm1, %eax
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm1
; SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm1
-; SSE4-NEXT: movq %xmm1, %r8
-; SSE4-NEXT: sbbq %rdx, %r11
+; SSE4-NEXT: movd %xmm1, %r15d
+; SSE4-NEXT: sbbq %r14, %r11
; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r11
-; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r15
-; SSE4-NEXT: sbbb $0, %bl
-; SSE4-NEXT: cmpq %r11, %r15
-; SSE4-NEXT: movq %r8, %rdx
-; SSE4-NEXT: sbbq %rcx, %rdx
+; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r14
+; SSE4-NEXT: sbbb $0, %dl
+; SSE4-NEXT: cmpq %r11, %r14
+; SSE4-NEXT: movq %r15, %r8
+; SSE4-NEXT: sbbq %rax, %r8
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm1
; SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm1
-; SSE4-NEXT: setb %r10b
-; SSE4-NEXT: cmpq %r15, %r11
-; SSE4-NEXT: movq %xmm1, %r11
+; SSE4-NEXT: setb %r8b
+; SSE4-NEXT: cmpq %r14, %r11
+; SSE4-NEXT: movd %xmm1, %r14d
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm1
; SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm1
-; SSE4-NEXT: movq %xmm1, %r15
-; SSE4-NEXT: sbbq %r8, %rcx
-; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rcx
-; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rbp
-; SSE4-NEXT: sbbb $0, %r10b
-; SSE4-NEXT: cmpq %rcx, %rbp
-; SSE4-NEXT: movq %r15, %r8
-; SSE4-NEXT: sbbq %r11, %r8
-; SSE4-NEXT: setb %r8b
-; SSE4-NEXT: cmpq %rbp, %rcx
+; SSE4-NEXT: movd %xmm1, %ebp
+; SSE4-NEXT: sbbq %r15, %rax
+; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r15
+; SSE4-NEXT: sbbb $0, %r8b
+; SSE4-NEXT: cmpq %rax, %r15
+; SSE4-NEXT: movq %rbp, %r11
+; SSE4-NEXT: sbbq %r14, %r11
+; SSE4-NEXT: setb %r11b
+; SSE4-NEXT: cmpq %r15, %rax
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm1
; SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm1
-; SSE4-NEXT: movq %xmm1, %rcx
+; SSE4-NEXT: movd %xmm1, %eax
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm1
; SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm1
-; SSE4-NEXT: sbbq %r15, %r11
+; SSE4-NEXT: sbbq %rbp, %r14
+; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r14
; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r15
-; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rbp
-; SSE4-NEXT: sbbb $0, %r8b
-; SSE4-NEXT: cmpq %r15, %rbp
-; SSE4-NEXT: movq %xmm1, %rax
-; SSE4-NEXT: movq %rax, %r11
-; SSE4-NEXT: sbbq %rcx, %r11
-; SSE4-NEXT: setb %r11b
-; SSE4-NEXT: cmpq %rbp, %r15
+; SSE4-NEXT: sbbb $0, %r11b
+; SSE4-NEXT: cmpq %r14, %r15
+; SSE4-NEXT: movd %xmm1, %ebx
+; SSE4-NEXT: movq %rbx, %rbp
+; SSE4-NEXT: sbbq %rax, %rbp
+; SSE4-NEXT: setb %bpl
+; SSE4-NEXT: cmpq %r15, %r14
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm1
; SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm1
-; SSE4-NEXT: sbbq %rax, %rcx
-; SSE4-NEXT: movq %xmm1, %rax
-; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rcx
-; SSE4-NEXT: sbbb $0, %r11b
-; SSE4-NEXT: cmpq %r9, %rcx
-; SSE4-NEXT: movq %rax, %r15
-; SSE4-NEXT: sbbq %r12, %r15
-; SSE4-NEXT: setb %bpl
-; SSE4-NEXT: cmpq %rcx, %r9
+; SSE4-NEXT: sbbq %rbx, %rax
+; SSE4-NEXT: movd %xmm1, %eax
+; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rbx
+; SSE4-NEXT: sbbb $0, %bpl
+; SSE4-NEXT: cmpq %r9, %rbx
+; SSE4-NEXT: movq %rax, %r14
+; SSE4-NEXT: sbbq %r12, %r14
+; SSE4-NEXT: setb %r14b
+; SSE4-NEXT: cmpq %rbx, %r9
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm1
; SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm1
; SSE4-NEXT: sbbq %rax, %r12
-; SSE4-NEXT: movq %xmm1, %rax
-; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rcx
-; SSE4-NEXT: sbbb $0, %bpl
+; SSE4-NEXT: movd %xmm1, %eax
+; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rbx
+; SSE4-NEXT: sbbb $0, %r14b
; SSE4-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r12 # 8-byte Reload
-; SSE4-NEXT: cmpq %r12, %rcx
+; SSE4-NEXT: cmpq %r12, %rbx
; SSE4-NEXT: movq %rax, %r9
-; SSE4-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
-; SSE4-NEXT: sbbq %rdx, %r9
+; SSE4-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
+; SSE4-NEXT: sbbq %rcx, %r9
; SSE4-NEXT: movq %rdi, %r15
; SSE4-NEXT: setb %r9b
-; SSE4-NEXT: cmpq %rcx, %r12
+; SSE4-NEXT: cmpq %rbx, %r12
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm1
; SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm1
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm2
; SSE4-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm2
-; SSE4-NEXT: movq %xmm2, %r12
-; SSE4-NEXT: sbbq %rax, %rdx
+; SSE4-NEXT: movd %xmm2, %r12d
+; SSE4-NEXT: sbbq %rax, %rcx
; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rax
; SSE4-NEXT: sbbb $0, %r9b
; SSE4-NEXT: cmpq %rsi, %rax
-; SSE4-NEXT: movq %r12, %rcx
-; SSE4-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
-; SSE4-NEXT: sbbq %rdx, %rcx
-; SSE4-NEXT: movq %xmm1, %rdi
+; SSE4-NEXT: movq %r12, %rdi
+; SSE4-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
+; SSE4-NEXT: sbbq %rcx, %rdi
+; SSE4-NEXT: movd %xmm1, %edi
; SSE4-NEXT: movdqu {{[0-9]+}}(%rsp), %xmm1
; SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
; SSE4-NEXT: pand %xmm0, %xmm1
-; SSE4-NEXT: setb %cl
+; SSE4-NEXT: setb %bl
; SSE4-NEXT: cmpq %rax, %rsi
-; SSE4-NEXT: movq %xmm1, %rsi
-; SSE4-NEXT: sbbq %r12, %rdx
+; SSE4-NEXT: movd %xmm1, %esi
+; SSE4-NEXT: sbbq %r12, %rcx
; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %r12
-; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rdx
-; SSE4-NEXT: sbbb $0, %cl
-; SSE4-NEXT: cmpq %r12, %rdx
+; SSE4-NEXT: movq {{[0-9]+}}(%rsp), %rcx
+; SSE4-NEXT: sbbb $0, %bl
+; SSE4-NEXT: cmpq %r12, %rcx
; SSE4-NEXT: movq %rsi, %rax
; SSE4-NEXT: sbbq %rdi, %rax
; SSE4-NEXT: setb %al
-; SSE4-NEXT: cmpq %rdx, %r12
-; SSE4-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 1-byte Folded Reload
-; SSE4-NEXT: movd %edx, %xmm1
-; SSE4-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 1-byte Folded Reload
-; SSE4-NEXT: movd %edx, %xmm2
-; SSE4-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 1-byte Folded Reload
-; SSE4-NEXT: movd %edx, %xmm3
-; SSE4-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 1-byte Folded Reload
-; SSE4-NEXT: movd %edx, %xmm4
-; SSE4-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 1-byte Folded Reload
-; SSE4-NEXT: movd %edx, %xmm5
-; SSE4-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 1-byte Folded Reload
-; SSE4-NEXT: movd %edx, %xmm6
-; SSE4-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 1-byte Folded Reload
-; SSE4-NEXT: movd %edx, %xmm7
-; SSE4-NEXT: movzbl %r13b, %edx
-; SSE4-NEXT: movd %edx, %xmm0
-; SSE4-NEXT: movzbl %r14b, %edx
-; SSE4-NEXT: movd %edx, %xmm8
-; SSE4-NEXT: movzbl %bl, %edx
-; SSE4-NEXT: movd %edx, %xmm9
-; SSE4-NEXT: movzbl %r10b, %edx
-; SSE4-NEXT: movd %edx, %xmm10
-; SSE4-NEXT: movzbl %r8b, %edx
-; SSE4-NEXT: movd %edx, %xmm11
-; SSE4-NEXT: movzbl %r11b, %edx
-; SSE4-NEXT: movd %edx, %xmm12
-; SSE4-NEXT: movzbl %bpl, %edx
-; SSE4-NEXT: movd %edx, %xmm13
-; SSE4-NEXT: movzbl %r9b, %edx
-; SSE4-NEXT: movd %edx, %xmm14
-; SSE4-NEXT: movzbl %cl, %ecx
+; SSE4-NEXT: cmpq %rcx, %r12
+; SSE4-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 1-byte Folded Reload
+; SSE4-NEXT: movd %ecx, %xmm1
+; SSE4-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 1-byte Folded Reload
+; SSE4-NEXT: movd %ecx, %xmm2
+; SSE4-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 1-byte Folded Reload
+; SSE4-NEXT: movd %ecx, %xmm3
+; SSE4-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 1-byte Folded Reload
+; SSE4-NEXT: movd %ecx, %xmm4
+; SSE4-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 1-byte Folded Reload
+; SSE4-NEXT: movd %ecx, %xmm5
+; SSE4-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 1-byte Folded Reload
+; SSE4-NEXT: movd %ecx, %xmm6
+; SSE4-NEXT: movzbl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 1-byte Folded Reload
+; SSE4-NEXT: movd %ecx, %xmm7
+; SSE4-NEXT: movzbl %r13b, %ecx
+; SSE4-NEXT: movd %ecx, %xmm0
+; SSE4-NEXT: movzbl %r10b, %ecx
+; SSE4-NEXT: movd %ecx, %xmm8
+; SSE4-NEXT: movzbl %dl, %ecx
+; SSE4-NEXT: movd %ecx, %xmm9
+; SSE4-NEXT: movzbl %r8b, %ecx
+; SSE4-NEXT: movd %ecx, %xmm10
+; SSE4-NEXT: movzbl %r11b, %ecx
+; SSE4-NEXT: movd %ecx, %xmm11
+; SSE4-NEXT: movzbl %bpl, %ecx
+; SSE4-NEXT: movd %ecx, %xmm12
+; SSE4-NEXT: movzbl %r14b, %ecx
+; SSE4-NEXT: movd %ecx, %xmm13
+; SSE4-NEXT: movzbl %r9b, %ecx
+; SSE4-NEXT: movd %ecx, %xmm14
+; SSE4-NEXT: movzbl %bl, %ecx
; SSE4-NEXT: movd %ecx, %xmm15
; SSE4-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3],xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
; SSE4-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3],xmm4[4],xmm3[4],xmm4[5],xmm3[5],xmm4[6],xmm3[6],xmm4[7],xmm3[7]
diff --git a/llvm/test/CodeGen/X86/udiv_fix.ll b/llvm/test/CodeGen/X86/udiv_fix.ll
index 82dfeeee13293..6e653a67fba2b 100644
--- a/llvm/test/CodeGen/X86/udiv_fix.ll
+++ b/llvm/test/CodeGen/X86/udiv_fix.ll
@@ -240,13 +240,13 @@ define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
; X64-LABEL: vec:
; X64: # %bb.0:
; X64-NEXT: pxor %xmm2, %xmm2
-; X64-NEXT: movdqa %xmm1, %xmm3
-; X64-NEXT: punpckhdq {{.*#+}} xmm3 = xmm3[2],xmm2[2],xmm3[3],xmm2[3]
-; X64-NEXT: movq %xmm3, %rcx
; X64-NEXT: movdqa %xmm0, %xmm4
; X64-NEXT: punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm2[2],xmm4[3],xmm2[3]
; X64-NEXT: psllq $31, %xmm4
; X64-NEXT: movq %xmm4, %rax
+; X64-NEXT: movdqa %xmm1, %xmm3
+; X64-NEXT: punpckhdq {{.*#+}} xmm3 = xmm3[2],xmm2[2],xmm3[3],xmm2[3]
+; X64-NEXT: movd %xmm3, %ecx
; X64-NEXT: xorl %edx, %edx
; X64-NEXT: divq %rcx
; X64-NEXT: movq %rax, %xmm3
@@ -254,7 +254,7 @@ define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
; X64-NEXT: movq %xmm4, %rax
; X64-NEXT: movdqa %xmm1, %xmm4
; X64-NEXT: psrldq {{.*#+}} xmm4 = xmm4[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; X64-NEXT: movq %xmm4, %rcx
+; X64-NEXT: movd %xmm4, %ecx
; X64-NEXT: xorl %edx, %edx
; X64-NEXT: divq %rcx
; X64-NEXT: movq %rax, %xmm4
@@ -269,7 +269,7 @@ define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
; X64-NEXT: movq %xmm0, %rax
; X64-NEXT: psrlq $32, %xmm1
-; X64-NEXT: movq %xmm1, %rcx
+; X64-NEXT: movd %xmm1, %ecx
; X64-NEXT: xorl %edx, %edx
; X64-NEXT: divq %rcx
; X64-NEXT: movq %rax, %xmm0
diff --git a/llvm/test/CodeGen/X86/udiv_fix_sat.ll b/llvm/test/CodeGen/X86/udiv_fix_sat.ll
index d1e9145c4ccee..2c4716bb74e70 100644
--- a/llvm/test/CodeGen/X86/udiv_fix_sat.ll
+++ b/llvm/test/CodeGen/X86/udiv_fix_sat.ll
@@ -317,7 +317,7 @@ define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
; X64-NEXT: movq %xmm3, %rax
; X64-NEXT: movdqa %xmm1, %xmm4
; X64-NEXT: punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm2[2],xmm4[3],xmm2[3]
-; X64-NEXT: movq %xmm4, %rcx
+; X64-NEXT: movd %xmm4, %ecx
; X64-NEXT: xorl %edx, %edx
; X64-NEXT: divq %rcx
; X64-NEXT: movq %rax, %xmm8
@@ -325,7 +325,7 @@ define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
; X64-NEXT: movq %xmm3, %rax
; X64-NEXT: movdqa %xmm1, %xmm3
; X64-NEXT: psrldq {{.*#+}} xmm3 = xmm3[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
-; X64-NEXT: movq %xmm3, %rcx
+; X64-NEXT: movd %xmm3, %ecx
; X64-NEXT: xorl %edx, %edx
; X64-NEXT: divq %rcx
; X64-NEXT: movq %rax, %xmm3
@@ -357,7 +357,7 @@ define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,2,3]
; X64-NEXT: movq %xmm0, %rax
; X64-NEXT: psrlq $32, %xmm1
-; X64-NEXT: movq %xmm1, %rcx
+; X64-NEXT: movd %xmm1, %ecx
; X64-NEXT: xorl %edx, %edx
; X64-NEXT: divq %rcx
; X64-NEXT: movq %rax, %xmm0
diff --git a/llvm/test/CodeGen/X86/vector-compress.ll b/llvm/test/CodeGen/X86/vector-compress.ll
index 22c8cd692400c..a0548ce8abdc3 100644
--- a/llvm/test/CodeGen/X86/vector-compress.ll
+++ b/llvm/test/CodeGen/X86/vector-compress.ll
@@ -449,7 +449,7 @@ define <4 x i64> @test_compress_v4i64(<4 x i64> %vec, <4 x i1> %mask, <4 x i64>
; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm3
; AVX2-NEXT: vpaddq %xmm3, %xmm2, %xmm2
; AVX2-NEXT: vpextrq $1, %xmm2, %rcx
-; AVX2-NEXT: vmovq %xmm2, %rax
+; AVX2-NEXT: vmovd %xmm2, %eax
; AVX2-NEXT: addl %ecx, %eax
; AVX2-NEXT: andl $3, %eax
; AVX2-NEXT: vpextrq $1, %xmm1, %rcx
@@ -521,7 +521,7 @@ define <4 x double> @test_compress_v4f64(<4 x double> %vec, <4 x i1> %mask, <4 x
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
; AVX2-NEXT: vpaddq %xmm2, %xmm1, %xmm1
; AVX2-NEXT: vpextrq $1, %xmm1, %rax
-; AVX2-NEXT: vmovq %xmm1, %rcx
+; AVX2-NEXT: vmovd %xmm1, %ecx
; AVX2-NEXT: addl %eax, %ecx
; AVX2-NEXT: andl $3, %ecx
; AVX2-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
@@ -900,7 +900,7 @@ define <8 x i64> @test_compress_v8i64(<8 x i64> %vec, <8 x i1> %mask, <8 x i64>
; AVX2-NEXT: vextracti128 $1, %ymm3, %xmm4
; AVX2-NEXT: vpaddq %xmm4, %xmm3, %xmm3
; AVX2-NEXT: vpextrq $1, %xmm3, %rcx
-; AVX2-NEXT: vmovq %xmm3, %rax
+; AVX2-NEXT: vmovd %xmm3, %eax
; AVX2-NEXT: addl %ecx, %eax
; AVX2-NEXT: andl $7, %eax
; AVX2-NEXT: vpextrw $1, %xmm2, %ecx
@@ -992,7 +992,7 @@ define <8 x double> @test_compress_v8f64(<8 x double> %vec, <8 x i1> %mask, <8 x
; AVX2-NEXT: vextracti128 $1, %ymm3, %xmm4
; AVX2-NEXT: vpaddq %xmm4, %xmm3, %xmm3
; AVX2-NEXT: vpextrq $1, %xmm3, %rax
-; AVX2-NEXT: vmovq %xmm3, %rcx
+; AVX2-NEXT: vmovd %xmm3, %ecx
; AVX2-NEXT: addl %eax, %ecx
; AVX2-NEXT: andl $7, %ecx
; AVX2-NEXT: vmovsd {{.*#+}} xmm3 = mem[0],zero
@@ -3510,7 +3510,7 @@ define <8 x i64> @test_compress_knownbits_zext_v8i16_8i64(<8 x i16> %vec, <8 x
; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm3
; AVX2-NEXT: vpaddq %xmm3, %xmm2, %xmm2
; AVX2-NEXT: vpextrq $1, %xmm2, %rcx
-; AVX2-NEXT: vmovq %xmm2, %rax
+; AVX2-NEXT: vmovd %xmm2, %eax
; AVX2-NEXT: addl %ecx, %eax
; AVX2-NEXT: andl $7, %eax
; AVX2-NEXT: vpextrw $1, %xmm1, %ecx
@@ -3614,7 +3614,7 @@ define <8 x i64> @test_compress_knownbits_sext_v8i16_8i64(<8 x i16> %vec, <8 x i
; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm3
; AVX2-NEXT: vpaddq %xmm3, %xmm2, %xmm2
; AVX2-NEXT: vpextrq $1, %xmm2, %rcx
-; AVX2-NEXT: vmovq %xmm2, %rax
+; AVX2-NEXT: vmovd %xmm2, %eax
; AVX2-NEXT: addl %ecx, %eax
; AVX2-NEXT: andl $7, %eax
; AVX2-NEXT: vpextrw $1, %xmm1, %ecx
diff --git a/llvm/test/CodeGen/X86/vector-reduce-add-mask.ll b/llvm/test/CodeGen/X86/vector-reduce-add-mask.ll
index b649facc8f2bb..bf09c79d579ea 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-add-mask.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-add-mask.ll
@@ -36,7 +36,7 @@ define i64 @test_v2i64_v2i32(<2 x i64> %a0) nounwind {
; X64-SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-SSE-NEXT: paddq %xmm0, %xmm1
-; X64-SSE-NEXT: movq %xmm1, %rax
+; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: retq
;
; X86-SSE4-LABEL: test_v2i64_v2i32:
@@ -62,7 +62,7 @@ define i64 @test_v2i64_v2i32(<2 x i64> %a0) nounwind {
; X64-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; X64-AVX1-NEXT: vmovq %xmm0, %rax
+; X64-AVX1-NEXT: vmovd %xmm0, %eax
; X64-AVX1-NEXT: retq
;
; X86-AVX2-LABEL: test_v2i64_v2i32:
@@ -79,7 +79,7 @@ define i64 @test_v2i64_v2i32(<2 x i64> %a0) nounwind {
; X64-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; X64-AVX2-NEXT: vmovq %xmm0, %rax
+; X64-AVX2-NEXT: vmovd %xmm0, %eax
; X64-AVX2-NEXT: retq
;
; AVX512F-LABEL: test_v2i64_v2i32:
@@ -87,7 +87,7 @@ define i64 @test_v2i64_v2i32(<2 x i64> %a0) nounwind {
; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512F-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; AVX512F-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; AVX512F-NEXT: vmovq %xmm0, %rax
+; AVX512F-NEXT: vmovd %xmm0, %eax
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: test_v2i64_v2i32:
@@ -95,7 +95,7 @@ define i64 @test_v2i64_v2i32(<2 x i64> %a0) nounwind {
; AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; AVX512VL-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; AVX512VL-NEXT: vmovq %xmm0, %rax
+; AVX512VL-NEXT: vmovd %xmm0, %eax
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: test_v2i64_v2i32:
@@ -103,7 +103,7 @@ define i64 @test_v2i64_v2i32(<2 x i64> %a0) nounwind {
; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; AVX512BW-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; AVX512BW-NEXT: vmovq %xmm0, %rax
+; AVX512BW-NEXT: vmovd %xmm0, %eax
; AVX512BW-NEXT: retq
;
; AVX512BWVL-LABEL: test_v2i64_v2i32:
@@ -111,7 +111,7 @@ define i64 @test_v2i64_v2i32(<2 x i64> %a0) nounwind {
; AVX512BWVL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512BWVL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; AVX512BWVL-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; AVX512BWVL-NEXT: vmovq %xmm0, %rax
+; AVX512BWVL-NEXT: vmovd %xmm0, %eax
; AVX512BWVL-NEXT: retq
%1 = and <2 x i64> %a0, <i64 255, i64 255>
%2 = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %1)
@@ -206,7 +206,7 @@ define i64 @test_v4i64_v4i16(<4 x i64> %a0) nounwind {
; AVX512F-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512F-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX512F-NEXT: vmovq %xmm0, %rax
+; AVX512F-NEXT: vmovd %xmm0, %eax
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
@@ -216,7 +216,7 @@ define i64 @test_v4i64_v4i16(<4 x i64> %a0) nounwind {
; AVX512VL-NEXT: vpmovqb %ymm0, %xmm0
; AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VL-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX512VL-NEXT: vmovq %xmm0, %rax
+; AVX512VL-NEXT: vmovd %xmm0, %eax
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
;
@@ -228,7 +228,7 @@ define i64 @test_v4i64_v4i16(<4 x i64> %a0) nounwind {
; AVX512BW-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BW-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX512BW-NEXT: vmovq %xmm0, %rax
+; AVX512BW-NEXT: vmovd %xmm0, %eax
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
;
@@ -238,7 +238,7 @@ define i64 @test_v4i64_v4i16(<4 x i64> %a0) nounwind {
; AVX512BWVL-NEXT: vpmovqb %ymm0, %xmm0
; AVX512BWVL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512BWVL-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX512BWVL-NEXT: vmovq %xmm0, %rax
+; AVX512BWVL-NEXT: vmovd %xmm0, %eax
; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq
%1 = and <4 x i64> %a0, <i64 15, i64 31, i64 63, i64 127>
@@ -374,7 +374,7 @@ define i64 @test_v8i64_v8i8(<8 x i64> %a0) nounwind {
; AVX512-NEXT: vpmovqb %zmm0, %xmm0
; AVX512-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vmovq %xmm0, %rax
+; AVX512-NEXT: vmovd %xmm0, %eax
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
%1 = lshr <8 x i64> %a0, <i64 60, i64 60, i64 60, i64 60, i64 60, i64 60, i64 60, i64 60>
@@ -606,7 +606,7 @@ define i64 @test_v16i64_v16i8(<16 x i64> %a0) nounwind {
; AVX512F-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX512F-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; AVX512F-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; AVX512F-NEXT: vmovq %xmm0, %rax
+; AVX512F-NEXT: vmovd %xmm0, %eax
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
@@ -620,7 +620,7 @@ define i64 @test_v16i64_v16i8(<16 x i64> %a0) nounwind {
; AVX512VL-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; AVX512VL-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; AVX512VL-NEXT: vmovq %xmm0, %rax
+; AVX512VL-NEXT: vmovd %xmm0, %eax
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
;
@@ -634,7 +634,7 @@ define i64 @test_v16i64_v16i8(<16 x i64> %a0) nounwind {
; AVX512BW-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX512BW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; AVX512BW-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; AVX512BW-NEXT: vmovq %xmm0, %rax
+; AVX512BW-NEXT: vmovd %xmm0, %eax
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
;
@@ -648,7 +648,7 @@ define i64 @test_v16i64_v16i8(<16 x i64> %a0) nounwind {
; AVX512BWVL-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX512BWVL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; AVX512BWVL-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; AVX512BWVL-NEXT: vmovq %xmm0, %rax
+; AVX512BWVL-NEXT: vmovd %xmm0, %eax
; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq
%1 = and <16 x i64> %a0, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>
diff --git a/llvm/test/CodeGen/X86/vector-reduce-add-zext.ll b/llvm/test/CodeGen/X86/vector-reduce-add-zext.ll
index f888d4049c70a..b28d3b4f81b6e 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-add-zext.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-add-zext.ll
@@ -153,7 +153,7 @@ define i64 @test_v4i64_v4i16(<4 x i16> %a0) nounwind {
; X64-SSE4-NEXT: paddq %xmm1, %xmm0
; X64-SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-SSE4-NEXT: paddq %xmm0, %xmm1
-; X64-SSE4-NEXT: movq %xmm1, %rax
+; X64-SSE4-NEXT: movd %xmm1, %eax
; X64-SSE4-NEXT: retq
;
; X86-AVX1-LABEL: test_v4i64_v4i16:
@@ -176,7 +176,7 @@ define i64 @test_v4i64_v4i16(<4 x i16> %a0) nounwind {
; X64-AVX1-NEXT: vpaddq %xmm0, %xmm1, %xmm0
; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; X64-AVX1-NEXT: vmovq %xmm0, %rax
+; X64-AVX1-NEXT: vmovd %xmm0, %eax
; X64-AVX1-NEXT: retq
;
; X86-AVX2-LABEL: test_v4i64_v4i16:
@@ -230,7 +230,7 @@ define i64 @test_v8i64_v8i8(<8 x i8> %a0) nounwind {
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: pxor %xmm1, %xmm1
; X64-SSE-NEXT: psadbw %xmm0, %xmm1
-; X64-SSE-NEXT: movq %xmm1, %rax
+; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: retq
;
; X86-SSE4-LABEL: test_v8i64_v8i8:
@@ -253,7 +253,7 @@ define i64 @test_v8i64_v8i8(<8 x i8> %a0) nounwind {
; X64-AVX1: # %bb.0:
; X64-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; X64-AVX1-NEXT: vmovq %xmm0, %rax
+; X64-AVX1-NEXT: vmovd %xmm0, %eax
; X64-AVX1-NEXT: retq
;
; X86-AVX2-LABEL: test_v8i64_v8i8:
@@ -268,14 +268,14 @@ define i64 @test_v8i64_v8i8(<8 x i8> %a0) nounwind {
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; X64-AVX2-NEXT: vmovq %xmm0, %rax
+; X64-AVX2-NEXT: vmovd %xmm0, %eax
; X64-AVX2-NEXT: retq
;
; AVX512-LABEL: test_v8i64_v8i8:
; AVX512: # %bb.0:
; AVX512-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vmovq %xmm0, %rax
+; AVX512-NEXT: vmovd %xmm0, %eax
; AVX512-NEXT: retq
%1 = zext <8 x i8> %a0 to <8 x i64>
%2 = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %1)
@@ -300,7 +300,7 @@ define i64 @test_v16i64_v16i8(<16 x i8> %a0) nounwind {
; X64-SSE-NEXT: psadbw %xmm0, %xmm1
; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
; X64-SSE-NEXT: paddq %xmm1, %xmm0
-; X64-SSE-NEXT: movq %xmm0, %rax
+; X64-SSE-NEXT: movd %xmm0, %eax
; X64-SSE-NEXT: retq
;
; X86-SSE4-LABEL: test_v16i64_v16i8:
@@ -329,7 +329,7 @@ define i64 @test_v16i64_v16i8(<16 x i8> %a0) nounwind {
; X64-AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; X64-AVX1-NEXT: vmovq %xmm0, %rax
+; X64-AVX1-NEXT: vmovd %xmm0, %eax
; X64-AVX1-NEXT: retq
;
; X86-AVX2-LABEL: test_v16i64_v16i8:
@@ -348,7 +348,7 @@ define i64 @test_v16i64_v16i8(<16 x i8> %a0) nounwind {
; X64-AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; X64-AVX2-NEXT: vmovq %xmm0, %rax
+; X64-AVX2-NEXT: vmovd %xmm0, %eax
; X64-AVX2-NEXT: retq
;
; AVX512-LABEL: test_v16i64_v16i8:
@@ -357,7 +357,7 @@ define i64 @test_v16i64_v16i8(<16 x i8> %a0) nounwind {
; AVX512-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; AVX512-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vmovq %xmm0, %rax
+; AVX512-NEXT: vmovd %xmm0, %eax
; AVX512-NEXT: retq
%1 = zext <16 x i8> %a0 to <16 x i64>
%2 = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %1)
diff --git a/llvm/test/CodeGen/X86/vector-reduce-ctpop.ll b/llvm/test/CodeGen/X86/vector-reduce-ctpop.ll
index e936f1e4faf21..15010a5190157 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-ctpop.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-ctpop.ll
@@ -63,7 +63,7 @@ define i64 @reduce_ctpop_v2i64(<2 x i64> %a0) nounwind {
; X64-SSE2-NEXT: psadbw %xmm1, %xmm0
; X64-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-SSE2-NEXT: paddq %xmm0, %xmm1
-; X64-SSE2-NEXT: movq %xmm1, %rax
+; X64-SSE2-NEXT: movd %xmm1, %eax
; X64-SSE2-NEXT: retq
;
; X86-SSE4-LABEL: reduce_ctpop_v2i64:
@@ -102,7 +102,7 @@ define i64 @reduce_ctpop_v2i64(<2 x i64> %a0) nounwind {
; X64-SSE4-NEXT: psadbw %xmm3, %xmm0
; X64-SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-SSE4-NEXT: paddq %xmm0, %xmm1
-; X64-SSE4-NEXT: movq %xmm1, %rax
+; X64-SSE4-NEXT: movd %xmm1, %eax
; X64-SSE4-NEXT: retq
;
; X86-AVX1-LABEL: reduce_ctpop_v2i64:
@@ -137,7 +137,7 @@ define i64 @reduce_ctpop_v2i64(<2 x i64> %a0) nounwind {
; X64-AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; X64-AVX1-NEXT: vmovq %xmm0, %rax
+; X64-AVX1-NEXT: vmovd %xmm0, %eax
; X64-AVX1-NEXT: retq
;
; X86-AVX2-LABEL: reduce_ctpop_v2i64:
@@ -172,7 +172,7 @@ define i64 @reduce_ctpop_v2i64(<2 x i64> %a0) nounwind {
; X64-AVX2-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; X64-AVX2-NEXT: vmovq %xmm0, %rax
+; X64-AVX2-NEXT: vmovd %xmm0, %eax
; X64-AVX2-NEXT: retq
;
; AVX512VL-LABEL: reduce_ctpop_v2i64:
@@ -189,7 +189,7 @@ define i64 @reduce_ctpop_v2i64(<2 x i64> %a0) nounwind {
; AVX512VL-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; AVX512VL-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; AVX512VL-NEXT: vmovq %xmm0, %rax
+; AVX512VL-NEXT: vmovd %xmm0, %eax
; AVX512VL-NEXT: retq
;
; AVX512VPOPCNT-LABEL: reduce_ctpop_v2i64:
@@ -197,7 +197,7 @@ define i64 @reduce_ctpop_v2i64(<2 x i64> %a0) nounwind {
; AVX512VPOPCNT-NEXT: vpopcntq %xmm0, %xmm0
; AVX512VPOPCNT-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; AVX512VPOPCNT-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; AVX512VPOPCNT-NEXT: vmovq %xmm0, %rax
+; AVX512VPOPCNT-NEXT: vmovd %xmm0, %eax
; AVX512VPOPCNT-NEXT: retq
%p0 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a0)
%r0 = tail call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %p0)
@@ -768,7 +768,7 @@ define i64 @reduce_ctpop_v4i64(<4 x i64> %a0) nounwind {
; X64-SSE2-NEXT: psadbw %xmm2, %xmm0
; X64-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-SSE2-NEXT: paddq %xmm0, %xmm1
-; X64-SSE2-NEXT: movq %xmm1, %rax
+; X64-SSE2-NEXT: movd %xmm1, %eax
; X64-SSE2-NEXT: retq
;
; X86-SSE4-LABEL: reduce_ctpop_v4i64:
@@ -827,7 +827,7 @@ define i64 @reduce_ctpop_v4i64(<4 x i64> %a0) nounwind {
; X64-SSE4-NEXT: psadbw %xmm4, %xmm0
; X64-SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-SSE4-NEXT: paddq %xmm0, %xmm1
-; X64-SSE4-NEXT: movq %xmm1, %rax
+; X64-SSE4-NEXT: movd %xmm1, %eax
; X64-SSE4-NEXT: retq
;
; X86-AVX1-LABEL: reduce_ctpop_v4i64:
@@ -879,7 +879,7 @@ define i64 @reduce_ctpop_v4i64(<4 x i64> %a0) nounwind {
; X64-AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; X64-AVX1-NEXT: vmovq %xmm0, %rax
+; X64-AVX1-NEXT: vmovd %xmm0, %eax
; X64-AVX1-NEXT: vzeroupper
; X64-AVX1-NEXT: retq
;
@@ -942,7 +942,7 @@ define i64 @reduce_ctpop_v4i64(<4 x i64> %a0) nounwind {
; AVX512VL-NEXT: vpmovqb %ymm0, %xmm0
; AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VL-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX512VL-NEXT: vmovq %xmm0, %rax
+; AVX512VL-NEXT: vmovd %xmm0, %eax
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
;
@@ -952,7 +952,7 @@ define i64 @reduce_ctpop_v4i64(<4 x i64> %a0) nounwind {
; AVX512VPOPCNT-NEXT: vpmovqb %ymm0, %xmm0
; AVX512VPOPCNT-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VPOPCNT-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX512VPOPCNT-NEXT: vmovq %xmm0, %rax
+; AVX512VPOPCNT-NEXT: vmovd %xmm0, %eax
; AVX512VPOPCNT-NEXT: vzeroupper
; AVX512VPOPCNT-NEXT: retq
%p0 = tail call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %a0)
@@ -1373,7 +1373,7 @@ define i64 @reduce_ctpop_v8i64(<8 x i64> %a0) nounwind {
; X64-SSE2-NEXT: psadbw %xmm3, %xmm0
; X64-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-SSE2-NEXT: paddq %xmm0, %xmm1
-; X64-SSE2-NEXT: movq %xmm1, %rax
+; X64-SSE2-NEXT: movd %xmm1, %eax
; X64-SSE2-NEXT: retq
;
; X86-SSE4-LABEL: reduce_ctpop_v8i64:
@@ -1479,7 +1479,7 @@ define i64 @reduce_ctpop_v8i64(<8 x i64> %a0) nounwind {
; X64-SSE4-NEXT: psadbw %xmm4, %xmm0
; X64-SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-SSE4-NEXT: paddq %xmm0, %xmm1
-; X64-SSE4-NEXT: movq %xmm1, %rax
+; X64-SSE4-NEXT: movd %xmm1, %eax
; X64-SSE4-NEXT: retq
;
; X86-AVX1-LABEL: reduce_ctpop_v8i64:
@@ -1561,7 +1561,7 @@ define i64 @reduce_ctpop_v8i64(<8 x i64> %a0) nounwind {
; X64-AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; X64-AVX1-NEXT: vmovq %xmm0, %rax
+; X64-AVX1-NEXT: vmovd %xmm0, %eax
; X64-AVX1-NEXT: vzeroupper
; X64-AVX1-NEXT: retq
;
@@ -1638,7 +1638,7 @@ define i64 @reduce_ctpop_v8i64(<8 x i64> %a0) nounwind {
; AVX512VL-NEXT: vpmovqb %zmm0, %xmm0
; AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VL-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX512VL-NEXT: vmovq %xmm0, %rax
+; AVX512VL-NEXT: vmovd %xmm0, %eax
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
;
@@ -1648,7 +1648,7 @@ define i64 @reduce_ctpop_v8i64(<8 x i64> %a0) nounwind {
; AVX512VPOPCNT-NEXT: vpmovqb %zmm0, %xmm0
; AVX512VPOPCNT-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VPOPCNT-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
-; AVX512VPOPCNT-NEXT: vmovq %xmm0, %rax
+; AVX512VPOPCNT-NEXT: vmovd %xmm0, %eax
; AVX512VPOPCNT-NEXT: vzeroupper
; AVX512VPOPCNT-NEXT: retq
%p0 = tail call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %a0)
@@ -2400,7 +2400,7 @@ define i64 @reduce_ctpop_v16i64(<16 x i64> %a0) nounwind {
; X64-SSE2-NEXT: psadbw %xmm4, %xmm0
; X64-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-SSE2-NEXT: paddq %xmm0, %xmm1
-; X64-SSE2-NEXT: movq %xmm1, %rax
+; X64-SSE2-NEXT: movd %xmm1, %eax
; X64-SSE2-NEXT: retq
;
; X86-SSE4-LABEL: reduce_ctpop_v16i64:
@@ -2593,7 +2593,7 @@ define i64 @reduce_ctpop_v16i64(<16 x i64> %a0) nounwind {
; X64-SSE4-NEXT: psadbw %xmm8, %xmm0
; X64-SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-SSE4-NEXT: paddq %xmm0, %xmm1
-; X64-SSE4-NEXT: movq %xmm1, %rax
+; X64-SSE4-NEXT: movd %xmm1, %eax
; X64-SSE4-NEXT: retq
;
; X86-AVX1-LABEL: reduce_ctpop_v16i64:
@@ -2745,7 +2745,7 @@ define i64 @reduce_ctpop_v16i64(<16 x i64> %a0) nounwind {
; X64-AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; X64-AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; X64-AVX1-NEXT: vmovq %xmm0, %rax
+; X64-AVX1-NEXT: vmovd %xmm0, %eax
; X64-AVX1-NEXT: vzeroupper
; X64-AVX1-NEXT: retq
;
@@ -2868,7 +2868,7 @@ define i64 @reduce_ctpop_v16i64(<16 x i64> %a0) nounwind {
; AVX512VL-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; AVX512VL-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; AVX512VL-NEXT: vmovq %xmm0, %rax
+; AVX512VL-NEXT: vmovd %xmm0, %eax
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
;
@@ -2883,7 +2883,7 @@ define i64 @reduce_ctpop_v16i64(<16 x i64> %a0) nounwind {
; AVX512VPOPCNT-NEXT: vpsadbw %xmm1, %xmm0, %xmm0
; AVX512VPOPCNT-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; AVX512VPOPCNT-NEXT: vpaddq %xmm1, %xmm0, %xmm0
-; AVX512VPOPCNT-NEXT: vmovq %xmm0, %rax
+; AVX512VPOPCNT-NEXT: vmovd %xmm0, %eax
; AVX512VPOPCNT-NEXT: vzeroupper
; AVX512VPOPCNT-NEXT: retq
%p0 = tail call <16 x i64> @llvm.ctpop.v16i64(<16 x i64> %a0)
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