[llvm] [AArch64][DAG] Port adde and sube combine to AArch64 (PR #202227)

[Benjamin Maxwell via llvm-commits]

================
@@ -23002,6 +23002,43 @@ static SDValue foldADCToCINC(SDNode *N, SelectionDAG &DAG) {
   return DAG.getNode(AArch64ISD::CSINC, DL, VT, LHS, LHS, CC, Cond);
 }
 
+static SDValue performAddSubCarryCombine(SDNode *N, SelectionDAG &DAG) {
+  SDValue RHS = N->getOperand(1);
+  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
+    int64_t Imm = C->getSExtValue();
+
+    // -1 is exempt because 0 gets the zero reg
----------------
MacDue wrote:

nit: Can you rephrase this comment to be a little more clear:

```suggestion
    // Note: We always allow -1 as it maps to 0 (which can use wzr/xzr).
```

https://github.com/llvm/llvm-project/pull/202227