[llvm] [AArch64][DAG] Port adde and sube combine to AArch64 (PR #202227)

[Ricardo Jesus via llvm-commits]

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@@ -23002,6 +23002,43 @@ static SDValue foldADCToCINC(SDNode *N, SelectionDAG &DAG) {
   return DAG.getNode(AArch64ISD::CSINC, DL, VT, LHS, LHS, CC, Cond);
 }
 
+static SDValue performAddSubCarryCombine(SDNode *N, SelectionDAG &DAG) {
+  SDValue RHS = N->getOperand(1);
+  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
+    int64_t Imm = C->getSExtValue();
+
+    // -1 is exempt because 0 gets the zero reg
+    if (Imm == -1 || (Imm < 0 && C->hasOneUse())) {
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rj-jesus wrote:

Is there value in gating the transformation based on the cost of materialising the immediate, rather than its sign?

https://github.com/llvm/llvm-project/pull/202227