[llvm] [RISCV] Add HasStdExtH to hfence.gvma and hfence.vvma aliases (PR #207061)

[Mark Zhuang via llvm-commits]

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@@ -14,13 +14,19 @@ sfence.w.inval 0x10 # CHECK: :[[@LINE]]:1: error: invalid instruction
 
 sfence.inval.ir 0x10 # CHECK: :[[@LINE]]:1: error: invalid instruction
 
-hfence.vvma zero, a1, a2 # CHECK: :[[@LINE]]:1: error: invalid instruction
+hfence.vvma zero, a1, a2
+# CHECK: :[[#@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
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zqb-all wrote:

`hfence.vvma zero, a1, a2` has 3 operands but every `hfence.vvma` form takes at most 2, so it misses two ways at once: bad operand and missing H. The shared matcher drops any candidate that misses in more than one way, so "requires H" gets thrown out. H only reports cleanly when the arity is right.

https://github.com/llvm/llvm-project/pull/207061