[llvm] [AMDGPU] SDAG and GISel support for folding fabs into fp_round source modifiers (PR #204861)
Chinmay Deshpande via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 30 08:02:56 PDT 2026
https://github.com/chinmaydd updated https://github.com/llvm/llvm-project/pull/204861
>From ef253b945074d7dc4de9ae28177f9d02246e15d9 Mon Sep 17 00:00:00 2001
From: Chinmay Deshpande <chdeshpa at amd.com>
Date: Thu, 18 Jun 2026 15:15:09 -0400
Subject: [PATCH 1/6] [AMDGPU] SDAG and GISel support for folding fabs into
source modifiers for fp_round
---
llvm/lib/Target/AMDGPU/AMDGPUCombine.td | 14 +-
.../Target/AMDGPU/AMDGPUCombinerHelper.cpp | 23 +
llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h | 3 +
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 11 +
llvm/test/CodeGen/AMDGPU/fptrunc.ll | 792 ++++++------------
5 files changed, 297 insertions(+), 546 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
index 620cefceda189..0c348bb647c0c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
@@ -115,6 +115,14 @@ def foldable_fneg : GICombineRule<
[{ return Helper.matchFoldableFneg(*${ffn}, ${matchinfo}); }]),
(apply [{ Helper.applyFoldableFneg(*${ffn}, ${matchinfo}); }])>;
+// fabs (fptrunc x) -> fptrunc (fabs x)
+def fold_fabs_fptrunc : GICombineRule<
+ (defs root:$dst),
+ (match (G_FABS $dst, $round):$fabs,
+ (G_FPTRUNC $round, $src):$fptrunc,
+ [{ return Helper.matchFoldFAbsFptrunc(*${fabs}, *${fptrunc}); }]),
+ (apply [{ Helper.applyFoldFAbsFptrunc(*${fabs}, *${fptrunc}); }])>;
+
// Detects s_mul_u64 instructions whose higher bits are zero/sign extended.
def smulu64 : GICombineRule<
(defs root:$smul, unsigned_matchinfo:$matchinfo),
@@ -237,7 +245,8 @@ def gfx8_combines : GICombineGroup<[expand_promoted_fmed3]>;
def AMDGPUPreLegalizerCombiner: GICombiner<
"AMDGPUPreLegalizerCombinerImpl",
[all_combines, combine_fmul_with_select_to_fldexp, clamp_i64_to_i16,
- foldable_fneg, combine_shuffle_vector, combine_shuffle_vector_to_build_vector,
+ foldable_fneg, fold_fabs_fptrunc, combine_shuffle_vector,
+ combine_shuffle_vector_to_build_vector,
binop_s64_with_s32_mask_combines, combine_or_s64_s32]> {
let CombineAllMethodName = "tryCombineAllImpl";
}
@@ -246,7 +255,8 @@ def AMDGPUPostLegalizerCombiner: GICombiner<
"AMDGPUPostLegalizerCombinerImpl",
[all_combines, gfx6gfx7_combines, gfx8_combines, combine_fmul_with_select_to_fldexp,
uchar_to_float, cvt_f32_ubyteN, remove_fcanonicalize, foldable_fneg,
- rcp_sqrt_to_rsq, fdiv_by_sqrt_to_rsq_f16, sign_extension_in_reg, smulu64,
+ fold_fabs_fptrunc, rcp_sqrt_to_rsq, fdiv_by_sqrt_to_rsq_f16,
+ sign_extension_in_reg, smulu64,
binop_s64_with_s32_mask_combines, combine_or_s64_s32]> {
let CombineAllMethodName = "tryCombineAllImpl";
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
index 1a158b335321d..955c561f9052c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
@@ -10,6 +10,7 @@
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
+#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/Target/TargetMachine.h"
@@ -401,6 +402,28 @@ void AMDGPUCombinerHelper::applyFoldableFneg(MachineInstr &MI,
MI.eraseFromParent();
}
+bool AMDGPUCombinerHelper::matchFoldFAbsFptrunc(MachineInstr &Fabs,
+ MachineInstr &Fptrunc) const {
+ Register Round = Fptrunc.getOperand(0).getReg();
+ if (!MRI.hasOneNonDBGUse(Round))
+ return false;
+
+ LLT SrcTy = MRI.getType(Fptrunc.getOperand(1).getReg());
+ return isLegalOrBeforeLegalizer({TargetOpcode::G_FABS, {SrcTy}});
+}
+
+void AMDGPUCombinerHelper::applyFoldFAbsFptrunc(MachineInstr &Fabs,
+ MachineInstr &Fptrunc) const {
+ // fabs (fptrunc x) -> fptrunc (fabs x)
+ Register Dst = Fabs.getOperand(0).getReg();
+ Register Src = Fptrunc.getOperand(1).getReg();
+ Builder.setInstrAndDebugLoc(Fabs);
+ Register Abs =
+ Builder.buildFAbs(MRI.getType(Src), Src, Fabs.getFlags()).getReg(0);
+ Builder.buildFPTrunc(Dst, Abs, Fptrunc.getFlags());
+ Fabs.eraseFromParent();
+}
+
// TODO: Should return converted value / extension source and avoid introducing
// intermediate fptruncs in the apply function.
static bool isFPExtFromF16OrConst(const MachineRegisterInfo &MRI,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h b/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h
index 243474a57cfab..ffbb3a4e69305 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h
@@ -35,6 +35,9 @@ class AMDGPUCombinerHelper : public CombinerHelper {
bool matchFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo) const;
void applyFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo) const;
+ bool matchFoldFAbsFptrunc(MachineInstr &Fabs, MachineInstr &Fptrunc) const;
+ void applyFoldFAbsFptrunc(MachineInstr &Fabs, MachineInstr &Fptrunc) const;
+
bool matchExpandPromotedF16FMed3(MachineInstr &MI, Register Src0,
Register Src1, Register Src2) const;
void applyExpandPromotedF16FMed3(MachineInstr &MI, Register Src0,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 336700afbcbbb..9386750190f42 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -5545,6 +5545,17 @@ SDValue AMDGPUTargetLowering::performFAbsCombine(SDNode *N,
DAG.getConstant(0x7fff, SL, SrcVT));
return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFAbs);
}
+ case ISD::FP_ROUND: {
+ SDValue CvtSrc = N0.getOperand(0);
+ EVT SrcVT = CvtSrc.getValueType();
+ if (!isOperationLegal(ISD::FABS, SrcVT))
+ return SDValue();
+
+ SDLoc SL(N);
+ SDValue Abs = DAG.getNode(ISD::FABS, SL, SrcVT, CvtSrc);
+ return DAG.getNode(ISD::FP_ROUND, SL, N->getValueType(0), Abs,
+ N0.getOperand(1));
+ }
default:
return SDValue();
}
diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.ll
index f54f1b9ab1258..87a98f10de934 100644
--- a/llvm/test/CodeGen/AMDGPU/fptrunc.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptrunc.ll
@@ -1691,52 +1691,43 @@ define float @fabs_fptrunc_f64_to_f32(double %x) {
; SI-LABEL: fabs_fptrunc_f64_to_f32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; SI-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; SI-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: fabs_fptrunc_f64_to_f32:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SDAG-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; VI-SDAG-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; VI-SDAG-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: fabs_fptrunc_f64_to_f32:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; VI-GISEL-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; VI-GISEL-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: fabs_fptrunc_f64_to_f32:
; GFX10-SDAG: ; %bb.0:
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; GFX10-SDAG-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX10-SDAG-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: fabs_fptrunc_f64_to_f32:
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX10-GISEL-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: fabs_fptrunc_f64_to_f32:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX11-SDAG-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: fabs_fptrunc_f64_to_f32:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX11-GISEL-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
%t = fptrunc double %x to float
%a = call float @llvm.fabs.f32(float %t)
@@ -1747,52 +1738,43 @@ define float @fneg_fabs_fptrunc_f64_to_f32(double %x) {
; SI-LABEL: fneg_fabs_fptrunc_f64_to_f32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; SI-NEXT: v_or_b32_e32 v0, 0x80000000, v0
+; SI-NEXT: v_cvt_f32_f64_e64 v0, -|v[0:1]|
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: fneg_fabs_fptrunc_f64_to_f32:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SDAG-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; VI-SDAG-NEXT: v_or_b32_e32 v0, 0x80000000, v0
+; VI-SDAG-NEXT: v_cvt_f32_f64_e64 v0, -|v[0:1]|
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: fneg_fabs_fptrunc_f64_to_f32:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; VI-GISEL-NEXT: v_or_b32_e32 v0, 0x80000000, v0
+; VI-GISEL-NEXT: v_cvt_f32_f64_e64 v0, -|v[0:1]|
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: fneg_fabs_fptrunc_f64_to_f32:
; GFX10-SDAG: ; %bb.0:
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; GFX10-SDAG-NEXT: v_or_b32_e32 v0, 0x80000000, v0
+; GFX10-SDAG-NEXT: v_cvt_f32_f64_e64 v0, -|v[0:1]|
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: fneg_fabs_fptrunc_f64_to_f32:
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; GFX10-GISEL-NEXT: v_or_b32_e32 v0, 0x80000000, v0
+; GFX10-GISEL-NEXT: v_cvt_f32_f64_e64 v0, -|v[0:1]|
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: fneg_fabs_fptrunc_f64_to_f32:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_or_b32_e32 v0, 0x80000000, v0
+; GFX11-SDAG-NEXT: v_cvt_f32_f64_e64 v0, -|v[0:1]|
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: fneg_fabs_fptrunc_f64_to_f32:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_or_b32_e32 v0, 0x80000000, v0
+; GFX11-GISEL-NEXT: v_cvt_f32_f64_e64 v0, -|v[0:1]|
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
%t = fptrunc double %x to float
%a = call float @llvm.fabs.f32(float %t)
@@ -1805,84 +1787,67 @@ define half @fabs_fptrunc_f32_to_f16(float %x) {
; SI-LABEL: fabs_fptrunc_f32_to_f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: v_and_b32_e32 v0, 0x7fff, v0
+; SI-NEXT: v_cvt_f16_f32_e64 v0, |v0|
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: fabs_fptrunc_f32_to_f16:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
-; VI-SDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
+; VI-SDAG-NEXT: v_cvt_f16_f32_e64 v0, |v0|
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: fabs_fptrunc_f32_to_f16:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
+; VI-GISEL-NEXT: v_cvt_f16_f32_e64 v0, |v0|
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: fabs_fptrunc_f32_to_f16:
; GFX10-SDAG: ; %bb.0:
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX10-SDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
+; GFX10-SDAG-NEXT: v_cvt_f16_f32_e64 v0, |v0|
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: fabs_fptrunc_f32_to_f16:
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
+; GFX10-GISEL-NEXT: v_cvt_f16_f32_e64 v0, |v0|
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SAFE-SDAG-LABEL: fabs_fptrunc_f32_to_f16:
; GFX11-SAFE-SDAG: ; %bb.0:
; GFX11-SAFE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-SDAG-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-SDAG-NEXT: v_and_b16 v0.l, 0x7fff, v0.l
+; GFX11-SAFE-SDAG-NEXT: v_cvt_f16_f32_e64 v0.l, |v0|
; GFX11-SAFE-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SAFE-GISEL-LABEL: fabs_fptrunc_f32_to_f16:
; GFX11-SAFE-GISEL: ; %bb.0:
; GFX11-SAFE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-GISEL-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-GISEL-NEXT: v_and_b16 v0.l, 0x7fff, v0.l
+; GFX11-SAFE-GISEL-NEXT: v_cvt_f16_f32_e64 v0.l, |v0|
; GFX11-SAFE-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-UNSAFE-SDAG-TRUE16-LABEL: fabs_fptrunc_f32_to_f16:
; GFX11-UNSAFE-SDAG-TRUE16: ; %bb.0:
; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v0.l
+; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e64 v0.l, |v0|
; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-UNSAFE-SDAG-FAKE16-LABEL: fabs_fptrunc_f32_to_f16:
; GFX11-UNSAFE-SDAG-FAKE16: ; %bb.0:
; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0x7fff, v0
+; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cvt_f16_f32_e64 v0, |v0|
; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-UNSAFE-GISEL-TRUE16-LABEL: fabs_fptrunc_f32_to_f16:
; GFX11-UNSAFE-GISEL-TRUE16: ; %bb.0:
; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v0.l
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e64 v0.l, |v0|
; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-UNSAFE-GISEL-FAKE16-LABEL: fabs_fptrunc_f32_to_f16:
; GFX11-UNSAFE-GISEL-FAKE16: ; %bb.0:
; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0x7fff, v0
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_cvt_f16_f32_e64 v0, |v0|
; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%t = fptrunc float %x to half
%a = call half @llvm.fabs.f16(half %t)
@@ -1893,84 +1858,67 @@ define half @fneg_fabs_fptrunc_f32_to_f16(float %x) {
; SI-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: v_or_b32_e32 v0, 0xffff8000, v0
+; SI-NEXT: v_cvt_f16_f32_e64 v0, -|v0|
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
-; VI-SDAG-NEXT: v_or_b32_e32 v0, 0x8000, v0
+; VI-SDAG-NEXT: v_cvt_f16_f32_e64 v0, -|v0|
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_or_b32_e32 v0, 0x8000, v0
+; VI-GISEL-NEXT: v_cvt_f16_f32_e64 v0, -|v0|
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; GFX10-SDAG: ; %bb.0:
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX10-SDAG-NEXT: v_or_b32_e32 v0, 0x8000, v0
+; GFX10-SDAG-NEXT: v_cvt_f16_f32_e64 v0, -|v0|
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX10-GISEL-NEXT: v_or_b32_e32 v0, 0x8000, v0
+; GFX10-GISEL-NEXT: v_cvt_f16_f32_e64 v0, -|v0|
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SAFE-SDAG-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; GFX11-SAFE-SDAG: ; %bb.0:
; GFX11-SAFE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-SDAG-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-SDAG-NEXT: v_or_b16 v0.l, 0x8000, v0.l
+; GFX11-SAFE-SDAG-NEXT: v_cvt_f16_f32_e64 v0.l, -|v0|
; GFX11-SAFE-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SAFE-GISEL-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; GFX11-SAFE-GISEL: ; %bb.0:
; GFX11-SAFE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-GISEL-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-GISEL-NEXT: v_or_b16 v0.l, 0x8000, v0.l
+; GFX11-SAFE-GISEL-NEXT: v_cvt_f16_f32_e64 v0.l, -|v0|
; GFX11-SAFE-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-UNSAFE-SDAG-TRUE16-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; GFX11-UNSAFE-SDAG-TRUE16: ; %bb.0:
; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_or_b16 v0.l, 0x8000, v0.l
+; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e64 v0.l, -|v0|
; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-UNSAFE-SDAG-FAKE16-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; GFX11-UNSAFE-SDAG-FAKE16: ; %bb.0:
; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, 0x8000, v0
+; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cvt_f16_f32_e64 v0, -|v0|
; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-UNSAFE-GISEL-TRUE16-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; GFX11-UNSAFE-GISEL-TRUE16: ; %bb.0:
; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_or_b16 v0.l, 0x8000, v0.l
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e64 v0.l, -|v0|
; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-UNSAFE-GISEL-FAKE16-LABEL: fneg_fabs_fptrunc_f32_to_f16:
; GFX11-UNSAFE-GISEL-FAKE16: ; %bb.0:
; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_or_b32_e32 v0, 0x8000, v0
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_cvt_f16_f32_e64 v0, -|v0|
; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%t = fptrunc float %x to half
%a = call half @llvm.fabs.f16(half %t)
@@ -1983,15 +1931,17 @@ define half @fabs_fptrunc_f64_to_f16(double %x) {
; SI-LABEL: fabs_fptrunc_f64_to_f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; SI-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v1
; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; SI-NEXT: v_and_b32_e32 v2, 0xffe, v2
-; SI-NEXT: v_bfe_u32 v1, v1, 20, 11
+; SI-NEXT: v_lshrrev_b32_e32 v1, 20, v1
+; SI-NEXT: s_movk_i32 s4, 0x3f1
; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_sub_i32_e32 v3, vcc, 0x3f1, v1
+; SI-NEXT: v_sub_i32_e32 v3, vcc, s4, v1
; SI-NEXT: v_or_b32_e32 v2, 0x1000, v0
; SI-NEXT: v_med3_i32 v3, v3, 0, 13
; SI-NEXT: v_lshrrev_b32_e32 v4, v3, v2
@@ -2022,60 +1972,58 @@ define half @fabs_fptrunc_f64_to_f16(double %x) {
; SI-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s4, v1
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; SI-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: fabs_fptrunc_f64_to_f16:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; VI-SDAG-NEXT: v_and_b32_e32 v2, 0x1ff, v1
; VI-SDAG-NEXT: v_or_b32_e32 v0, v2, v0
; VI-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-SDAG-NEXT: v_lshrrev_b32_e32 v2, 8, v1
; VI-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; VI-SDAG-NEXT: v_and_b32_e32 v2, 0xffe, v2
-; VI-SDAG-NEXT: v_bfe_u32 v3, v1, 20, 11
+; VI-SDAG-NEXT: v_lshrrev_b32_e32 v1, 20, v1
+; VI-SDAG-NEXT: s_movk_i32 s4, 0x3f1
; VI-SDAG-NEXT: v_or_b32_e32 v0, v2, v0
-; VI-SDAG-NEXT: v_sub_u32_e32 v4, vcc, 0x3f1, v3
+; VI-SDAG-NEXT: v_sub_u32_e32 v3, vcc, s4, v1
; VI-SDAG-NEXT: v_or_b32_e32 v2, 0x1000, v0
-; VI-SDAG-NEXT: v_med3_i32 v4, v4, 0, 13
-; VI-SDAG-NEXT: v_lshrrev_b32_e32 v5, v4, v2
-; VI-SDAG-NEXT: v_lshlrev_b32_e32 v4, v4, v5
-; VI-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, v4, v2
+; VI-SDAG-NEXT: v_med3_i32 v3, v3, 0, 13
+; VI-SDAG-NEXT: v_lshrrev_b32_e32 v4, v3, v2
+; VI-SDAG-NEXT: v_lshlrev_b32_e32 v3, v3, v4
+; VI-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, v3, v2
; VI-SDAG-NEXT: s_movk_i32 s4, 0xfc10
; VI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; VI-SDAG-NEXT: v_add_u32_e32 v3, vcc, s4, v3
-; VI-SDAG-NEXT: v_lshlrev_b32_e32 v4, 12, v3
-; VI-SDAG-NEXT: v_or_b32_e32 v2, v5, v2
-; VI-SDAG-NEXT: v_or_b32_e32 v4, v0, v4
-; VI-SDAG-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
-; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; VI-SDAG-NEXT: v_and_b32_e32 v4, 7, v2
-; VI-SDAG-NEXT: v_cmp_lt_i32_e32 vcc, 5, v4
-; VI-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; VI-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 3, v4
+; VI-SDAG-NEXT: v_add_u32_e32 v1, vcc, s4, v1
+; VI-SDAG-NEXT: v_lshlrev_b32_e32 v3, 12, v1
+; VI-SDAG-NEXT: v_or_b32_e32 v2, v4, v2
+; VI-SDAG-NEXT: v_or_b32_e32 v3, v0, v3
+; VI-SDAG-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
+; VI-SDAG-NEXT: v_and_b32_e32 v3, 7, v2
+; VI-SDAG-NEXT: v_cmp_lt_i32_e32 vcc, 5, v3
; VI-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
-; VI-SDAG-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 3, v3
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
+; VI-SDAG-NEXT: v_or_b32_e32 v3, v3, v4
; VI-SDAG-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; VI-SDAG-NEXT: v_add_u32_e32 v2, vcc, v2, v4
-; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0x7c00
-; VI-SDAG-NEXT: v_cmp_gt_i32_e32 vcc, 31, v3
-; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; VI-SDAG-NEXT: v_mov_b32_e32 v5, 0x7e00
+; VI-SDAG-NEXT: v_add_u32_e32 v2, vcc, v2, v3
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, 0x7c00
+; VI-SDAG-NEXT: v_cmp_gt_i32_e32 vcc, 31, v1
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0x7e00
; VI-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; VI-SDAG-NEXT: s_movk_i32 s4, 0x40f
-; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
-; VI-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, s4, v3
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
+; VI-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, s4, v1
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x8000
-; VI-SDAG-NEXT: v_and_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
-; VI-SDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: fabs_fptrunc_f64_to_f16:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; VI-GISEL-NEXT: v_bfe_u32 v2, v1, 20, 11
; VI-GISEL-NEXT: v_and_b32_e32 v4, 0x1ff, v1
; VI-GISEL-NEXT: v_add_u32_e32 v2, vcc, 0xfffffc10, v2
@@ -2117,53 +2065,51 @@ define half @fabs_fptrunc_f64_to_f16(double %x) {
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; VI-GISEL-NEXT: v_and_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
-; VI-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: fabs_fptrunc_f64_to_f16:
; GFX10-SDAG: ; %bb.0:
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; GFX10-SDAG-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; GFX10-SDAG-NEXT: v_bfe_u32 v3, v1, 20, 11
-; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v1, 20, v1
; GFX10-SDAG-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX10-SDAG-NEXT: v_sub_nc_u32_e32 v4, 0x3f1, v3
-; GFX10-SDAG-NEXT: v_add_nc_u32_e32 v3, 0xfffffc10, v3
+; GFX10-SDAG-NEXT: v_sub_nc_u32_e32 v3, 0x3f1, v1
+; GFX10-SDAG-NEXT: v_add_nc_u32_e32 v1, 0xfffffc10, v1
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10-SDAG-NEXT: v_and_or_b32 v0, 0xffe, v2, v0
-; GFX10-SDAG-NEXT: v_med3_i32 v2, v4, 0, 13
-; GFX10-SDAG-NEXT: v_or_b32_e32 v4, 0x1000, v0
-; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v5, v2, v4
-; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v2, v2, v5
-; GFX10-SDAG-NEXT: v_cmp_ne_u32_e32 vcc_lo, v2, v4
-; GFX10-SDAG-NEXT: v_lshl_or_b32 v4, v3, 12, v0
+; GFX10-SDAG-NEXT: v_med3_i32 v2, v3, 0, 13
+; GFX10-SDAG-NEXT: v_or_b32_e32 v3, 0x1000, v0
+; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v4, v2, v3
+; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v2, v2, v4
+; GFX10-SDAG-NEXT: v_cmp_ne_u32_e32 vcc_lo, v2, v3
+; GFX10-SDAG-NEXT: v_lshl_or_b32 v3, v1, 12, v0
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX10-SDAG-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v3
-; GFX10-SDAG-NEXT: v_or_b32_e32 v2, v5, v2
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
-; GFX10-SDAG-NEXT: v_and_b32_e32 v4, 7, v2
+; GFX10-SDAG-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
+; GFX10-SDAG-NEXT: v_or_b32_e32 v2, v4, v2
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX10-SDAG-NEXT: v_and_b32_e32 v3, 7, v2
; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; GFX10-SDAG-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v4
+; GFX10-SDAG-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v3
; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX10-SDAG-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX10-SDAG-NEXT: v_or_b32_e32 v4, v4, v5
-; GFX10-SDAG-NEXT: v_mov_b32_e32 v5, 0x7e00
-; GFX10-SDAG-NEXT: v_add_nc_u32_e32 v2, v2, v4
-; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v5, vcc_lo
-; GFX10-SDAG-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v3
+; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v3
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v1
+; GFX10-SDAG-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX10-SDAG-NEXT: v_add_nc_u32_e32 v2, v2, v3
+; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0x7e00
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, 0x7c00, v2, vcc_lo
-; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v3
+; GFX10-SDAG-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v3, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v1
; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX10-SDAG-NEXT: v_and_or_b32 v0, 0x8000, v1, v0
-; GFX10-SDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: fabs_fptrunc_f64_to_f16:
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
; GFX10-GISEL-NEXT: v_bfe_u32 v2, v1, 20, 11
; GFX10-GISEL-NEXT: v_lshrrev_b32_e32 v3, 8, v1
@@ -2198,310 +2144,104 @@ define half @fabs_fptrunc_f64_to_f16(double %x) {
; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v2
; GFX10-GISEL-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo
; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0x8000, v1, v0
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-SAFE-SDAG-LABEL: fabs_fptrunc_f64_to_f16:
-; GFX11-SAFE-SDAG: ; %bb.0:
-; GFX11-SAFE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-SDAG-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
-; GFX11-SAFE-SDAG-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; GFX11-SAFE-SDAG-NEXT: v_bfe_u32 v3, v1, 20, 11
-; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SAFE-SDAG-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-SAFE-SDAG-NEXT: v_sub_nc_u32_e32 v4, 0x3f1, v3
-; GFX11-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-SAFE-SDAG-NEXT: v_and_or_b32 v0, 0xffe, v2, v0
-; GFX11-SAFE-SDAG-NEXT: v_med3_i32 v2, v4, 0, 13
-; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-SDAG-NEXT: v_or_b32_e32 v4, 0x1000, v0
-; GFX11-SAFE-SDAG-NEXT: v_lshrrev_b32_e32 v5, v2, v4
-; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-SDAG-NEXT: v_lshlrev_b32_e32 v2, v2, v5
-; GFX11-SAFE-SDAG-NEXT: v_cmp_ne_u32_e32 vcc_lo, v2, v4
-; GFX11-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SAFE-SDAG-NEXT: v_or_b32_e32 v2, v5, v2
-; GFX11-SAFE-SDAG-NEXT: v_add_nc_u32_e32 v3, 0xfffffc10, v3
-; GFX11-SAFE-SDAG-NEXT: v_lshl_or_b32 v4, v3, 12, v0
-; GFX11-SAFE-SDAG-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v3
-; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
-; GFX11-SAFE-SDAG-NEXT: v_and_b32_e32 v4, 7, v2
-; GFX11-SAFE-SDAG-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-SAFE-SDAG-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v4
-; GFX11-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX11-SAFE-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v4
-; GFX11-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX11-SAFE-SDAG-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-SAFE-SDAG-NEXT: v_or_b32_e32 v4, v4, v5
-; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-SDAG-NEXT: v_dual_mov_b32 v5, 0x7e00 :: v_dual_add_nc_u32 v2, v2, v4
-; GFX11-SAFE-SDAG-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v5, vcc_lo
-; GFX11-SAFE-SDAG-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v3
-; GFX11-SAFE-SDAG-NEXT: v_mov_b16_e32 v4.h, 0
-; GFX11-SAFE-SDAG-NEXT: v_mov_b16_e32 v4.l, v1.h
-; GFX11-SAFE-SDAG-NEXT: v_cndmask_b32_e32 v2, 0x7c00, v2, vcc_lo
-; GFX11-SAFE-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v3
-; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX11-SAFE-SDAG-NEXT: v_and_or_b32 v0, 0x8000, v4, v0
-; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-SDAG-NEXT: v_and_b16 v0.l, 0x7fff, v0.l
-; GFX11-SAFE-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-SAFE-GISEL-LABEL: fabs_fptrunc_f64_to_f16:
-; GFX11-SAFE-GISEL: ; %bb.0:
-; GFX11-SAFE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-GISEL-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
-; GFX11-SAFE-GISEL-NEXT: v_bfe_u32 v2, v1, 20, 11
-; GFX11-SAFE-GISEL-NEXT: v_lshrrev_b32_e32 v3, 8, v1
-; GFX11-SAFE-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SAFE-GISEL-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-SAFE-GISEL-NEXT: v_add_nc_u32_e32 v2, 0xfffffc10, v2
-; GFX11-SAFE-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SAFE-GISEL-NEXT: v_sub_nc_u32_e32 v4, 1, v2
-; GFX11-SAFE-GISEL-NEXT: v_and_or_b32 v0, 0xffe, v3, v0
-; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SAFE-GISEL-NEXT: v_med3_i32 v3, v4, 0, 13
-; GFX11-SAFE-GISEL-NEXT: v_or_b32_e32 v4, 0x1000, v0
-; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-GISEL-NEXT: v_lshrrev_b32_e32 v5, v3, v4
-; GFX11-SAFE-GISEL-NEXT: v_lshlrev_b32_e32 v3, v3, v5
-; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-SAFE-GISEL-NEXT: v_cmp_ne_u32_e32 vcc_lo, v3, v4
-; GFX11-SAFE-GISEL-NEXT: v_lshl_or_b32 v4, v2, 12, v0
-; GFX11-SAFE-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; GFX11-SAFE-GISEL-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v2
-; GFX11-SAFE-GISEL-NEXT: v_or_b32_e32 v3, v5, v3
-; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-GISEL-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
-; GFX11-SAFE-GISEL-NEXT: v_and_b32_e32 v4, 7, v3
-; GFX11-SAFE-GISEL-NEXT: v_lshrrev_b32_e32 v3, 2, v3
-; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-SAFE-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v4
-; GFX11-SAFE-GISEL-NEXT: v_cmp_lt_i32_e64 s0, 5, v4
-; GFX11-SAFE-GISEL-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX11-SAFE-GISEL-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-SAFE-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
-; GFX11-SAFE-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-SAFE-GISEL-NEXT: v_add_nc_u32_e32 v3, v3, v4
-; GFX11-SAFE-GISEL-NEXT: v_cmp_lt_i32_e32 vcc_lo, 30, v2
-; GFX11-SAFE-GISEL-NEXT: v_lshl_or_b32 v0, v0, 9, 0x7c00
-; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-SAFE-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0x7c00, vcc_lo
-; GFX11-SAFE-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v2
-; GFX11-SAFE-GISEL-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo
-; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SAFE-GISEL-NEXT: v_and_or_b32 v0, 0x8000, v1, v0
-; GFX11-SAFE-GISEL-NEXT: v_and_b16 v0.l, 0x7fff, v0.l
-; GFX11-SAFE-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-UNSAFE-SDAG-TRUE16-LABEL: fabs_fptrunc_f64_to_f16:
-; GFX11-UNSAFE-SDAG-TRUE16: ; %bb.0:
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v1, 20, 11
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_sub_nc_u32_e32 v4, 0x3f1, v3
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_and_or_b32 v0, 0xffe, v2, v0
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_med3_i32 v2, v4, 0, 13
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_or_b32_e32 v4, 0x1000, v0
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v2, v4
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, v2, v5
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v2, v4
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_or_b32_e32 v2, v5, v2
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0xfffffc10, v3
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_lshl_or_b32 v4, v3, 12, v0
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v3
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_and_b32_e32 v4, 7, v2
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v4
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v4
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_or_b32_e32 v4, v4, v5
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_dual_mov_b32 v5, 0x7e00 :: v_dual_add_nc_u32 v2, v2, v4
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v5, vcc_lo
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v3
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.h, 0
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.h
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v2, 0x7c00, v2, vcc_lo
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v3
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_and_or_b32 v0, 0x8000, v4, v0
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v0.l
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-UNSAFE-SDAG-FAKE16-LABEL: fabs_fptrunc_f64_to_f16:
-; GFX11-UNSAFE-SDAG-FAKE16: ; %bb.0:
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 8, v1
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_bfe_u32 v3, v1, 20, 11
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_sub_nc_u32_e32 v4, 0x3f1, v3
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_and_or_b32 v0, 0xffe, v2, v0
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_med3_i32 v2, v4, 0, 13
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_or_b32_e32 v4, 0x1000, v0
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v2, v4
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v2, v5
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v2, v4
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_or_b32_e32 v2, v5, v2
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0xfffffc10, v3
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_lshl_or_b32 v4, v3, 12, v0
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v3
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_and_b32_e32 v4, 7, v2
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 2, v2
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v4
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v4
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_or_b32_e32 v4, v4, v5
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_dual_mov_b32 v5, 0x7e00 :: v_dual_add_nc_u32 v2, v2, v4
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v5, vcc_lo
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v3
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v2, 0x7c00, v2, vcc_lo
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v3
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_and_or_b32 v0, 0x8000, v1, v0
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-UNSAFE-GISEL-TRUE16-LABEL: fabs_fptrunc_f64_to_f16:
-; GFX11-UNSAFE-GISEL-TRUE16: ; %bb.0:
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_bfe_u32 v2, v1, 20, 11
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 8, v1
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0xfffffc10, v2
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_sub_nc_u32_e32 v4, 1, v2
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_and_or_b32 v0, 0xffe, v3, v0
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_med3_i32 v3, v4, 0, 13
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_or_b32_e32 v4, 0x1000, v0
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v4
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v3, v3, v5
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v3, v4
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_lshl_or_b32 v4, v2, 12, v0
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v2
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_or_b32_e32 v3, v5, v3
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_and_b32_e32 v4, 7, v3
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 2, v3
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v4
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cmp_lt_i32_e64 s0, 5, v4
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v4
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 30, v2
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_lshl_or_b32 v0, v0, 9, 0x7c00
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v3, v3, 0x7c00, vcc_lo
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v2
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_and_or_b32 v0, 0x8000, v1, v0
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v0.l
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-SDAG-LABEL: fabs_fptrunc_f64_to_f16:
+; GFX11-SDAG: ; %bb.0:
+; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
+; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v2, 8, v1
+; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v1, 20, v1
+; GFX11-SDAG-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_sub_nc_u32_e32 v3, 0x3f1, v1
+; GFX11-SDAG-NEXT: v_add_nc_u32_e32 v1, 0xfffffc10, v1
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-SDAG-NEXT: v_and_or_b32 v0, 0xffe, v2, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_med3_i32 v2, v3, 0, 13
+; GFX11-SDAG-NEXT: v_or_b32_e32 v3, 0x1000, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v4, v2, v3
+; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v2, v2, v4
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_cmp_ne_u32_e32 vcc_lo, v2, v3
+; GFX11-SDAG-NEXT: v_lshl_or_b32 v3, v1, 12, v0
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11-SDAG-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v1
+; GFX11-SDAG-NEXT: v_or_b32_e32 v2, v4, v2
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-SDAG-NEXT: v_and_b32_e32 v3, 7, v2
+; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v2, 2, v2
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v3
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v3
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX11-SDAG-NEXT: v_cmp_gt_i32_e32 vcc_lo, 31, v1
+; GFX11-SDAG-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_dual_mov_b32 v3, 0x7e00 :: v_dual_add_nc_u32 v2, v2, v3
+; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v2, 0x7c00, v2, vcc_lo
+; GFX11-SDAG-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v3, vcc_lo
+; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v1
+; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-UNSAFE-GISEL-FAKE16-LABEL: fabs_fptrunc_f64_to_f16:
-; GFX11-UNSAFE-GISEL-FAKE16: ; %bb.0:
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_bfe_u32 v2, v1, 20, 11
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 8, v1
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0xfffffc10, v2
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_sub_nc_u32_e32 v4, 1, v2
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_and_or_b32 v0, 0xffe, v3, v0
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_med3_i32 v3, v4, 0, 13
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_or_b32_e32 v4, 0x1000, v0
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v4
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_lshlrev_b32_e32 v3, v3, v5
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v3, v4
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_lshl_or_b32 v4, v2, 12, v0
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v2
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_or_b32_e32 v3, v5, v3
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_and_b32_e32 v4, 7, v3
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 2, v3
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v4
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_cmp_lt_i32_e64 s0, 5, v4
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v4
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 30, v2
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 9, 0x7c00
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v3, v3, 0x7c00, vcc_lo
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v2
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_and_or_b32 v0, 0x8000, v1, v0
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-GISEL-LABEL: fabs_fptrunc_f64_to_f16:
+; GFX11-GISEL: ; %bb.0:
+; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
+; GFX11-GISEL-NEXT: v_bfe_u32 v2, v1, 20, 11
+; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-GISEL-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v2, 0xfffffc10, v2
+; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-NEXT: v_sub_nc_u32_e32 v4, 1, v2
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_and_or_b32 v0, 0xffe, v3, v0
+; GFX11-GISEL-NEXT: v_med3_i32 v3, v4, 0, 13
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_or_b32_e32 v4, 0x1000, v0
+; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v5, v3, v4
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v3, v3, v5
+; GFX11-GISEL-NEXT: v_cmp_ne_u32_e32 vcc_lo, v3, v4
+; GFX11-GISEL-NEXT: v_lshl_or_b32 v4, v2, 12, v0
+; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX11-GISEL-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v2
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_or_b32_e32 v3, v5, v3
+; GFX11-GISEL-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_and_b32_e32 v4, 7, v3
+; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v3, 2, v3
+; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v4
+; GFX11-GISEL-NEXT: v_cmp_lt_i32_e64 s0, 5, v4
+; GFX11-GISEL-NEXT: s_or_b32 s0, vcc_lo, s0
+; GFX11-GISEL-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
+; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v3, v3, v4
+; GFX11-GISEL-NEXT: v_cmp_lt_i32_e32 vcc_lo, 30, v2
+; GFX11-GISEL-NEXT: v_lshl_or_b32 v0, v0, 9, 0x7c00
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0x7c00, vcc_lo
+; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v2
+; GFX11-GISEL-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo
+; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_and_or_b32 v0, 0x8000, v1, v0
+; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
%t = fptrunc double %x to half
%a = call half @llvm.fabs.f16(half %t)
ret half %a
@@ -2512,66 +2252,50 @@ define <2 x float> @fabs_fptrunc_v2f64_to_v2f32(<2 x double> %x) {
; SI-LABEL: fabs_fptrunc_v2f64_to_v2f32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; SI-NEXT: v_cvt_f32_f64_e32 v1, v[2:3]
-; SI-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; SI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; SI-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
+; SI-NEXT: v_cvt_f32_f64_e64 v1, |v[2:3]|
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: fabs_fptrunc_v2f64_to_v2f32:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SDAG-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; VI-SDAG-NEXT: v_cvt_f32_f64_e32 v1, v[2:3]
-; VI-SDAG-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; VI-SDAG-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; VI-SDAG-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
+; VI-SDAG-NEXT: v_cvt_f32_f64_e64 v1, |v[2:3]|
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: fabs_fptrunc_v2f64_to_v2f32:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v1, v[2:3]
-; VI-GISEL-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; VI-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; VI-GISEL-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
+; VI-GISEL-NEXT: v_cvt_f32_f64_e64 v1, |v[2:3]|
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: fabs_fptrunc_v2f64_to_v2f32:
; GFX10-SDAG: ; %bb.0:
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; GFX10-SDAG-NEXT: v_cvt_f32_f64_e32 v1, v[2:3]
-; GFX10-SDAG-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; GFX10-SDAG-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; GFX10-SDAG-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
+; GFX10-SDAG-NEXT: v_cvt_f32_f64_e64 v1, |v[2:3]|
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: fabs_fptrunc_v2f64_to_v2f32:
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v1, v[2:3]
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; GFX10-GISEL-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
+; GFX10-GISEL-NEXT: v_cvt_f32_f64_e64 v1, |v[2:3]|
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: fabs_fptrunc_v2f64_to_v2f32:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; GFX11-SDAG-NEXT: v_cvt_f32_f64_e32 v1, v[2:3]
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; GFX11-SDAG-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; GFX11-SDAG-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
+; GFX11-SDAG-NEXT: v_cvt_f32_f64_e64 v1, |v[2:3]|
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: fabs_fptrunc_v2f64_to_v2f32:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v1, v[2:3]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
-; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
+; GFX11-GISEL-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
+; GFX11-GISEL-NEXT: v_cvt_f32_f64_e64 v1, |v[2:3]|
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
%t = fptrunc <2 x double> %x to <2 x float>
%a = call <2 x float> @llvm.fabs.v2f32(<2 x float> %t)
@@ -2583,103 +2307,92 @@ define <2 x half> @fabs_fptrunc_v2f32_to_v2f16(<2 x float> %x) {
; SI-LABEL: fabs_fptrunc_v2f32_to_v2f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e64 v1, |v1|
+; SI-NEXT: v_cvt_f16_f32_e64 v0, |v0|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: fabs_fptrunc_v2f32_to_v2f16:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SDAG-NEXT: v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-; VI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_cvt_f16_f32_sdwa v1, |v1| dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; VI-SDAG-NEXT: v_cvt_f16_f32_e64 v0, |v0|
; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-SDAG-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: fabs_fptrunc_v2f32_to_v2f16:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; VI-GISEL-NEXT: v_cvt_f16_f32_e64 v0, |v0|
+; VI-GISEL-NEXT: v_cvt_f16_f32_sdwa v1, |v1| dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; VI-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: fabs_fptrunc_v2f32_to_v2f16:
; GFX10-SDAG: ; %bb.0:
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX10-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX10-SDAG-NEXT: v_cvt_f16_f32_e64 v1, |v1|
+; GFX10-SDAG-NEXT: v_cvt_f16_f32_e64 v0, |v0|
; GFX10-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX10-SDAG-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: fabs_fptrunc_v2f32_to_v2f16:
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX10-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX10-GISEL-NEXT: v_cvt_f16_f32_e64 v0, |v0|
+; GFX10-GISEL-NEXT: v_cvt_f16_f32_e64 v1, |v1|
; GFX10-GISEL-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SAFE-SDAG-LABEL: fabs_fptrunc_v2f32_to_v2f16:
; GFX11-SAFE-SDAG: ; %bb.0:
; GFX11-SAFE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-SDAG-NEXT: v_cvt_f16_f32_e32 v1.h, v1
-; GFX11-SAFE-SDAG-NEXT: v_cvt_f16_f32_e32 v1.l, v0
+; GFX11-SAFE-SDAG-NEXT: v_cvt_f16_f32_e64 v1.h, |v1|
+; GFX11-SAFE-SDAG-NEXT: v_cvt_f16_f32_e64 v1.l, |v0|
; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-SDAG-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v1
+; GFX11-SAFE-SDAG-NEXT: v_mov_b32_e32 v0, v1
; GFX11-SAFE-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SAFE-GISEL-LABEL: fabs_fptrunc_v2f32_to_v2f16:
; GFX11-SAFE-GISEL: ; %bb.0:
; GFX11-SAFE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SAFE-GISEL-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-SAFE-GISEL-NEXT: v_cvt_f16_f32_e32 v0.h, v1
-; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SAFE-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
+; GFX11-SAFE-GISEL-NEXT: v_cvt_f16_f32_e64 v0.l, |v0|
+; GFX11-SAFE-GISEL-NEXT: v_cvt_f16_f32_e64 v0.h, |v1|
; GFX11-SAFE-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-UNSAFE-SDAG-TRUE16-LABEL: fabs_fptrunc_v2f32_to_v2f16:
; GFX11-UNSAFE-SDAG-TRUE16: ; %bb.0:
; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.h, v1
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v0
+; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e64 v1.h, |v1|
+; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e64 v1.l, |v0|
; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v1
+; GFX11-UNSAFE-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v1
; GFX11-UNSAFE-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-UNSAFE-SDAG-FAKE16-LABEL: fabs_fptrunc_v2f32_to_v2f16:
; GFX11-UNSAFE-SDAG-FAKE16: ; %bb.0:
; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cvt_f16_f32_e64 v1, |v1|
+; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_cvt_f16_f32_e64 v0, |v0|
+; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX11-UNSAFE-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
; GFX11-UNSAFE-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-UNSAFE-GISEL-TRUE16-LABEL: fabs_fptrunc_v2f32_to_v2f16:
; GFX11-UNSAFE-GISEL-TRUE16: ; %bb.0:
; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e64 v0.l, |v0|
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e64 v0.h, |v1|
; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-UNSAFE-GISEL-FAKE16-LABEL: fabs_fptrunc_v2f32_to_v2f16:
; GFX11-UNSAFE-GISEL-FAKE16: ; %bb.0:
; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_cvt_f16_f32_e64 v0, |v0|
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_cvt_f16_f32_e64 v1, |v1|
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%t = fptrunc <2 x float> %x to <2 x half>
%a = call <2 x half> @llvm.fabs.v2f16(<2 x half> %t)
@@ -2766,52 +2479,52 @@ define float @fabs_fptrunc_f64_to_f32_used_by_fadd(double %x, float %y) {
; SI-LABEL: fabs_fptrunc_f64_to_f32_used_by_fadd:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; SI-NEXT: v_add_f32_e64 v0, |v0|, v2
+; SI-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
+; SI-NEXT: v_add_f32_e32 v0, v0, v2
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: fabs_fptrunc_f64_to_f32_used_by_fadd:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SDAG-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; VI-SDAG-NEXT: v_add_f32_e64 v0, |v0|, v2
+; VI-SDAG-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
+; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: fabs_fptrunc_f64_to_f32_used_by_fadd:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; VI-GISEL-NEXT: v_add_f32_e64 v0, |v0|, v2
+; VI-GISEL-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
+; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v2
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: fabs_fptrunc_f64_to_f32_used_by_fadd:
; GFX10-SDAG: ; %bb.0:
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; GFX10-SDAG-NEXT: v_add_f32_e64 v0, |v0|, v2
+; GFX10-SDAG-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
+; GFX10-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: fabs_fptrunc_f64_to_f32_used_by_fadd:
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
-; GFX10-GISEL-NEXT: v_add_f32_e64 v0, |v0|, v2
+; GFX10-GISEL-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
+; GFX10-GISEL-NEXT: v_add_f32_e32 v0, v0, v2
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: fabs_fptrunc_f64_to_f32_used_by_fadd:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX11-SDAG-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_add_f32_e64 v0, |v0|, v2
+; GFX11-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: fabs_fptrunc_f64_to_f32_used_by_fadd:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX11-GISEL-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_add_f32_e64 v0, |v0|, v2
+; GFX11-GISEL-NEXT: v_add_f32_e32 v0, v0, v2
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
%t = fptrunc double %x to float
%a = call float @llvm.fabs.f32(float %t)
@@ -2825,52 +2538,43 @@ define float @fabs_fptrunc_fneg_f64_to_f32(double %x) {
; SI-LABEL: fabs_fptrunc_fneg_f64_to_f32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cvt_f32_f64_e64 v0, -v[0:1]
-; SI-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; SI-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: fabs_fptrunc_fneg_f64_to_f32:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SDAG-NEXT: v_cvt_f32_f64_e64 v0, -v[0:1]
-; VI-SDAG-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; VI-SDAG-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: fabs_fptrunc_fneg_f64_to_f32:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-GISEL-NEXT: v_cvt_f32_f64_e64 v0, -v[0:1]
-; VI-GISEL-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; VI-GISEL-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-SDAG-LABEL: fabs_fptrunc_fneg_f64_to_f32:
; GFX10-SDAG: ; %bb.0:
; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-SDAG-NEXT: v_cvt_f32_f64_e64 v0, -v[0:1]
-; GFX10-SDAG-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX10-SDAG-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-GISEL-LABEL: fabs_fptrunc_fneg_f64_to_f32:
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-GISEL-NEXT: v_cvt_f32_f64_e64 v0, -v[0:1]
-; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX10-GISEL-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: fabs_fptrunc_fneg_f64_to_f32:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-SDAG-NEXT: v_cvt_f32_f64_e64 v0, -v[0:1]
-; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX11-SDAG-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: fabs_fptrunc_fneg_f64_to_f32:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_cvt_f32_f64_e64 v0, -v[0:1]
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX11-GISEL-NEXT: v_cvt_f32_f64_e64 v0, |v[0:1]|
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
%n = fneg double %x
%t = fptrunc double %n to float
>From 634df3e1f46eb115b3e462964f498193f57f5330 Mon Sep 17 00:00:00 2001
From: Chinmay Deshpande <chdeshpa at amd.com>
Date: Fri, 19 Jun 2026 13:00:07 -0400
Subject: [PATCH 2/6] Address comments
---
.../include/llvm/Target/GlobalISel/Combine.td | 19 +++++++++++++++
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 +++++++
llvm/lib/Target/AMDGPU/AMDGPUCombine.td | 13 ++---------
.../Target/AMDGPU/AMDGPUCombinerHelper.cpp | 23 -------------------
llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h | 3 ---
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 11 ---------
6 files changed, 29 insertions(+), 48 deletions(-)
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index 1b0602af68367..623a7d48d9c82 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -1052,6 +1052,24 @@ def fabs_fneg_fold: GICombineRule <
(G_FABS $dst, $tmp)),
(apply (G_FABS $dst, $x))>;
+// Fold (fabs (fptrunc x)) -> (fptrunc (fabs x)).
+def fabs_fptrunc_fold: GICombineRule <
+ (defs root:$dst),
+ (match (G_FPTRUNC $round, $src):$fptrunc,
+ (G_FABS $dst, $round):$fabs,
+ [{ return MRI.hasOneNonDBGUse(${round}.getReg()); }]),
+ (apply [{
+ Register Src = ${src}.getReg();
+ Helper.getBuilder().setInstrAndDebugLoc(*${fabs});
+ Register Abs = Helper.getBuilder()
+ .buildFAbs(MRI.getType(Src), Src,
+ ${fabs}->getFlags())
+ .getReg(0);
+ Helper.getBuilder().buildFPTrunc(${dst}.getReg(), Abs,
+ ${fptrunc}->getFlags());
+ ${fabs}->eraseFromParent();
+ }])>;
+
// Fold (unmerge cst) -> cst1, cst2, ...
def unmerge_cst_matchinfo : GIDefMatchData<"SmallVector<APInt, 8>">;
def unmerge_cst : GICombineRule<
@@ -2619,6 +2637,7 @@ def all_combines : GICombineGroup<[integer_reassoc_combines, trivial_combines,
div_rem_to_divrem, funnel_shift_combines, bitreverse_shift, commute_shift,
form_bitfield_extract, constant_fold_binops, constant_fold_fma,
constant_fold_cast_op, constant_fold_unary_int_op, fabs_fneg_fold,
+ fabs_fptrunc_fold,
mulh_combines, redundant_neg_operands,
and_or_disjoint_mask, fma_combines, fold_binop_into_select,
intrem_combines, intdiv_combines, fdiv_repeated_divison,
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index e04e9578a3232..b8419544839cd 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -20623,6 +20623,14 @@ SDValue DAGCombiner::visitFABS(SDNode *N) {
if (SDValue C = DAG.FoldConstantArithmetic(ISD::FABS, DL, VT, {N0}))
return C;
+ // fold (fabs (fpround x)) -> (fpround (fabs x))
+ if (N0.getOpcode() == ISD::FP_ROUND && N0.hasOneUse()) {
+ SDValue Abs = DAG.getNode(ISD::FABS, DL, N0.getOperand(0).getValueType(),
+ N0.getOperand(0), N->getFlags());
+ return DAG.getNode(ISD::FP_ROUND, DL, VT, Abs, N0.getOperand(1),
+ N0->getFlags());
+ }
+
if (SimplifyDemandedBits(SDValue(N, 0)))
return SDValue(N, 0);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
index 0c348bb647c0c..9d554df1454bb 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
@@ -115,14 +115,6 @@ def foldable_fneg : GICombineRule<
[{ return Helper.matchFoldableFneg(*${ffn}, ${matchinfo}); }]),
(apply [{ Helper.applyFoldableFneg(*${ffn}, ${matchinfo}); }])>;
-// fabs (fptrunc x) -> fptrunc (fabs x)
-def fold_fabs_fptrunc : GICombineRule<
- (defs root:$dst),
- (match (G_FABS $dst, $round):$fabs,
- (G_FPTRUNC $round, $src):$fptrunc,
- [{ return Helper.matchFoldFAbsFptrunc(*${fabs}, *${fptrunc}); }]),
- (apply [{ Helper.applyFoldFAbsFptrunc(*${fabs}, *${fptrunc}); }])>;
-
// Detects s_mul_u64 instructions whose higher bits are zero/sign extended.
def smulu64 : GICombineRule<
(defs root:$smul, unsigned_matchinfo:$matchinfo),
@@ -245,7 +237,7 @@ def gfx8_combines : GICombineGroup<[expand_promoted_fmed3]>;
def AMDGPUPreLegalizerCombiner: GICombiner<
"AMDGPUPreLegalizerCombinerImpl",
[all_combines, combine_fmul_with_select_to_fldexp, clamp_i64_to_i16,
- foldable_fneg, fold_fabs_fptrunc, combine_shuffle_vector,
+ foldable_fneg, combine_shuffle_vector,
combine_shuffle_vector_to_build_vector,
binop_s64_with_s32_mask_combines, combine_or_s64_s32]> {
let CombineAllMethodName = "tryCombineAllImpl";
@@ -255,8 +247,7 @@ def AMDGPUPostLegalizerCombiner: GICombiner<
"AMDGPUPostLegalizerCombinerImpl",
[all_combines, gfx6gfx7_combines, gfx8_combines, combine_fmul_with_select_to_fldexp,
uchar_to_float, cvt_f32_ubyteN, remove_fcanonicalize, foldable_fneg,
- fold_fabs_fptrunc, rcp_sqrt_to_rsq, fdiv_by_sqrt_to_rsq_f16,
- sign_extension_in_reg, smulu64,
+ rcp_sqrt_to_rsq, fdiv_by_sqrt_to_rsq_f16, sign_extension_in_reg, smulu64,
binop_s64_with_s32_mask_combines, combine_or_s64_s32]> {
let CombineAllMethodName = "tryCombineAllImpl";
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
index 955c561f9052c..1a158b335321d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
@@ -10,7 +10,6 @@
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
-#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/Target/TargetMachine.h"
@@ -402,28 +401,6 @@ void AMDGPUCombinerHelper::applyFoldableFneg(MachineInstr &MI,
MI.eraseFromParent();
}
-bool AMDGPUCombinerHelper::matchFoldFAbsFptrunc(MachineInstr &Fabs,
- MachineInstr &Fptrunc) const {
- Register Round = Fptrunc.getOperand(0).getReg();
- if (!MRI.hasOneNonDBGUse(Round))
- return false;
-
- LLT SrcTy = MRI.getType(Fptrunc.getOperand(1).getReg());
- return isLegalOrBeforeLegalizer({TargetOpcode::G_FABS, {SrcTy}});
-}
-
-void AMDGPUCombinerHelper::applyFoldFAbsFptrunc(MachineInstr &Fabs,
- MachineInstr &Fptrunc) const {
- // fabs (fptrunc x) -> fptrunc (fabs x)
- Register Dst = Fabs.getOperand(0).getReg();
- Register Src = Fptrunc.getOperand(1).getReg();
- Builder.setInstrAndDebugLoc(Fabs);
- Register Abs =
- Builder.buildFAbs(MRI.getType(Src), Src, Fabs.getFlags()).getReg(0);
- Builder.buildFPTrunc(Dst, Abs, Fptrunc.getFlags());
- Fabs.eraseFromParent();
-}
-
// TODO: Should return converted value / extension source and avoid introducing
// intermediate fptruncs in the apply function.
static bool isFPExtFromF16OrConst(const MachineRegisterInfo &MRI,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h b/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h
index ffbb3a4e69305..243474a57cfab 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h
@@ -35,9 +35,6 @@ class AMDGPUCombinerHelper : public CombinerHelper {
bool matchFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo) const;
void applyFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo) const;
- bool matchFoldFAbsFptrunc(MachineInstr &Fabs, MachineInstr &Fptrunc) const;
- void applyFoldFAbsFptrunc(MachineInstr &Fabs, MachineInstr &Fptrunc) const;
-
bool matchExpandPromotedF16FMed3(MachineInstr &MI, Register Src0,
Register Src1, Register Src2) const;
void applyExpandPromotedF16FMed3(MachineInstr &MI, Register Src0,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 9386750190f42..336700afbcbbb 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -5545,17 +5545,6 @@ SDValue AMDGPUTargetLowering::performFAbsCombine(SDNode *N,
DAG.getConstant(0x7fff, SL, SrcVT));
return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFAbs);
}
- case ISD::FP_ROUND: {
- SDValue CvtSrc = N0.getOperand(0);
- EVT SrcVT = CvtSrc.getValueType();
- if (!isOperationLegal(ISD::FABS, SrcVT))
- return SDValue();
-
- SDLoc SL(N);
- SDValue Abs = DAG.getNode(ISD::FABS, SL, SrcVT, CvtSrc);
- return DAG.getNode(ISD::FP_ROUND, SL, N->getValueType(0), Abs,
- N0.getOperand(1));
- }
default:
return SDValue();
}
>From ddffbd2e0f46e7a6327f7ddccb2108f164ba9ad8 Mon Sep 17 00:00:00 2001
From: Chinmay Deshpande <chdeshpa at amd.com>
Date: Fri, 19 Jun 2026 13:02:14 -0400
Subject: [PATCH 3/6] Remove unnecessary change
---
llvm/lib/Target/AMDGPU/AMDGPUCombine.td | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
index 9d554df1454bb..620cefceda189 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
@@ -237,8 +237,7 @@ def gfx8_combines : GICombineGroup<[expand_promoted_fmed3]>;
def AMDGPUPreLegalizerCombiner: GICombiner<
"AMDGPUPreLegalizerCombinerImpl",
[all_combines, combine_fmul_with_select_to_fldexp, clamp_i64_to_i16,
- foldable_fneg, combine_shuffle_vector,
- combine_shuffle_vector_to_build_vector,
+ foldable_fneg, combine_shuffle_vector, combine_shuffle_vector_to_build_vector,
binop_s64_with_s32_mask_combines, combine_or_s64_s32]> {
let CombineAllMethodName = "tryCombineAllImpl";
}
>From bff1b28d64d17d34e836e5a1621d8f06bcc0fa7d Mon Sep 17 00:00:00 2001
From: Chinmay Deshpande <chdeshpa at amd.com>
Date: Mon, 22 Jun 2026 11:21:29 -0400
Subject: [PATCH 4/6] Add GISel legality check
---
llvm/include/llvm/Target/GlobalISel/Combine.td | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index 623a7d48d9c82..80fefce983693 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -1057,7 +1057,10 @@ def fabs_fptrunc_fold: GICombineRule <
(defs root:$dst),
(match (G_FPTRUNC $round, $src):$fptrunc,
(G_FABS $dst, $round):$fabs,
- [{ return MRI.hasOneNonDBGUse(${round}.getReg()); }]),
+ [{ return MRI.hasOneNonDBGUse(${round}.getReg()) &&
+ Helper.isLegalOrBeforeLegalizer(
+ {TargetOpcode::G_FABS,
+ {MRI.getType(${src}.getReg())}}); }]),
(apply [{
Register Src = ${src}.getReg();
Helper.getBuilder().setInstrAndDebugLoc(*${fabs});
>From b76da029643942691a3a984209f990a29719cf34 Mon Sep 17 00:00:00 2001
From: Chinmay Deshpande <chdeshpa at amd.com>
Date: Tue, 23 Jun 2026 11:15:59 -0400
Subject: [PATCH 5/6] Move back to being AMDGPU specific
Change-Id: I67db2eaba8d4b8c53ec62d210e75ee5788dbdf4b
---
.../include/llvm/Target/GlobalISel/Combine.td | 22 ------------------
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 -------
llvm/lib/Target/AMDGPU/AMDGPUCombine.td | 14 +++++++++--
.../Target/AMDGPU/AMDGPUCombinerHelper.cpp | 23 +++++++++++++++++++
llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h | 3 +++
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 10 ++++++++
6 files changed, 48 insertions(+), 32 deletions(-)
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index 80fefce983693..1b0602af68367 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -1052,27 +1052,6 @@ def fabs_fneg_fold: GICombineRule <
(G_FABS $dst, $tmp)),
(apply (G_FABS $dst, $x))>;
-// Fold (fabs (fptrunc x)) -> (fptrunc (fabs x)).
-def fabs_fptrunc_fold: GICombineRule <
- (defs root:$dst),
- (match (G_FPTRUNC $round, $src):$fptrunc,
- (G_FABS $dst, $round):$fabs,
- [{ return MRI.hasOneNonDBGUse(${round}.getReg()) &&
- Helper.isLegalOrBeforeLegalizer(
- {TargetOpcode::G_FABS,
- {MRI.getType(${src}.getReg())}}); }]),
- (apply [{
- Register Src = ${src}.getReg();
- Helper.getBuilder().setInstrAndDebugLoc(*${fabs});
- Register Abs = Helper.getBuilder()
- .buildFAbs(MRI.getType(Src), Src,
- ${fabs}->getFlags())
- .getReg(0);
- Helper.getBuilder().buildFPTrunc(${dst}.getReg(), Abs,
- ${fptrunc}->getFlags());
- ${fabs}->eraseFromParent();
- }])>;
-
// Fold (unmerge cst) -> cst1, cst2, ...
def unmerge_cst_matchinfo : GIDefMatchData<"SmallVector<APInt, 8>">;
def unmerge_cst : GICombineRule<
@@ -2640,7 +2619,6 @@ def all_combines : GICombineGroup<[integer_reassoc_combines, trivial_combines,
div_rem_to_divrem, funnel_shift_combines, bitreverse_shift, commute_shift,
form_bitfield_extract, constant_fold_binops, constant_fold_fma,
constant_fold_cast_op, constant_fold_unary_int_op, fabs_fneg_fold,
- fabs_fptrunc_fold,
mulh_combines, redundant_neg_operands,
and_or_disjoint_mask, fma_combines, fold_binop_into_select,
intrem_combines, intdiv_combines, fdiv_repeated_divison,
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index b8419544839cd..e04e9578a3232 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -20623,14 +20623,6 @@ SDValue DAGCombiner::visitFABS(SDNode *N) {
if (SDValue C = DAG.FoldConstantArithmetic(ISD::FABS, DL, VT, {N0}))
return C;
- // fold (fabs (fpround x)) -> (fpround (fabs x))
- if (N0.getOpcode() == ISD::FP_ROUND && N0.hasOneUse()) {
- SDValue Abs = DAG.getNode(ISD::FABS, DL, N0.getOperand(0).getValueType(),
- N0.getOperand(0), N->getFlags());
- return DAG.getNode(ISD::FP_ROUND, DL, VT, Abs, N0.getOperand(1),
- N0->getFlags());
- }
-
if (SimplifyDemandedBits(SDValue(N, 0)))
return SDValue(N, 0);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
index 620cefceda189..0c348bb647c0c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
@@ -115,6 +115,14 @@ def foldable_fneg : GICombineRule<
[{ return Helper.matchFoldableFneg(*${ffn}, ${matchinfo}); }]),
(apply [{ Helper.applyFoldableFneg(*${ffn}, ${matchinfo}); }])>;
+// fabs (fptrunc x) -> fptrunc (fabs x)
+def fold_fabs_fptrunc : GICombineRule<
+ (defs root:$dst),
+ (match (G_FABS $dst, $round):$fabs,
+ (G_FPTRUNC $round, $src):$fptrunc,
+ [{ return Helper.matchFoldFAbsFptrunc(*${fabs}, *${fptrunc}); }]),
+ (apply [{ Helper.applyFoldFAbsFptrunc(*${fabs}, *${fptrunc}); }])>;
+
// Detects s_mul_u64 instructions whose higher bits are zero/sign extended.
def smulu64 : GICombineRule<
(defs root:$smul, unsigned_matchinfo:$matchinfo),
@@ -237,7 +245,8 @@ def gfx8_combines : GICombineGroup<[expand_promoted_fmed3]>;
def AMDGPUPreLegalizerCombiner: GICombiner<
"AMDGPUPreLegalizerCombinerImpl",
[all_combines, combine_fmul_with_select_to_fldexp, clamp_i64_to_i16,
- foldable_fneg, combine_shuffle_vector, combine_shuffle_vector_to_build_vector,
+ foldable_fneg, fold_fabs_fptrunc, combine_shuffle_vector,
+ combine_shuffle_vector_to_build_vector,
binop_s64_with_s32_mask_combines, combine_or_s64_s32]> {
let CombineAllMethodName = "tryCombineAllImpl";
}
@@ -246,7 +255,8 @@ def AMDGPUPostLegalizerCombiner: GICombiner<
"AMDGPUPostLegalizerCombinerImpl",
[all_combines, gfx6gfx7_combines, gfx8_combines, combine_fmul_with_select_to_fldexp,
uchar_to_float, cvt_f32_ubyteN, remove_fcanonicalize, foldable_fneg,
- rcp_sqrt_to_rsq, fdiv_by_sqrt_to_rsq_f16, sign_extension_in_reg, smulu64,
+ fold_fabs_fptrunc, rcp_sqrt_to_rsq, fdiv_by_sqrt_to_rsq_f16,
+ sign_extension_in_reg, smulu64,
binop_s64_with_s32_mask_combines, combine_or_s64_s32]> {
let CombineAllMethodName = "tryCombineAllImpl";
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
index 1a158b335321d..955c561f9052c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
@@ -10,6 +10,7 @@
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
+#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/Target/TargetMachine.h"
@@ -401,6 +402,28 @@ void AMDGPUCombinerHelper::applyFoldableFneg(MachineInstr &MI,
MI.eraseFromParent();
}
+bool AMDGPUCombinerHelper::matchFoldFAbsFptrunc(MachineInstr &Fabs,
+ MachineInstr &Fptrunc) const {
+ Register Round = Fptrunc.getOperand(0).getReg();
+ if (!MRI.hasOneNonDBGUse(Round))
+ return false;
+
+ LLT SrcTy = MRI.getType(Fptrunc.getOperand(1).getReg());
+ return isLegalOrBeforeLegalizer({TargetOpcode::G_FABS, {SrcTy}});
+}
+
+void AMDGPUCombinerHelper::applyFoldFAbsFptrunc(MachineInstr &Fabs,
+ MachineInstr &Fptrunc) const {
+ // fabs (fptrunc x) -> fptrunc (fabs x)
+ Register Dst = Fabs.getOperand(0).getReg();
+ Register Src = Fptrunc.getOperand(1).getReg();
+ Builder.setInstrAndDebugLoc(Fabs);
+ Register Abs =
+ Builder.buildFAbs(MRI.getType(Src), Src, Fabs.getFlags()).getReg(0);
+ Builder.buildFPTrunc(Dst, Abs, Fptrunc.getFlags());
+ Fabs.eraseFromParent();
+}
+
// TODO: Should return converted value / extension source and avoid introducing
// intermediate fptruncs in the apply function.
static bool isFPExtFromF16OrConst(const MachineRegisterInfo &MRI,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h b/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h
index 243474a57cfab..ffbb3a4e69305 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h
@@ -35,6 +35,9 @@ class AMDGPUCombinerHelper : public CombinerHelper {
bool matchFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo) const;
void applyFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo) const;
+ bool matchFoldFAbsFptrunc(MachineInstr &Fabs, MachineInstr &Fptrunc) const;
+ void applyFoldFAbsFptrunc(MachineInstr &Fabs, MachineInstr &Fptrunc) const;
+
bool matchExpandPromotedF16FMed3(MachineInstr &MI, Register Src0,
Register Src1, Register Src2) const;
void applyExpandPromotedF16FMed3(MachineInstr &MI, Register Src0,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 336700afbcbbb..18227df3280bc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -5545,6 +5545,16 @@ SDValue AMDGPUTargetLowering::performFAbsCombine(SDNode *N,
DAG.getConstant(0x7fff, SL, SrcVT));
return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFAbs);
}
+ case ISD::FP_ROUND: {
+ SDLoc SL(N);
+ SDValue CvtSrc = N0.getOperand(0);
+
+ // fabs (fp_round x) -> fp_round (fabs x)
+ SDValue Abs =
+ DAG.getNode(ISD::FABS, SL, CvtSrc.getValueType(), CvtSrc, N->getFlags());
+ return DAG.getNode(ISD::FP_ROUND, SL, N->getValueType(0), Abs,
+ N0.getOperand(1), N0->getFlags());
+ }
default:
return SDValue();
}
>From c5c5f441dcdf5701dc068b1482c076d500fc0f4a Mon Sep 17 00:00:00 2001
From: Chinmay Deshpande <chdeshpa at amd.com>
Date: Tue, 23 Jun 2026 11:24:41 -0400
Subject: [PATCH 6/6] Fix formatting
Change-Id: Ic29193b957bee133c18ce378271f1f41b6c10811
---
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 18227df3280bc..a8c310a04b9e8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -5550,8 +5550,8 @@ SDValue AMDGPUTargetLowering::performFAbsCombine(SDNode *N,
SDValue CvtSrc = N0.getOperand(0);
// fabs (fp_round x) -> fp_round (fabs x)
- SDValue Abs =
- DAG.getNode(ISD::FABS, SL, CvtSrc.getValueType(), CvtSrc, N->getFlags());
+ SDValue Abs = DAG.getNode(ISD::FABS, SL, CvtSrc.getValueType(), CvtSrc,
+ N->getFlags());
return DAG.getNode(ISD::FP_ROUND, SL, N->getValueType(0), Abs,
N0.getOperand(1), N0->getFlags());
}
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