[llvm] 16ee9ad - [NFC][LLVM][CodeGen] Refactor testing of SVE predicate logical instructions. (#206737)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 30 08:01:53 PDT 2026
Author: Paul Walker
Date: 2026-06-30T16:01:48+01:00
New Revision: 16ee9ad499a1d8c500f902571249925849f6f653
URL: https://github.com/llvm/llvm-project/commit/16ee9ad499a1d8c500f902571249925849f6f653
DIFF: https://github.com/llvm/llvm-project/commit/16ee9ad499a1d8c500f902571249925849f6f653.diff
LOG: [NFC][LLVM][CodeGen] Refactor testing of SVE predicate logical instructions. (#206737)
Added:
Modified:
llvm/test/CodeGen/AArch64/sve-intrinsics-pred-operations.ll
llvm/test/CodeGen/AArch64/sve-pred-log.ll
llvm/test/CodeGen/AArch64/sve-select.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-pred-operations.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-pred-operations.ll
index fd1469930726f..8a0403c59732a 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-pred-operations.ll
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-pred-operations.ll
@@ -2,6 +2,36 @@
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
+;
+; AND
+;
+
+define <vscale x 16 x i1> @and_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: and_b8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and p0.b, p0/z, p1.b, p2.b
+; CHECK-NEXT: ret
+ %res = call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> %pg,
+ <vscale x 16 x i1> %a,
+ <vscale x 16 x i1> %b)
+ ret <vscale x 16 x i1> %res;
+}
+
+;
+; BIC
+;
+
+define <vscale x 16 x i1> @bic_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: bic_b8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic p0.b, p0/z, p1.b, p2.b
+; CHECK-NEXT: ret
+ %res = call <vscale x 16 x i1> @llvm.aarch64.sve.bic.z.nxv16i1(<vscale x 16 x i1> %pg,
+ <vscale x 16 x i1> %a,
+ <vscale x 16 x i1> %b)
+ ret <vscale x 16 x i1> %res;
+}
+
;
; BRKA
;
@@ -11,10 +41,10 @@ define <vscale x 16 x i1> @brka_m_b8(<vscale x 16 x i1> %inactive, <vscale x 16
; CHECK: // %bb.0:
; CHECK-NEXT: brka p0.b, p1/m, p2.b
; CHECK-NEXT: ret
- %out = call <vscale x 16 x i1> @llvm.aarch64.sve.brka.nxv16i1(<vscale x 16 x i1> %inactive,
+ %res = call <vscale x 16 x i1> @llvm.aarch64.sve.brka.nxv16i1(<vscale x 16 x i1> %inactive,
<vscale x 16 x i1> %pg,
<vscale x 16 x i1> %a)
- ret <vscale x 16 x i1> %out
+ ret <vscale x 16 x i1> %res
}
define <vscale x 16 x i1> @brka_z_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
@@ -22,9 +52,9 @@ define <vscale x 16 x i1> @brka_z_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1>
; CHECK: // %bb.0:
; CHECK-NEXT: brka p0.b, p0/z, p1.b
; CHECK-NEXT: ret
- %out = call <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1> %pg,
+ %res = call <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1> %pg,
<vscale x 16 x i1> %a)
- ret <vscale x 16 x i1> %out
+ ret <vscale x 16 x i1> %res
}
;
@@ -36,10 +66,10 @@ define <vscale x 16 x i1> @brkb_m_b8(<vscale x 16 x i1> %inactive, <vscale x 16
; CHECK: // %bb.0:
; CHECK-NEXT: brkb p0.b, p1/m, p2.b
; CHECK-NEXT: ret
- %out = call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.nxv16i1(<vscale x 16 x i1> %inactive,
+ %res = call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.nxv16i1(<vscale x 16 x i1> %inactive,
<vscale x 16 x i1> %pg,
<vscale x 16 x i1> %a)
- ret <vscale x 16 x i1> %out
+ ret <vscale x 16 x i1> %res
}
define <vscale x 16 x i1> @brkb_z_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
@@ -47,9 +77,9 @@ define <vscale x 16 x i1> @brkb_z_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1>
; CHECK: // %bb.0:
; CHECK-NEXT: brkb p0.b, p0/z, p1.b
; CHECK-NEXT: ret
- %out = call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1> %pg,
+ %res = call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1> %pg,
<vscale x 16 x i1> %a)
- ret <vscale x 16 x i1> %out
+ ret <vscale x 16 x i1> %res
}
;
@@ -62,10 +92,10 @@ define <vscale x 16 x i1> @brkn_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a
; CHECK-NEXT: brkn p2.b, p0/z, p1.b, p2.b
; CHECK-NEXT: mov p0.b, p2.b
; CHECK-NEXT: ret
- %out = call <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1> %pg,
+ %res = call <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1> %pg,
<vscale x 16 x i1> %a,
<vscale x 16 x i1> %b)
- ret <vscale x 16 x i1> %out
+ ret <vscale x 16 x i1> %res
}
;
@@ -77,10 +107,10 @@ define <vscale x 16 x i1> @brkpa_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %
; CHECK: // %bb.0:
; CHECK-NEXT: brkpa p0.b, p0/z, p1.b, p2.b
; CHECK-NEXT: ret
- %out = call <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1> %pg,
+ %res = call <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1> %pg,
<vscale x 16 x i1> %a,
<vscale x 16 x i1> %b)
- ret <vscale x 16 x i1> %out
+ ret <vscale x 16 x i1> %res
}
;
@@ -92,10 +122,85 @@ define <vscale x 16 x i1> @brkpb_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %
; CHECK: // %bb.0:
; CHECK-NEXT: brkpb p0.b, p0/z, p1.b, p2.b
; CHECK-NEXT: ret
- %out = call <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1> %pg,
+ %res = call <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1> %pg,
<vscale x 16 x i1> %a,
<vscale x 16 x i1> %b)
- ret <vscale x 16 x i1> %out
+ ret <vscale x 16 x i1> %res
+}
+
+;
+; EOR
+;
+
+define <vscale x 16 x i1> @eor_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: eor_b8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: eor p0.b, p0/z, p1.b, p2.b
+; CHECK-NEXT: ret
+ %res = call <vscale x 16 x i1> @llvm.aarch64.sve.eor.z.nxv16i1(<vscale x 16 x i1> %pg,
+ <vscale x 16 x i1> %a,
+ <vscale x 16 x i1> %b)
+ ret <vscale x 16 x i1> %res;
+}
+
+;
+; ORN
+;
+
+define <vscale x 16 x i1> @orn_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: orn_b8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: orn p0.b, p0/z, p1.b, p2.b
+; CHECK-NEXT: ret
+ %res = call <vscale x 16 x i1> @llvm.aarch64.sve.orn.z.nxv16i1(<vscale x 16 x i1> %pg,
+ <vscale x 16 x i1> %a,
+ <vscale x 16 x i1> %b)
+ ret <vscale x 16 x i1> %res;
+}
+
+;
+; ORR
+;
+
+define <vscale x 16 x i1> @orr_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: orr_b8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr p0.b, p0/z, p1.b, p2.b
+; CHECK-NEXT: ret
+ %res = call <vscale x 16 x i1> @llvm.aarch64.sve.orr.z.nxv16i1(<vscale x 16 x i1> %pg,
+ <vscale x 16 x i1> %a,
+ <vscale x 16 x i1> %b)
+ ret <vscale x 16 x i1> %res;
+}
+
+;
+; NAND
+;
+
+define <vscale x 16 x i1> @nand_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: nand_b8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: nand p0.b, p0/z, p1.b, p2.b
+; CHECK-NEXT: ret
+ %res = call <vscale x 16 x i1> @llvm.aarch64.sve.nand.z.nxv16i1(<vscale x 16 x i1> %pg,
+ <vscale x 16 x i1> %a,
+ <vscale x 16 x i1> %b)
+ ret <vscale x 16 x i1> %res;
+}
+
+;
+; NOR
+;
+
+define <vscale x 16 x i1> @nor_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: nor_b8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: nor p0.b, p0/z, p1.b, p2.b
+; CHECK-NEXT: ret
+ %res = call <vscale x 16 x i1> @llvm.aarch64.sve.nor.z.nxv16i1(<vscale x 16 x i1> %pg,
+ <vscale x 16 x i1> %a,
+ <vscale x 16 x i1> %b)
+ ret <vscale x 16 x i1> %res;
}
;
@@ -108,9 +213,9 @@ define <vscale x 16 x i1> @pfirst_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1>
; CHECK-NEXT: pfirst p1.b, p0, p1.b
; CHECK-NEXT: mov p0.b, p1.b
; CHECK-NEXT: ret
- %out = call <vscale x 16 x i1> @llvm.aarch64.sve.pfirst.nxv16i1(<vscale x 16 x i1> %pg,
+ %res = call <vscale x 16 x i1> @llvm.aarch64.sve.pfirst.nxv16i1(<vscale x 16 x i1> %pg,
<vscale x 16 x i1> %a)
- ret <vscale x 16 x i1> %out
+ ret <vscale x 16 x i1> %res
}
;
@@ -123,9 +228,9 @@ define <vscale x 16 x i1> @pnext_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %
; CHECK-NEXT: pnext p1.b, p0, p1.b
; CHECK-NEXT: mov p0.b, p1.b
; CHECK-NEXT: ret
- %out = call <vscale x 16 x i1> @llvm.aarch64.sve.pnext.nxv16i1(<vscale x 16 x i1> %pg,
+ %res = call <vscale x 16 x i1> @llvm.aarch64.sve.pnext.nxv16i1(<vscale x 16 x i1> %pg,
<vscale x 16 x i1> %a)
- ret <vscale x 16 x i1> %out
+ ret <vscale x 16 x i1> %res
}
define <vscale x 8 x i1> @pnext_b16(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %a) {
@@ -134,9 +239,9 @@ define <vscale x 8 x i1> @pnext_b16(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %a)
; CHECK-NEXT: pnext p1.h, p0, p1.h
; CHECK-NEXT: mov p0.b, p1.b
; CHECK-NEXT: ret
- %out = call <vscale x 8 x i1> @llvm.aarch64.sve.pnext.nxv8i1(<vscale x 8 x i1> %pg,
+ %res = call <vscale x 8 x i1> @llvm.aarch64.sve.pnext.nxv8i1(<vscale x 8 x i1> %pg,
<vscale x 8 x i1> %a)
- ret <vscale x 8 x i1> %out
+ ret <vscale x 8 x i1> %res
}
define <vscale x 4 x i1> @pnext_b32(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %a) {
@@ -145,9 +250,9 @@ define <vscale x 4 x i1> @pnext_b32(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %a)
; CHECK-NEXT: pnext p1.s, p0, p1.s
; CHECK-NEXT: mov p0.b, p1.b
; CHECK-NEXT: ret
- %out = call <vscale x 4 x i1> @llvm.aarch64.sve.pnext.nxv4i1(<vscale x 4 x i1> %pg,
+ %res = call <vscale x 4 x i1> @llvm.aarch64.sve.pnext.nxv4i1(<vscale x 4 x i1> %pg,
<vscale x 4 x i1> %a)
- ret <vscale x 4 x i1> %out
+ ret <vscale x 4 x i1> %res
}
define <vscale x 2 x i1> @pnext_b64(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %a) {
@@ -156,9 +261,9 @@ define <vscale x 2 x i1> @pnext_b64(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %a)
; CHECK-NEXT: pnext p1.d, p0, p1.d
; CHECK-NEXT: mov p0.b, p1.b
; CHECK-NEXT: ret
- %out = call <vscale x 2 x i1> @llvm.aarch64.sve.pnext.nxv2i1(<vscale x 2 x i1> %pg,
+ %res = call <vscale x 2 x i1> @llvm.aarch64.sve.pnext.nxv2i1(<vscale x 2 x i1> %pg,
<vscale x 2 x i1> %a)
- ret <vscale x 2 x i1> %out
+ ret <vscale x 2 x i1> %res
}
;
@@ -223,25 +328,3 @@ define <vscale x 2 x i1> @punpklo_b4(<vscale x 4 x i1> %a) {
ret <vscale x 2 x i1> %res
}
-declare <vscale x 16 x i1> @llvm.aarch64.sve.brka.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
-declare <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
-declare <vscale x 16 x i1> @llvm.aarch64.sve.brkb.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
-declare <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
-declare <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
-declare <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
-declare <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
-
-declare <vscale x 16 x i1> @llvm.aarch64.sve.pfirst.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
-
-declare <vscale x 16 x i1> @llvm.aarch64.sve.pnext.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
-declare <vscale x 8 x i1> @llvm.aarch64.sve.pnext.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>)
-declare <vscale x 4 x i1> @llvm.aarch64.sve.pnext.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>)
-declare <vscale x 2 x i1> @llvm.aarch64.sve.pnext.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>)
-
-declare <vscale x 8 x i1> @llvm.aarch64.sve.punpkhi.nxv8i1(<vscale x 16 x i1>)
-declare <vscale x 4 x i1> @llvm.aarch64.sve.punpkhi.nxv4i1(<vscale x 8 x i1>)
-declare <vscale x 2 x i1> @llvm.aarch64.sve.punpkhi.nxv2i1(<vscale x 4 x i1>)
-
-declare <vscale x 8 x i1> @llvm.aarch64.sve.punpklo.nxv8i1(<vscale x 16 x i1>)
-declare <vscale x 4 x i1> @llvm.aarch64.sve.punpklo.nxv4i1(<vscale x 8 x i1>)
-declare <vscale x 2 x i1> @llvm.aarch64.sve.punpklo.nxv2i1(<vscale x 4 x i1>)
diff --git a/llvm/test/CodeGen/AArch64/sve-pred-log.ll b/llvm/test/CodeGen/AArch64/sve-pred-log.ll
index a66375258db3a..418dc503695a4 100644
--- a/llvm/test/CodeGen/AArch64/sve-pred-log.ll
+++ b/llvm/test/CodeGen/AArch64/sve-pred-log.ll
@@ -1,294 +1,855 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
-
-define <vscale x 16 x i1> @vselect_16(<vscale x 16 x i1> %Pg, <vscale x 16 x i1> %Pn, <vscale x 16 x i1> %Pd) {
-; CHECK-LABEL: vselect_16:
-; CHECK: sel p0.b, p0, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = select <vscale x 16 x i1> %Pg, <vscale x 16 x i1> %Pn, <vscale x 16 x i1> %Pd
- ret <vscale x 16 x i1> %res;
-}
-
-define <vscale x 8 x i1> @vselect_8(<vscale x 8 x i1> %Pg, <vscale x 8 x i1> %Pn, <vscale x 8 x i1> %Pd) {
-; CHECK-LABEL: vselect_8:
-; CHECK: sel p0.b, p0, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = select <vscale x 8 x i1> %Pg, <vscale x 8 x i1> %Pn, <vscale x 8 x i1> %Pd
- ret <vscale x 8 x i1> %res;
-}
-
-define <vscale x 4 x i1> @vselect_4(<vscale x 4 x i1> %Pg, <vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd) {
-; CHECK-LABEL: vselect_4:
-; CHECK: sel p0.b, p0, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = select <vscale x 4 x i1> %Pg, <vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd
- ret <vscale x 4 x i1> %res;
-}
-
-define <vscale x 2 x i1> @vselect_2(<vscale x 2 x i1> %Pg, <vscale x 2 x i1> %Pn, <vscale x 2 x i1> %Pd) {
-; CHECK-LABEL: vselect_2:
-; CHECK: sel p0.b, p0, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = select <vscale x 2 x i1> %Pg, <vscale x 2 x i1> %Pn, <vscale x 2 x i1> %Pd
- ret <vscale x 2 x i1> %res;
-}
-
-define <vscale x 1 x i1> @vselect_1(<vscale x 1 x i1> %Pg, <vscale x 1 x i1> %Pn, <vscale x 1 x i1> %Pd) {
-; CHECK-LABEL: vselect_1:
-; CHECK: sel p0.b, p0, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = select <vscale x 1 x i1> %Pg, <vscale x 1 x i1> %Pn, <vscale x 1 x i1> %Pd
- ret <vscale x 1 x i1> %res;
-}
-
-define <vscale x 16 x i1> @and_16(<vscale x 16 x i1> %Pg, <vscale x 16 x i1> %Pn, <vscale x 16 x i1> %Pd) {
-; CHECK-LABEL: and_16:
-; CHECK: and p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> %Pg, <vscale x 16 x i1> %Pn, <vscale x 16 x i1> %Pd)
- ret <vscale x 16 x i1> %res;
-}
-
-define <vscale x 8 x i1> @and_8(<vscale x 8 x i1> %Pg, <vscale x 8 x i1> %Pn, <vscale x 8 x i1> %Pd) {
-; CHECK-LABEL: and_8:
-; CHECK: and p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 8 x i1> @llvm.aarch64.sve.and.z.nxv8i1(<vscale x 8 x i1> %Pg, <vscale x 8 x i1> %Pn, <vscale x 8 x i1> %Pd)
- ret <vscale x 8 x i1> %res;
-}
-
-define <vscale x 4 x i1> @and_4(<vscale x 4 x i1> %Pg, <vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd) {
-; CHECK-LABEL: and_4:
-; CHECK: and p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 4 x i1> @llvm.aarch64.sve.and.z.nxv4i1(<vscale x 4 x i1> %Pg, <vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd)
- ret <vscale x 4 x i1> %res;
-}
-
-define <vscale x 2 x i1> @and_2(<vscale x 2 x i1> %Pg, <vscale x 2 x i1> %Pn, <vscale x 2 x i1> %Pd) {
-; CHECK-LABEL: and_2:
-; CHECK: and p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 2 x i1> @llvm.aarch64.sve.and.z.nxv2i1(<vscale x 2 x i1> %Pg, <vscale x 2 x i1> %Pn, <vscale x 2 x i1> %Pd)
- ret <vscale x 2 x i1> %res;
-}
-
-define <vscale x 16 x i1> @bic_16(<vscale x 16 x i1> %Pg, <vscale x 16 x i1> %Pn, <vscale x 16 x i1> %Pd) {
-; CHECK-LABEL: bic_16:
-; CHECK: bic p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 16 x i1> @llvm.aarch64.sve.bic.z.nxv16i1(<vscale x 16 x i1> %Pg, <vscale x 16 x i1> %Pn, <vscale x 16 x i1> %Pd)
- ret <vscale x 16 x i1> %res;
-}
-
-define <vscale x 8 x i1> @bic_8(<vscale x 8 x i1> %Pg, <vscale x 8 x i1> %Pn, <vscale x 8 x i1> %Pd) {
-; CHECK-LABEL: bic_8:
-; CHECK: bic p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 8 x i1> @llvm.aarch64.sve.bic.z.nxv8i1(<vscale x 8 x i1> %Pg, <vscale x 8 x i1> %Pn, <vscale x 8 x i1> %Pd)
- ret <vscale x 8 x i1> %res;
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64-unknown-linux-gnu -mattr=+sve < %s | FileCheck %s
+
+define <vscale x 16 x i1> @and_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: and_nxv16i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %res = and <vscale x 16 x i1> %a, %b
+ ret <vscale x 16 x i1> %res
+}
+
+define <vscale x 8 x i1> @and_nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
+; CHECK-LABEL: and_nxv8i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %res = and <vscale x 8 x i1> %a, %b
+ ret <vscale x 8 x i1> %res
+}
+
+define <vscale x 4 x i1> @and_nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
+; CHECK-LABEL: and_nxv4i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %res = and <vscale x 4 x i1> %a, %b
+ ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 2 x i1> @and_nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
+; CHECK-LABEL: and_nxv2i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %res = and <vscale x 2 x i1> %a, %b
+ ret <vscale x 2 x i1> %res
+}
+
+define <vscale x 1 x i1> @and_nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
+; CHECK-LABEL: and_nxv1i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %res = and <vscale x 1 x i1> %a, %b
+ ret <vscale x 1 x i1> %res
+}
+
+define <vscale x 16 x i1> @and_and_nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: and_and_nxv16i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and p2.b, p1/z, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p2.b
+; CHECK-NEXT: ret
+ %op = and <vscale x 16 x i1> %a, %b
+ %res = and <vscale x 16 x i1> %pg, %op
+ ret <vscale x 16 x i1> %res
+}
+
+define <vscale x 8 x i1> @and_and_nxv8i1(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
+; CHECK-LABEL: and_and_nxv8i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and p2.b, p1/z, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p2.b
+; CHECK-NEXT: ret
+ %op = and <vscale x 8 x i1> %a, %b
+ %res = and <vscale x 8 x i1> %pg, %op
+ ret <vscale x 8 x i1> %res
+}
+
+define <vscale x 4 x i1> @and_and_nxv4i1(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
+; CHECK-LABEL: and_and_nxv4i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and p2.b, p1/z, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p2.b
+; CHECK-NEXT: ret
+ %op = and <vscale x 4 x i1> %a, %b
+ %res = and <vscale x 4 x i1> %pg, %op
+ ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 2 x i1> @and_and_nxv2i1(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
+; CHECK-LABEL: and_and_nxv2i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and p2.b, p1/z, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p2.b
+; CHECK-NEXT: ret
+ %op = and <vscale x 2 x i1> %a, %b
+ %res = and <vscale x 2 x i1> %pg, %op
+ ret <vscale x 2 x i1> %res
+}
+
+define <vscale x 1 x i1> @and_and_nxv1i1(<vscale x 1 x i1> %pg, <vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
+; CHECK-LABEL: and_and_nxv1i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and p2.b, p1/z, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p2.b
+; CHECK-NEXT: ret
+ %op = and <vscale x 1 x i1> %a, %b
+ %res = and <vscale x 1 x i1> %pg, %op
+ ret <vscale x 1 x i1> %res
+}
+
+define <vscale x 16 x i1> @and_bic_nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: and_bic_nxv16i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic p2.b, p1/z, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p2.b
+; CHECK-NEXT: ret
+ %not.b = xor <vscale x 16 x i1> %b, splat (i1 true)
+ %op = and <vscale x 16 x i1> %a, %not.b
+ %res = and <vscale x 16 x i1> %pg, %op
+ ret <vscale x 16 x i1> %res
+}
+
+define <vscale x 8 x i1> @and_bic_nxv8i1(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
+; CHECK-LABEL: and_bic_nxv8i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic p2.b, p1/z, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p2.b
+; CHECK-NEXT: ret
+ %not.b = xor <vscale x 8 x i1> %b, splat (i1 true)
+ %op = and <vscale x 8 x i1> %a, %not.b
+ %res = and <vscale x 8 x i1> %pg, %op
+ ret <vscale x 8 x i1> %res
+}
+
+define <vscale x 4 x i1> @and_bic_nxv4i1(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
+; CHECK-LABEL: and_bic_nxv4i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic p2.b, p1/z, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p2.b
+; CHECK-NEXT: ret
+ %not.b = xor <vscale x 4 x i1> %b, splat (i1 true)
+ %op = and <vscale x 4 x i1> %a, %not.b
+ %res = and <vscale x 4 x i1> %pg, %op
+ ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 2 x i1> @and_bic_nxv2i1(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
+; CHECK-LABEL: and_bic_nxv2i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic p2.b, p1/z, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p2.b
+; CHECK-NEXT: ret
+ %not.b = xor <vscale x 2 x i1> %b, splat (i1 true)
+ %op = and <vscale x 2 x i1> %a, %not.b
+ %res = and <vscale x 2 x i1> %pg, %op
+ ret <vscale x 2 x i1> %res
+}
+
+define <vscale x 1 x i1> @and_bic_nxv1i1(<vscale x 1 x i1> %pg, <vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
+; CHECK-LABEL: and_bic_nxv1i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic p2.b, p1/z, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p2.b
+; CHECK-NEXT: ret
+ %not.b = xor <vscale x 1 x i1> %b, splat (i1 true)
+ %op = and <vscale x 1 x i1> %a, %not.b
+ %res = and <vscale x 1 x i1> %pg, %op
+ ret <vscale x 1 x i1> %res
+}
+
+define <vscale x 16 x i1> @and_eor_nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: and_eor_nxv16i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p3.b
+; CHECK-NEXT: eor p1.b, p3/z, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %op = xor <vscale x 16 x i1> %a, %b
+ %res = and <vscale x 16 x i1> %pg, %op
+ ret <vscale x 16 x i1> %res
+}
+
+define <vscale x 8 x i1> @and_eor_nxv8i1(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
+; CHECK-LABEL: and_eor_nxv8i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p3.h
+; CHECK-NEXT: eor p1.b, p3/z, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %op = xor <vscale x 8 x i1> %a, %b
+ %res = and <vscale x 8 x i1> %pg, %op
+ ret <vscale x 8 x i1> %res
+}
+
+define <vscale x 4 x i1> @and_eor_nxv4i1(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
+; CHECK-LABEL: and_eor_nxv4i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p3.s
+; CHECK-NEXT: eor p1.b, p3/z, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %op = xor <vscale x 4 x i1> %a, %b
+ %res = and <vscale x 4 x i1> %pg, %op
+ ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 2 x i1> @and_eor_nxv2i1(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
+; CHECK-LABEL: and_eor_nxv2i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p3.d
+; CHECK-NEXT: eor p1.b, p3/z, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %op = xor <vscale x 2 x i1> %a, %b
+ %res = and <vscale x 2 x i1> %pg, %op
+ ret <vscale x 2 x i1> %res
+}
+
+define <vscale x 1 x i1> @and_eor_nxv1i1(<vscale x 1 x i1> %pg, <vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
+; CHECK-LABEL: and_eor_nxv1i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p3.d
+; CHECK-NEXT: eor p1.b, p3/z, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %op = xor <vscale x 1 x i1> %a, %b
+ %res = and <vscale x 1 x i1> %pg, %op
+ ret <vscale x 1 x i1> %res
+}
+
+define <vscale x 16 x i1> @and_orn_nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: and_orn_nxv16i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p3.b
+; CHECK-NEXT: not p2.b, p3/z, p2.b
+; CHECK-NEXT: sel p1.b, p1, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %not.b = xor <vscale x 16 x i1> %b, splat (i1 true)
+ %op = or <vscale x 16 x i1> %a, %not.b
+ %res = and <vscale x 16 x i1> %pg, %op
+ ret <vscale x 16 x i1> %res
+}
+
+define <vscale x 8 x i1> @and_orn_nxv8i1(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
+; CHECK-LABEL: and_orn_nxv8i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p3.h
+; CHECK-NEXT: not p2.b, p3/z, p2.b
+; CHECK-NEXT: sel p1.b, p1, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %not.b = xor <vscale x 8 x i1> %b, splat (i1 true)
+ %op = or <vscale x 8 x i1> %a, %not.b
+ %res = and <vscale x 8 x i1> %pg, %op
+ ret <vscale x 8 x i1> %res
+}
+
+define <vscale x 4 x i1> @and_orn_nxv4i1(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
+; CHECK-LABEL: and_orn_nxv4i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p3.s
+; CHECK-NEXT: not p2.b, p3/z, p2.b
+; CHECK-NEXT: sel p1.b, p1, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %not.b = xor <vscale x 4 x i1> %b, splat (i1 true)
+ %op = or <vscale x 4 x i1> %a, %not.b
+ %res = and <vscale x 4 x i1> %pg, %op
+ ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 2 x i1> @and_orn_nxv2i1(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
+; CHECK-LABEL: and_orn_nxv2i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p3.d
+; CHECK-NEXT: not p2.b, p3/z, p2.b
+; CHECK-NEXT: sel p1.b, p1, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %not.b = xor <vscale x 2 x i1> %b, splat (i1 true)
+ %op = or <vscale x 2 x i1> %a, %not.b
+ %res = and <vscale x 2 x i1> %pg, %op
+ ret <vscale x 2 x i1> %res
+}
+
+define <vscale x 1 x i1> @and_orn_nxv1i1(<vscale x 1 x i1> %pg, <vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
+; CHECK-LABEL: and_orn_nxv1i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: addvl sp, sp, #-1
+; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill
+; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG
+; CHECK-NEXT: .cfi_offset w29, -16
+; CHECK-NEXT: ptrue p3.d
+; CHECK-NEXT: punpklo p4.h, p3.b
+; CHECK-NEXT: eor p2.b, p3/z, p2.b, p4.b
+; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload
+; CHECK-NEXT: sel p1.b, p1, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: addvl sp, sp, #1
+; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
+ %not.b = xor <vscale x 1 x i1> %b, splat (i1 true)
+ %op = or <vscale x 1 x i1> %a, %not.b
+ %res = and <vscale x 1 x i1> %pg, %op
+ ret <vscale x 1 x i1> %res
+}
+
+define <vscale x 16 x i1> @and_orr_nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: and_orr_nxv16i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel p1.b, p1, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %op = or <vscale x 16 x i1> %a, %b
+ %res = and <vscale x 16 x i1> %pg, %op
+ ret <vscale x 16 x i1> %res
+}
+
+define <vscale x 8 x i1> @and_orr_nxv8i1(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
+; CHECK-LABEL: and_orr_nxv8i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel p1.b, p1, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %op = or <vscale x 8 x i1> %a, %b
+ %res = and <vscale x 8 x i1> %pg, %op
+ ret <vscale x 8 x i1> %res
+}
+
+define <vscale x 4 x i1> @and_orr_nxv4i1(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
+; CHECK-LABEL: and_orr_nxv4i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel p1.b, p1, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %op = or <vscale x 4 x i1> %a, %b
+ %res = and <vscale x 4 x i1> %pg, %op
+ ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 2 x i1> @and_orr_nxv2i1(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
+; CHECK-LABEL: and_orr_nxv2i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel p1.b, p1, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %op = or <vscale x 2 x i1> %a, %b
+ %res = and <vscale x 2 x i1> %pg, %op
+ ret <vscale x 2 x i1> %res
+}
+
+define <vscale x 1 x i1> @and_orr_nxv1i1(<vscale x 1 x i1> %pg, <vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
+; CHECK-LABEL: and_orr_nxv1i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel p1.b, p1, p1.b, p2.b
+; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %op = or <vscale x 1 x i1> %a, %b
+ %res = and <vscale x 1 x i1> %pg, %op
+ ret <vscale x 1 x i1> %res
+}
+
+define <vscale x 16 x i1> @and_nand_nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: and_nand_nxv16i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and p2.b, p1/z, p1.b, p2.b
+; CHECK-NEXT: bic p0.b, p0/z, p0.b, p2.b
+; CHECK-NEXT: ret
+ %and = and <vscale x 16 x i1> %a, %b
+ %op = xor <vscale x 16 x i1> %and, splat (i1 true)
+ %res = and <vscale x 16 x i1> %pg, %op
+ ret <vscale x 16 x i1> %res
+}
+
+define <vscale x 8 x i1> @and_nand_nxv8i1(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
+; CHECK-LABEL: and_nand_nxv8i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and p2.b, p1/z, p1.b, p2.b
+; CHECK-NEXT: bic p0.b, p0/z, p0.b, p2.b
+; CHECK-NEXT: ret
+ %and = and <vscale x 8 x i1> %a, %b
+ %op = xor <vscale x 8 x i1> %and, splat (i1 true)
+ %res = and <vscale x 8 x i1> %pg, %op
+ ret <vscale x 8 x i1> %res
+}
+
+define <vscale x 4 x i1> @and_nand_nxv4i1(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
+; CHECK-LABEL: and_nand_nxv4i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and p2.b, p1/z, p1.b, p2.b
+; CHECK-NEXT: bic p0.b, p0/z, p0.b, p2.b
+; CHECK-NEXT: ret
+ %and = and <vscale x 4 x i1> %a, %b
+ %op = xor <vscale x 4 x i1> %and, splat (i1 true)
+ %res = and <vscale x 4 x i1> %pg, %op
+ ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 2 x i1> @and_nand_nxv2i1(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
+; CHECK-LABEL: and_nand_nxv2i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and p2.b, p1/z, p1.b, p2.b
+; CHECK-NEXT: bic p0.b, p0/z, p0.b, p2.b
+; CHECK-NEXT: ret
+ %and = and <vscale x 2 x i1> %a, %b
+ %op = xor <vscale x 2 x i1> %and, splat (i1 true)
+ %res = and <vscale x 2 x i1> %pg, %op
+ ret <vscale x 2 x i1> %res
+}
+
+define <vscale x 1 x i1> @and_nand_nxv1i1(<vscale x 1 x i1> %pg, <vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
+; CHECK-LABEL: and_nand_nxv1i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and p2.b, p1/z, p1.b, p2.b
+; CHECK-NEXT: bic p0.b, p0/z, p0.b, p2.b
+; CHECK-NEXT: ret
+ %and = and <vscale x 1 x i1> %a, %b
+ %op = xor <vscale x 1 x i1> %and, splat (i1 true)
+ %res = and <vscale x 1 x i1> %pg, %op
+ ret <vscale x 1 x i1> %res
+}
+
+define <vscale x 16 x i1> @and_nor_nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: and_nor_nxv16i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel p1.b, p1, p1.b, p2.b
+; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %or = or <vscale x 16 x i1> %a, %b
+ %op = xor <vscale x 16 x i1> %or, splat (i1 true)
+ %res = and <vscale x 16 x i1> %pg, %op
+ ret <vscale x 16 x i1> %res
+}
+
+define <vscale x 8 x i1> @and_nor_nxv8i1(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
+; CHECK-LABEL: and_nor_nxv8i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel p1.b, p1, p1.b, p2.b
+; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %or = or <vscale x 8 x i1> %a, %b
+ %op = xor <vscale x 8 x i1> %or, splat (i1 true)
+ %res = and <vscale x 8 x i1> %pg, %op
+ ret <vscale x 8 x i1> %res
+}
+
+define <vscale x 4 x i1> @and_nor_nxv4i1(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
+; CHECK-LABEL: and_nor_nxv4i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel p1.b, p1, p1.b, p2.b
+; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %or = or <vscale x 4 x i1> %a, %b
+ %op = xor <vscale x 4 x i1> %or, splat (i1 true)
+ %res = and <vscale x 4 x i1> %pg, %op
+ ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 2 x i1> @and_nor_nxv2i1(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
+; CHECK-LABEL: and_nor_nxv2i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel p1.b, p1, p1.b, p2.b
+; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %or = or <vscale x 2 x i1> %a, %b
+ %op = xor <vscale x 2 x i1> %or, splat (i1 true)
+ %res = and <vscale x 2 x i1> %pg, %op
+ ret <vscale x 2 x i1> %res
+}
+
+define <vscale x 1 x i1> @and_nor_nxv1i1(<vscale x 1 x i1> %pg, <vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
+; CHECK-LABEL: and_nor_nxv1i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel p1.b, p1, p1.b, p2.b
+; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %or = or <vscale x 1 x i1> %a, %b
+ %op = xor <vscale x 1 x i1> %or, splat (i1 true)
+ %res = and <vscale x 1 x i1> %pg, %op
+ ret <vscale x 1 x i1> %res
+}
+
+define <vscale x 16 x i1> @bic_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: bic_nxv16i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %not.b = xor <vscale x 16 x i1> %b, splat (i1 true)
+ %res = and <vscale x 16 x i1> %a, %not.b
+ ret <vscale x 16 x i1> %res
+}
+
+define <vscale x 8 x i1> @bic_nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
+; CHECK-LABEL: bic_nxv8i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %not.b = xor <vscale x 8 x i1> %b, splat (i1 true)
+ %res = and <vscale x 8 x i1> %a, %not.b
+ ret <vscale x 8 x i1> %res
+}
+
+define <vscale x 4 x i1> @bic_nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
+; CHECK-LABEL: bic_nxv4i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %not.b = xor <vscale x 4 x i1> %b, splat (i1 true)
+ %res = and <vscale x 4 x i1> %a, %not.b
+ ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 2 x i1> @bic_nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
+; CHECK-LABEL: bic_nxv2i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %not.b = xor <vscale x 2 x i1> %b, splat (i1 true)
+ %res = and <vscale x 2 x i1> %a, %not.b
+ ret <vscale x 2 x i1> %res
+}
+
+define <vscale x 1 x i1> @bic_nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
+; CHECK-LABEL: bic_nxv1i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %not.b = xor <vscale x 1 x i1> %b, splat (i1 true)
+ %res = and <vscale x 1 x i1> %a, %not.b
+ ret <vscale x 1 x i1> %res
+}
+
+define <vscale x 16 x i1> @eor_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: eor_nxv16i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p2.b
+; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %res = xor <vscale x 16 x i1> %a, %b
+ ret <vscale x 16 x i1> %res
+}
+
+define <vscale x 8 x i1> @eor_nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
+; CHECK-LABEL: eor_nxv8i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p2.h
+; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %res = xor <vscale x 8 x i1> %a, %b
+ ret <vscale x 8 x i1> %res
+}
+
+define <vscale x 4 x i1> @eor_nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
+; CHECK-LABEL: eor_nxv4i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p2.s
+; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %res = xor <vscale x 4 x i1> %a, %b
+ ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 2 x i1> @eor_nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
+; CHECK-LABEL: eor_nxv2i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p2.d
+; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %res = xor <vscale x 2 x i1> %a, %b
+ ret <vscale x 2 x i1> %res
+}
+
+define <vscale x 1 x i1> @eor_nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
+; CHECK-LABEL: eor_nxv1i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p2.d
+; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %res = xor <vscale x 1 x i1> %a, %b
+ ret <vscale x 1 x i1> %res
+}
+
+define <vscale x 16 x i1> @orn_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: orn_nxv16i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p2.b
+; CHECK-NEXT: not p1.b, p2/z, p1.b
+; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
+; CHECK-NEXT: ret
+ %not.b = xor <vscale x 16 x i1> %b, splat (i1 true)
+ %res = or <vscale x 16 x i1> %a, %not.b
+ ret <vscale x 16 x i1> %res
+}
+
+define <vscale x 8 x i1> @orn_nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
+; CHECK-LABEL: orn_nxv8i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p2.h
+; CHECK-NEXT: not p1.b, p2/z, p1.b
+; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
+; CHECK-NEXT: ret
+ %not.b = xor <vscale x 8 x i1> %b, splat (i1 true)
+ %res = or <vscale x 8 x i1> %a, %not.b
+ ret <vscale x 8 x i1> %res
+}
+
+define <vscale x 4 x i1> @orn_nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
+; CHECK-LABEL: orn_nxv4i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p2.s
+; CHECK-NEXT: not p1.b, p2/z, p1.b
+; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
+; CHECK-NEXT: ret
+ %not.b = xor <vscale x 4 x i1> %b, splat (i1 true)
+ %res = or <vscale x 4 x i1> %a, %not.b
+ ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 2 x i1> @orn_nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
+; CHECK-LABEL: orn_nxv2i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p2.d
+; CHECK-NEXT: not p1.b, p2/z, p1.b
+; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
+; CHECK-NEXT: ret
+ %not.b = xor <vscale x 2 x i1> %b, splat (i1 true)
+ %res = or <vscale x 2 x i1> %a, %not.b
+ ret <vscale x 2 x i1> %res
+}
+
+define <vscale x 1 x i1> @orn_nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
+; CHECK-LABEL: orn_nxv1i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p2.d
+; CHECK-NEXT: punpklo p3.h, p2.b
+; CHECK-NEXT: eor p1.b, p2/z, p1.b, p3.b
+; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
+; CHECK-NEXT: ret
+ %not.b = xor <vscale x 1 x i1> %b, splat (i1 true)
+ %res = or <vscale x 1 x i1> %a, %not.b
+ ret <vscale x 1 x i1> %res
+}
+
+define <vscale x 16 x i1> @orr_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: orr_nxv16i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
+; CHECK-NEXT: ret
+ %res = or <vscale x 16 x i1> %a, %b
+ ret <vscale x 16 x i1> %res
+}
+
+define <vscale x 8 x i1> @orr_nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
+; CHECK-LABEL: orr_nxv8i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
+; CHECK-NEXT: ret
+ %res = or <vscale x 8 x i1> %a, %b
+ ret <vscale x 8 x i1> %res
+}
+
+define <vscale x 4 x i1> @orr_nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
+; CHECK-LABEL: orr_nxv4i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
+; CHECK-NEXT: ret
+ %res = or <vscale x 4 x i1> %a, %b
+ ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 2 x i1> @orr_nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
+; CHECK-LABEL: orr_nxv2i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
+; CHECK-NEXT: ret
+ %res = or <vscale x 2 x i1> %a, %b
+ ret <vscale x 2 x i1> %res
+}
+
+define <vscale x 1 x i1> @orr_nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
+; CHECK-LABEL: orr_nxv1i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
+; CHECK-NEXT: ret
+ %res = or <vscale x 1 x i1> %a, %b
+ ret <vscale x 1 x i1> %res
+}
+
+define <vscale x 16 x i1> @nand_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: nand_nxv16i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p2.b
+; CHECK-NEXT: and p1.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: not p0.b, p2/z, p1.b
+; CHECK-NEXT: ret
+ %and = and <vscale x 16 x i1> %a, %b
+ %res = xor <vscale x 16 x i1> %and, splat (i1 true)
+ ret <vscale x 16 x i1> %res
+}
+
+define <vscale x 8 x i1> @nand_nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
+; CHECK-LABEL: nand_nxv8i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p2.h
+; CHECK-NEXT: and p1.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: not p0.b, p2/z, p1.b
+; CHECK-NEXT: ret
+ %and = and <vscale x 8 x i1> %a, %b
+ %res = xor <vscale x 8 x i1> %and, splat (i1 true)
+ ret <vscale x 8 x i1> %res
+}
+
+define <vscale x 4 x i1> @nand_nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
+; CHECK-LABEL: nand_nxv4i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p2.s
+; CHECK-NEXT: and p1.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: not p0.b, p2/z, p1.b
+; CHECK-NEXT: ret
+ %and = and <vscale x 4 x i1> %a, %b
+ %res = xor <vscale x 4 x i1> %and, splat (i1 true)
+ ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 2 x i1> @nand_nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
+; CHECK-LABEL: nand_nxv2i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p2.d
+; CHECK-NEXT: and p1.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: not p0.b, p2/z, p1.b
+; CHECK-NEXT: ret
+ %and = and <vscale x 2 x i1> %a, %b
+ %res = xor <vscale x 2 x i1> %and, splat (i1 true)
+ ret <vscale x 2 x i1> %res
+}
+
+define <vscale x 1 x i1> @nand_nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
+; CHECK-LABEL: nand_nxv1i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p2.d
+; CHECK-NEXT: and p1.b, p0/z, p0.b, p1.b
+; CHECK-NEXT: punpklo p0.h, p2.b
+; CHECK-NEXT: eor p0.b, p2/z, p1.b, p0.b
+; CHECK-NEXT: ret
+ %and = and <vscale x 1 x i1> %a, %b
+ %res = xor <vscale x 1 x i1> %and, splat (i1 true)
+ ret <vscale x 1 x i1> %res
+}
+
+define <vscale x 16 x i1> @nor_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: nor_nxv16i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p2.b
+; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
+; CHECK-NEXT: not p0.b, p2/z, p0.b
+; CHECK-NEXT: ret
+ %or = or <vscale x 16 x i1> %a, %b
+ %res = xor <vscale x 16 x i1> %or, splat (i1 true)
+ ret <vscale x 16 x i1> %res
+}
+
+define <vscale x 8 x i1> @nor_nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
+; CHECK-LABEL: nor_nxv8i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p2.h
+; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
+; CHECK-NEXT: not p0.b, p2/z, p0.b
+; CHECK-NEXT: ret
+ %or = or <vscale x 8 x i1> %a, %b
+ %res = xor <vscale x 8 x i1> %or, splat (i1 true)
+ ret <vscale x 8 x i1> %res
+}
+
+define <vscale x 4 x i1> @nor_nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
+; CHECK-LABEL: nor_nxv4i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p2.s
+; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
+; CHECK-NEXT: not p0.b, p2/z, p0.b
+; CHECK-NEXT: ret
+ %or = or <vscale x 4 x i1> %a, %b
+ %res = xor <vscale x 4 x i1> %or, splat (i1 true)
+ ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 2 x i1> @nor_nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
+; CHECK-LABEL: nor_nxv2i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p2.d
+; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
+; CHECK-NEXT: not p0.b, p2/z, p0.b
+; CHECK-NEXT: ret
+ %or = or <vscale x 2 x i1> %a, %b
+ %res = xor <vscale x 2 x i1> %or, splat (i1 true)
+ ret <vscale x 2 x i1> %res
+}
+
+define <vscale x 1 x i1> @nor_nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
+; CHECK-LABEL: nor_nxv1i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p2.d
+; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
+; CHECK-NEXT: punpklo p1.h, p2.b
+; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b
+; CHECK-NEXT: ret
+ %or = or <vscale x 1 x i1> %a, %b
+ %res = xor <vscale x 1 x i1> %or, splat (i1 true)
+ ret <vscale x 1 x i1> %res
+}
+
+define <vscale x 16 x i1> @not_nxv16i1(<vscale x 16 x i1> %a) {
+; CHECK-LABEL: not_nxv16i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p1.b
+; CHECK-NEXT: not p0.b, p1/z, p0.b
+; CHECK-NEXT: ret
+ %res = xor <vscale x 16 x i1> %a, splat (i1 true)
+ ret <vscale x 16 x i1> %res
+}
+
+define <vscale x 8 x i1> @not_nxv8i1(<vscale x 8 x i1> %a) {
+; CHECK-LABEL: not_nxv8i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p1.h
+; CHECK-NEXT: not p0.b, p1/z, p0.b
+; CHECK-NEXT: ret
+ %res = xor <vscale x 8 x i1> %a, splat (i1 true)
+ ret <vscale x 8 x i1> %res
+}
+
+define <vscale x 4 x i1> @not_nxv4i1(<vscale x 4 x i1> %a) {
+; CHECK-LABEL: not_nxv4i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p1.s
+; CHECK-NEXT: not p0.b, p1/z, p0.b
+; CHECK-NEXT: ret
+ %res = xor <vscale x 4 x i1> %a, splat (i1 true)
+ ret <vscale x 4 x i1> %res
+}
+
+define <vscale x 2 x i1> @not_nxv2i1(<vscale x 2 x i1> %a) {
+; CHECK-LABEL: not_nxv2i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p1.d
+; CHECK-NEXT: not p0.b, p1/z, p0.b
+; CHECK-NEXT: ret
+ %res = xor <vscale x 2 x i1> %a, splat (i1 true)
+ ret <vscale x 2 x i1> %res
+}
+
+define <vscale x 1 x i1> @not_nxv1i1(<vscale x 1 x i1> %a) {
+; CHECK-LABEL: not_nxv1i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p1.d
+; CHECK-NEXT: punpklo p2.h, p1.b
+; CHECK-NEXT: eor p0.b, p1/z, p0.b, p2.b
+; CHECK-NEXT: ret
+ %res = xor <vscale x 1 x i1> %a, splat (i1 true)
+ ret <vscale x 1 x i1> %res
}
-
-define <vscale x 4 x i1> @bic_4(<vscale x 4 x i1> %Pg, <vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd) {
-; CHECK-LABEL: bic_4:
-; CHECK: bic p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 4 x i1> @llvm.aarch64.sve.bic.z.nxv4i1(<vscale x 4 x i1> %Pg, <vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd)
- ret <vscale x 4 x i1> %res;
-}
-
-define <vscale x 2 x i1> @bic_2(<vscale x 2 x i1> %Pg, <vscale x 2 x i1> %Pn, <vscale x 2 x i1> %Pd) {
-; CHECK-LABEL: bic_2:
-; CHECK: bic p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 2 x i1> @llvm.aarch64.sve.bic.z.nxv2i1(<vscale x 2 x i1> %Pg, <vscale x 2 x i1> %Pn, <vscale x 2 x i1> %Pd)
- ret <vscale x 2 x i1> %res;
-}
-
-define <vscale x 16 x i1> @eor_16(<vscale x 16 x i1> %Pg, <vscale x 16 x i1> %Pn, <vscale x 16 x i1> %Pd) {
-; CHECK-LABEL: eor_16:
-; CHECK: eor p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 16 x i1> @llvm.aarch64.sve.eor.z.nxv16i1(<vscale x 16 x i1> %Pg, <vscale x 16 x i1> %Pn, <vscale x 16 x i1> %Pd)
- ret <vscale x 16 x i1> %res;
-}
-
-define <vscale x 8 x i1> @eor_8(<vscale x 8 x i1> %Pg, <vscale x 8 x i1> %Pn, <vscale x 8 x i1> %Pd) {
-; CHECK-LABEL: eor_8:
-; CHECK: eor p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 8 x i1> @llvm.aarch64.sve.eor.z.nxv8i1(<vscale x 8 x i1> %Pg, <vscale x 8 x i1> %Pn, <vscale x 8 x i1> %Pd)
- ret <vscale x 8 x i1> %res;
-}
-
-define <vscale x 4 x i1> @eor_4(<vscale x 4 x i1> %Pg, <vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd) {
-; CHECK-LABEL: eor_4:
-; CHECK: eor p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 4 x i1> @llvm.aarch64.sve.eor.z.nxv4i1(<vscale x 4 x i1> %Pg, <vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd)
- ret <vscale x 4 x i1> %res;
-}
-
-define <vscale x 2 x i1> @eor_2(<vscale x 2 x i1> %Pg, <vscale x 2 x i1> %Pn, <vscale x 2 x i1> %Pd) {
-; CHECK-LABEL: eor_2:
-; CHECK: eor p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 2 x i1> @llvm.aarch64.sve.eor.z.nxv2i1(<vscale x 2 x i1> %Pg, <vscale x 2 x i1> %Pn, <vscale x 2 x i1> %Pd)
- ret <vscale x 2 x i1> %res;
-}
-
-define <vscale x 16 x i1> @orr_16(<vscale x 16 x i1> %Pg, <vscale x 16 x i1> %Pn, <vscale x 16 x i1> %Pd) {
-; CHECK-LABEL: orr_16:
-; CHECK: orr p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 16 x i1> @llvm.aarch64.sve.orr.z.nxv16i1(<vscale x 16 x i1> %Pg, <vscale x 16 x i1> %Pn, <vscale x 16 x i1> %Pd)
- ret <vscale x 16 x i1> %res;
-}
-
-define <vscale x 8 x i1> @orr_8(<vscale x 8 x i1> %Pg, <vscale x 8 x i1> %Pn, <vscale x 8 x i1> %Pd) {
-; CHECK-LABEL: orr_8:
-; CHECK: orr p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 8 x i1> @llvm.aarch64.sve.orr.z.nxv8i1(<vscale x 8 x i1> %Pg, <vscale x 8 x i1> %Pn, <vscale x 8 x i1> %Pd)
- ret <vscale x 8 x i1> %res;
-}
-
-define <vscale x 4 x i1> @orr_4(<vscale x 4 x i1> %Pg, <vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd) {
-; CHECK-LABEL: orr_4:
-; CHECK: orr p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 4 x i1> @llvm.aarch64.sve.orr.z.nxv4i1(<vscale x 4 x i1> %Pg, <vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd)
- ret <vscale x 4 x i1> %res;
-}
-
-define <vscale x 2 x i1> @orr_2(<vscale x 2 x i1> %Pg, <vscale x 2 x i1> %Pn, <vscale x 2 x i1> %Pd) {
-; CHECK-LABEL: orr_2:
-; CHECK: orr p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 2 x i1> @llvm.aarch64.sve.orr.z.nxv2i1(<vscale x 2 x i1> %Pg, <vscale x 2 x i1> %Pn, <vscale x 2 x i1> %Pd)
- ret <vscale x 2 x i1> %res;
-}
-
-define <vscale x 16 x i1> @orn_16(<vscale x 16 x i1> %Pg, <vscale x 16 x i1> %Pn, <vscale x 16 x i1> %Pd) {
-; CHECK-LABEL: orn_16:
-; CHECK: orn p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 16 x i1> @llvm.aarch64.sve.orn.z.nxv16i1(<vscale x 16 x i1> %Pg, <vscale x 16 x i1> %Pn, <vscale x 16 x i1> %Pd)
- ret <vscale x 16 x i1> %res;
-}
-
-define <vscale x 8 x i1> @orn_8(<vscale x 8 x i1> %Pg, <vscale x 8 x i1> %Pn, <vscale x 8 x i1> %Pd) {
-; CHECK-LABEL: orn_8:
-; CHECK: orn p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 8 x i1> @llvm.aarch64.sve.orn.z.nxv8i1(<vscale x 8 x i1> %Pg, <vscale x 8 x i1> %Pn, <vscale x 8 x i1> %Pd)
- ret <vscale x 8 x i1> %res;
-}
-
-define <vscale x 4 x i1> @orn_4(<vscale x 4 x i1> %Pg, <vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd) {
-; CHECK-LABEL: orn_4:
-; CHECK: orn p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 4 x i1> @llvm.aarch64.sve.orn.z.nxv4i1(<vscale x 4 x i1> %Pg, <vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd)
- ret <vscale x 4 x i1> %res;
-}
-
-define <vscale x 2 x i1> @orn_2(<vscale x 2 x i1> %Pg, <vscale x 2 x i1> %Pn, <vscale x 2 x i1> %Pd) {
-; CHECK-LABEL: orn_2:
-; CHECK: orn p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 2 x i1> @llvm.aarch64.sve.orn.z.nxv2i1(<vscale x 2 x i1> %Pg, <vscale x 2 x i1> %Pn, <vscale x 2 x i1> %Pd)
- ret <vscale x 2 x i1> %res;
-}
-
-define <vscale x 16 x i1> @nor_16(<vscale x 16 x i1> %Pg, <vscale x 16 x i1> %Pn, <vscale x 16 x i1> %Pd) {
-; CHECK-LABEL: nor_16:
-; CHECK: nor p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 16 x i1> @llvm.aarch64.sve.nor.z.nxv16i1(<vscale x 16 x i1> %Pg, <vscale x 16 x i1> %Pn, <vscale x 16 x i1> %Pd)
- ret <vscale x 16 x i1> %res;
-}
-
-define <vscale x 8 x i1> @nor_8(<vscale x 8 x i1> %Pg, <vscale x 8 x i1> %Pn, <vscale x 8 x i1> %Pd) {
-; CHECK-LABEL: nor_8:
-; CHECK: nor p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 8 x i1> @llvm.aarch64.sve.nor.z.nxv8i1(<vscale x 8 x i1> %Pg, <vscale x 8 x i1> %Pn, <vscale x 8 x i1> %Pd)
- ret <vscale x 8 x i1> %res;
-}
-
-define <vscale x 4 x i1> @nor_4(<vscale x 4 x i1> %Pg, <vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd) {
-; CHECK-LABEL: nor_4:
-; CHECK: nor p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 4 x i1> @llvm.aarch64.sve.nor.z.nxv4i1(<vscale x 4 x i1> %Pg, <vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd)
- ret <vscale x 4 x i1> %res;
-}
-
-define <vscale x 2 x i1> @nor_2(<vscale x 2 x i1> %Pg, <vscale x 2 x i1> %Pn, <vscale x 2 x i1> %Pd) {
-; CHECK-LABEL: nor_2:
-; CHECK: nor p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 2 x i1> @llvm.aarch64.sve.nor.z.nxv2i1(<vscale x 2 x i1> %Pg, <vscale x 2 x i1> %Pn, <vscale x 2 x i1> %Pd)
- ret <vscale x 2 x i1> %res;
-}
-
-define <vscale x 16 x i1> @nand_16(<vscale x 16 x i1> %Pg, <vscale x 16 x i1> %Pn, <vscale x 16 x i1> %Pd) {
-; CHECK-LABEL: nand_16:
-; CHECK: nand p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 16 x i1> @llvm.aarch64.sve.nand.z.nxv16i1(<vscale x 16 x i1> %Pg, <vscale x 16 x i1> %Pn, <vscale x 16 x i1> %Pd)
- ret <vscale x 16 x i1> %res;
-}
-
-define <vscale x 8 x i1> @nand_8(<vscale x 8 x i1> %Pg, <vscale x 8 x i1> %Pn, <vscale x 8 x i1> %Pd) {
-; CHECK-LABEL: nand_8:
-; CHECK: nand p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 8 x i1> @llvm.aarch64.sve.nand.z.nxv8i1(<vscale x 8 x i1> %Pg, <vscale x 8 x i1> %Pn, <vscale x 8 x i1> %Pd)
- ret <vscale x 8 x i1> %res;
-}
-
-define <vscale x 4 x i1> @nand_4(<vscale x 4 x i1> %Pg, <vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd) {
-; CHECK-LABEL: nand_4:
-; CHECK: nand p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 4 x i1> @llvm.aarch64.sve.nand.z.nxv4i1(<vscale x 4 x i1> %Pg, <vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd)
- ret <vscale x 4 x i1> %res;
-}
-
-define <vscale x 2 x i1> @nand_2(<vscale x 2 x i1> %Pg, <vscale x 2 x i1> %Pn, <vscale x 2 x i1> %Pd) {
-; CHECK-LABEL: nand_2:
-; CHECK: nand p0.b, p0/z, p1.b, p2.b
-; CHECK-NEXT: ret
- %res = call <vscale x 2 x i1> @llvm.aarch64.sve.nand.z.nxv2i1(<vscale x 2 x i1> %Pg, <vscale x 2 x i1> %Pn, <vscale x 2 x i1> %Pd)
- ret <vscale x 2 x i1> %res;
-}
-
-declare <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
-declare <vscale x 8 x i1> @llvm.aarch64.sve.and.z.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>)
-declare <vscale x 4 x i1> @llvm.aarch64.sve.and.z.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>)
-declare <vscale x 2 x i1> @llvm.aarch64.sve.and.z.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>)
-declare <vscale x 16 x i1> @llvm.aarch64.sve.bic.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
-declare <vscale x 8 x i1> @llvm.aarch64.sve.bic.z.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>)
-declare <vscale x 4 x i1> @llvm.aarch64.sve.bic.z.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>)
-declare <vscale x 2 x i1> @llvm.aarch64.sve.bic.z.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>)
-declare <vscale x 16 x i1> @llvm.aarch64.sve.eor.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
-declare <vscale x 8 x i1> @llvm.aarch64.sve.eor.z.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>)
-declare <vscale x 4 x i1> @llvm.aarch64.sve.eor.z.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>)
-declare <vscale x 2 x i1> @llvm.aarch64.sve.eor.z.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>)
-declare <vscale x 16 x i1> @llvm.aarch64.sve.orr.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
-declare <vscale x 8 x i1> @llvm.aarch64.sve.orr.z.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>)
-declare <vscale x 4 x i1> @llvm.aarch64.sve.orr.z.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>)
-declare <vscale x 2 x i1> @llvm.aarch64.sve.orr.z.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>)
-declare <vscale x 16 x i1> @llvm.aarch64.sve.orn.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
-declare <vscale x 8 x i1> @llvm.aarch64.sve.orn.z.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>)
-declare <vscale x 4 x i1> @llvm.aarch64.sve.orn.z.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>)
-declare <vscale x 2 x i1> @llvm.aarch64.sve.orn.z.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>)
-declare <vscale x 16 x i1> @llvm.aarch64.sve.nor.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
-declare <vscale x 8 x i1> @llvm.aarch64.sve.nor.z.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>)
-declare <vscale x 4 x i1> @llvm.aarch64.sve.nor.z.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>)
-declare <vscale x 2 x i1> @llvm.aarch64.sve.nor.z.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>)
-declare <vscale x 16 x i1> @llvm.aarch64.sve.nand.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
-declare <vscale x 8 x i1> @llvm.aarch64.sve.nand.z.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>)
-declare <vscale x 4 x i1> @llvm.aarch64.sve.nand.z.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>)
-declare <vscale x 2 x i1> @llvm.aarch64.sve.nand.z.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>)
diff --git a/llvm/test/CodeGen/AArch64/sve-select.ll b/llvm/test/CodeGen/AArch64/sve-select.ll
index 513613b741cd4..dc51119239a51 100644
--- a/llvm/test/CodeGen/AArch64/sve-select.ll
+++ b/llvm/test/CodeGen/AArch64/sve-select.ll
@@ -266,92 +266,184 @@ define <vscale x 1 x i1> @select_nxv1i1(i1 %cond, <vscale x 1 x i1> %a, <vscale
ret <vscale x 1 x i1> %res
}
+; Predicate vector select
+
+define <vscale x 16 x i1> @sel_nxv16i1(<vscale x 16 x i1> %cond, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
+; CHECK-LABEL: sel_nxv16i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel p0.b, p0, p1.b, p2.b
+; CHECK-NEXT: ret
+ %res = select <vscale x 16 x i1> %cond, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b
+ ret <vscale x 16 x i1> %res;
+}
+
+define <vscale x 8 x i1> @sel_nxv8i1(<vscale x 8 x i1> %cond, <vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
+; CHECK-LABEL: sel_nxv8i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel p0.b, p0, p1.b, p2.b
+; CHECK-NEXT: ret
+ %res = select <vscale x 8 x i1> %cond, <vscale x 8 x i1> %a, <vscale x 8 x i1> %b
+ ret <vscale x 8 x i1> %res;
+}
+
+define <vscale x 4 x i1> @sel_nxv4i1(<vscale x 4 x i1> %cond, <vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
+; CHECK-LABEL: sel_nxv4i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel p0.b, p0, p1.b, p2.b
+; CHECK-NEXT: ret
+ %res = select <vscale x 4 x i1> %cond, <vscale x 4 x i1> %a, <vscale x 4 x i1> %b
+ ret <vscale x 4 x i1> %res;
+}
+
+define <vscale x 2 x i1> @sel_nxv2i1(<vscale x 2 x i1> %cond, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
+; CHECK-LABEL: sel_nxv2i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel p0.b, p0, p1.b, p2.b
+; CHECK-NEXT: ret
+ %res = select <vscale x 2 x i1> %cond, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b
+ ret <vscale x 2 x i1> %res;
+}
+
+define <vscale x 1 x i1> @sel_nxv1i1(<vscale x 1 x i1> %cond, <vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
+; CHECK-LABEL: sel_nxv1i1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel p0.b, p0, p1.b, p2.b
+; CHECK-NEXT: ret
+ %res = select <vscale x 1 x i1> %cond, <vscale x 1 x i1> %a, <vscale x 1 x i1> %b
+ ret <vscale x 1 x i1> %res;
+}
+
; Integer vector select
-define <vscale x 16 x i8> @sel_nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %dst, <vscale x 16 x i8> %a) {
+define <vscale x 16 x i8> @sel_nxv16i8(<vscale x 16 x i1> %cond, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
; CHECK-LABEL: sel_nxv16i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov z0.b, p0/m, z1.b
+; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b
; CHECK-NEXT: ret
- %sel = select <vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %dst
+ %sel = select <vscale x 16 x i1> %cond, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b
ret <vscale x 16 x i8> %sel
}
-define <vscale x 8 x i16> @sel_nxv8i16(<vscale x 8 x i1> %p, <vscale x 8 x i16> %dst, <vscale x 8 x i16> %a) {
+define <vscale x 8 x i16> @sel_nxv8i16(<vscale x 8 x i1> %cond, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
; CHECK-LABEL: sel_nxv8i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
; CHECK-NEXT: ret
- %sel = select <vscale x 8 x i1> %p, <vscale x 8 x i16> %a, <vscale x 8 x i16> %dst
+ %sel = select <vscale x 8 x i1> %cond, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b
ret <vscale x 8 x i16> %sel
}
-define <vscale x 4 x i32> @sel_nxv4i32(<vscale x 4 x i1> %p, <vscale x 4 x i32> %dst, <vscale x 4 x i32> %a) {
+define <vscale x 4 x i32> @sel_nxv4i32(<vscale x 4 x i1> %cond, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
; CHECK-LABEL: sel_nxv4i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
; CHECK-NEXT: ret
- %sel = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %a, <vscale x 4 x i32> %dst
+ %sel = select <vscale x 4 x i1> %cond, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b
ret <vscale x 4 x i32> %sel
}
-define <vscale x 1 x i64> @sel_nxv1i64(<vscale x 1 x i1> %p, <vscale x 1 x i64> %dst, <vscale x 1 x i64> %a) {
+define <vscale x 1 x i64> @sel_nxv1i64(<vscale x 1 x i1> %cond, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b) {
; CHECK-LABEL: sel_nxv1i64:
; CHECK: // %bb.0:
; CHECK-NEXT: uzp1 p0.d, p0.d, p0.d
-; CHECK-NEXT: mov z0.d, p0/m, z1.d
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
; CHECK-NEXT: ret
- %sel = select <vscale x 1 x i1> %p, <vscale x 1 x i64> %a, <vscale x 1 x i64> %dst
+ %sel = select <vscale x 1 x i1> %cond, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b
ret <vscale x 1 x i64> %sel
}
-define <vscale x 2 x i64> @sel_nxv2i64(<vscale x 2 x i1> %p, <vscale x 2 x i64> %dst, <vscale x 2 x i64> %a) {
+define <vscale x 2 x i64> @sel_nxv2i64(<vscale x 2 x i1> %cond, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
; CHECK-LABEL: sel_nxv2i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov z0.d, p0/m, z1.d
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
; CHECK-NEXT: ret
- %sel = select <vscale x 2 x i1> %p, <vscale x 2 x i64> %a, <vscale x 2 x i64> %dst
+ %sel = select <vscale x 2 x i1> %cond, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b
ret <vscale x 2 x i64> %sel
}
; Floating point vector select
-define <vscale x 8 x half> @sel_nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %dst, <vscale x 8 x half> %a) {
+define <vscale x 8 x half> @sel_nxv8f16(<vscale x 8 x i1> %cond, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
; CHECK-LABEL: sel_nxv8f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
; CHECK-NEXT: ret
- %sel = select <vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %dst
+ %sel = select <vscale x 8 x i1> %cond, <vscale x 8 x half> %a, <vscale x 8 x half> %b
ret <vscale x 8 x half> %sel
}
-define <vscale x 4 x float> @sel_nxv4f32(<vscale x 4 x i1> %p, <vscale x 4 x float> %dst, <vscale x 4 x float> %a) {
+define <vscale x 4 x half> @sel_nxv4f16(<vscale x 4 x i1> %cond, <vscale x 4 x half> %a, <vscale x 4 x half> %b) {
+; CHECK-LABEL: sel_nxv4f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: ret
+ %sel = select <vscale x 4 x i1> %cond, <vscale x 4 x half> %a, <vscale x 4 x half> %b
+ ret <vscale x 4 x half> %sel
+}
+
+define <vscale x 2 x half> @sel_nxv2f16(<vscale x 2 x i1> %cond, <vscale x 2 x half> %a, <vscale x 2 x half> %b) {
+; CHECK-LABEL: sel_nxv2f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+ %sel = select <vscale x 2 x i1> %cond, <vscale x 2 x half> %a, <vscale x 2 x half> %b
+ ret <vscale x 2 x half> %sel
+}
+
+define <vscale x 4 x float> @sel_nxv4f32(<vscale x 4 x i1> %cond, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
; CHECK-LABEL: sel_nxv4f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
; CHECK-NEXT: ret
- %sel = select <vscale x 4 x i1> %p, <vscale x 4 x float> %a, <vscale x 4 x float> %dst
+ %sel = select <vscale x 4 x i1> %cond, <vscale x 4 x float> %a, <vscale x 4 x float> %b
ret <vscale x 4 x float> %sel
}
-define <vscale x 2 x float> @sel_nxv2f32(<vscale x 2 x i1> %p, <vscale x 2 x float> %dst, <vscale x 2 x float> %a) {
+define <vscale x 2 x float> @sel_nxv2f32(<vscale x 2 x i1> %cond, <vscale x 2 x float> %a, <vscale x 2 x float> %b) {
; CHECK-LABEL: sel_nxv2f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov z0.d, p0/m, z1.d
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
; CHECK-NEXT: ret
- %sel = select <vscale x 2 x i1> %p, <vscale x 2 x float> %a, <vscale x 2 x float> %dst
+ %sel = select <vscale x 2 x i1> %cond, <vscale x 2 x float> %a, <vscale x 2 x float> %b
ret <vscale x 2 x float> %sel
}
-define <vscale x 2 x double> @sel_nxv8f64(<vscale x 2 x i1> %p, <vscale x 2 x double> %dst, <vscale x 2 x double> %a) {
-; CHECK-LABEL: sel_nxv8f64:
+define <vscale x 2 x double> @sel_nxv2f64(<vscale x 2 x i1> %cond, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
+; CHECK-LABEL: sel_nxv2f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov z0.d, p0/m, z1.d
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
; CHECK-NEXT: ret
- %sel = select <vscale x 2 x i1> %p, <vscale x 2 x double> %a, <vscale x 2 x double> %dst
+ %sel = select <vscale x 2 x i1> %cond, <vscale x 2 x double> %a, <vscale x 2 x double> %b
ret <vscale x 2 x double> %sel
}
+define <vscale x 8 x bfloat> @sel_nxv8bf16(<vscale x 8 x i1> %cond, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
+; CHECK-LABEL: sel_nxv8bf16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+ %sel = select <vscale x 8 x i1> %cond, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b
+ ret <vscale x 8 x bfloat> %sel
+}
+
+define <vscale x 4 x bfloat> @sel_nxv4bf16(<vscale x 4 x i1> %cond, <vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b) {
+; CHECK-LABEL: sel_nxv4bf16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT: ret
+ %sel = select <vscale x 4 x i1> %cond, <vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b
+ ret <vscale x 4 x bfloat> %sel
+}
+
+define <vscale x 2 x bfloat> @sel_nxv2bf16(<vscale x 2 x i1> %cond, <vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b) {
+; CHECK-LABEL: sel_nxv2bf16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: ret
+ %sel = select <vscale x 2 x i1> %cond, <vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b
+ ret <vscale x 2 x bfloat> %sel
+}
+
; Check icmp+select
define <vscale x 2 x half> @icmp_select_nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i64 %x0) {
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