[llvm] [PeepholeOptimizer] Add REG_SEQUENCE subregister use folding (PR #205795)

[Frederik Harwath via llvm-commits]

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@@ -1739,6 +1764,119 @@ bool PeepholeOptimizerLegacy::runOnMachineFunction(MachineFunction &MF) {
   return Impl.run(MF);
 }
 
+/// Check if a REG_SEQUENCE subregister use can be safely rewritten to use
+/// the source register directly.
+bool PeepholeOptimizer::canRewriteRegSequenceSubRegUse(MachineOperand &UseMO,
+                                                       RegSubRegPair Src) {
+  if (!Src.Reg.isValid() || !Src.Reg.isVirtual())
+    return false;
+
+  MachineInstr *UseMI = UseMO.getParent();
+  Register DstReg = UseMO.getReg();
+
+  // Instructions, e.g. AMDGPU S_MOVRELS_B32, may require specific
+  // subregister relationships with implicit operands. Replacing the
----------------
frederik-h wrote:

If the src0 operand of an `S_MOVRELS_B32` instruction that uses a subregister of a `REG_SEQUENCE ` is replaced by the source of that subregister, the resulting IR fails verification with the error "src0 should be subreg of implicit vector use" which originates from [here ](https://github.com/llvm/llvm-project/blob/c4dafb0c3bda13f40ded1e0f3f018dd5ec529fbb/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp#L5642). Similarly, MIMG instructions can fail with the error "Subtarget requires even aligned vector registers for vaddr operand of image instruction" originating from [here](https://github.com/llvm/llvm-project/blob/c4dafb0c3bda13f40ded1e0f3f018dd5ec529fbb/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp#L5852). Hence, I think it is necessary to keep that check. Perhaps the comment could be improved?

https://github.com/llvm/llvm-project/pull/205795