[llvm] [AMDGPU][GlobalISel] Reduce instruction count for store in global addrspace for non-powers-of-2 (PR #206043)

[Rajveer Singh Bharadwaj via llvm-commits]

Rajveer100 wrote:

> This shouldn't require custom lowering.
> 
> I've complained about this before (and I have a 6 year old branch working on fixing this), but the way we write load and store legalization rules is broken. We're abusing the legality rules for the register type to legalize the memory type. We should simplify the rules here to only specify the actions for the register values. The lower() action in LegalizerHelper should figure out the correct way to break down the memory type into the appropriate set of loads or extending loads

Sounds right, although the `GlobalISel` lowering right now for non-powers of two are quite inefficient generating multiple stores.

Ideally it should be greedily done, for example for `7 x i16` it would be `64+32+16`, but right now more than 3 stores are generated.

Let me know what's the best way.

I thought of unmerging the bits first and then doing a merge for each subsections, like it is right now, it only needs to be generalized.

https://github.com/llvm/llvm-project/pull/206043