[llvm] [WIP][DAG] SimplifyDemandedBits - handle ISD::VSELECT cases where the demanded true/false bits are known (PR #205858)

[Simon Pilgrim via llvm-commits]

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@@ -1586,17 +1586,49 @@ define void @addus_v8i8(ptr %p1, ptr %p2) {
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    movq {{.*#+}} xmm0 = mem[0],zero
 ; SSE-NEXT:    movq {{.*#+}} xmm1 = mem[0],zero
-; SSE-NEXT:    paddusb %xmm0, %xmm1
-; SSE-NEXT:    movq %xmm1, (%rdi)
+; SSE-NEXT:    paddb %xmm0, %xmm1
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RKSimon wrote:

stuck freeze(add()) is preventing the uaddsat match

https://github.com/llvm/llvm-project/pull/205858