[llvm] [AMDGPU] Select the high-half 16-bit packing idiom to v_lshl_or_b32 (PR #206058)
Barbara Mitic via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 26 09:08:36 PDT 2026
https://github.com/barbara-amd updated https://github.com/llvm/llvm-project/pull/206058
>From fd57af92901f4400d43f45da62755b879d6f7fb7 Mon Sep 17 00:00:00 2001
From: Barbara Mitic <Barbara.Mitic at amd.com>
Date: Fri, 26 Jun 2026 12:36:25 +0200
Subject: [PATCH] [AMDGPU] Select the high-half 16-bit packing idiom to
v_lshl_or_b32
The (hi << 16) | z high-half packing idiom is not fused into
v_lshl_or_b32 by the existing (or (shl x, y), z) selection. By the time
it reaches ISel the DAG combiner has rewritten (ext i16) << 16 into
bitcast(build_vector (i16 0), hi), so there is no shl node left to match
and the build_vector and or are selected separately.
Add ISel patterns that match the build_vector form directly and fold it
into v_lshl_or_b32. Both operand orders of the or are handled. On the
non-real-true16 path the high-half source is already a VGPR_32; on the
real-true16 path it is widened from a VGPR_16 with a REG_SEQUENCE. Only
the divergent case is matched; gated on GFX9+, where v_lshl_or_b32 is
available.
---
llvm/lib/Target/AMDGPU/SIInstructions.td | 22 +
.../CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll | 4856 ++++++++---------
.../CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll | 742 ++-
.../CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll | 724 ++-
.../CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll | 1108 ++--
.../CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll | 138 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll | 1952 ++++---
.../CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll | 224 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll | 280 +-
.../CodeGen/AMDGPU/calling-conventions.ll | 255 +-
llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll | 63 +-
.../CodeGen/AMDGPU/float-to-arbitrary-fp.ll | 16 +-
llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll | 169 +-
llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll | 145 +-
llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll | 8 +-
llvm/test/CodeGen/AMDGPU/idot4u.ll | 94 +-
llvm/test/CodeGen/AMDGPU/idot8s.ll | 334 +-
llvm/test/CodeGen/AMDGPU/idot8u.ll | 208 +-
.../AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll | 6 +-
.../CodeGen/AMDGPU/pack-half-to-lshl-or.ll | 109 +
llvm/test/CodeGen/AMDGPU/permute_i8.ll | 397 +-
llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll | 29 +-
llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll | 118 +-
.../test/CodeGen/AMDGPU/vni8-across-blocks.ll | 61 +-
24 files changed, 5926 insertions(+), 6132 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/pack-half-to-lshl-or.ll
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 750cb1973e21f..3710928f6309c 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -4024,6 +4024,28 @@ def : GCNPat <
(v2i16 (V_LSHL_OR_B32_e64 $src1, (i32 16), (i32 (V_AND_B32_e64 (i32 (V_MOV_B32_e32 (i32 0xffff))), $src0))))
>;
+// Fold the (hi << 16) | z high-half packing idiom into v_lshl_or_b32.
+// DAGCombine canonicalizes a 16-bit value shifted into the high half to
+// bitcast(build_vector (i16 0), hi), leaving no shl for the
+// (or (shl x, y), z) selection to match, so match the build_vector directly.
+let True16Predicate = NotUseRealTrue16Insts in
+def : GCNPat <
+ (i32 (DivergentBinFrag<or>
+ (i32 (bitconvert (v2i16 (build_vector (i16 0), (i16 VGPR_32:$src_hi))))),
+ i32:$src2)),
+ (V_LSHL_OR_B32_e64 VGPR_32:$src_hi, (i32 16), VSrc_b32:$src2)
+>;
+
+let True16Predicate = UseRealTrue16Insts in
+def : GCNPat <
+ (i32 (DivergentBinFrag<or>
+ (i32 (bitconvert (v2i16 (build_vector (i16 0), (i16 VGPR_16:$src_hi))))),
+ i32:$src2)),
+ (V_LSHL_OR_B32_e64
+ (i32 (REG_SEQUENCE VGPR_32, VGPR_16:$src_hi, lo16, (i16 (IMPLICIT_DEF)), hi16)),
+ (i32 16), VSrc_b32:$src2)
+>;
+
// With multiple uses of the shift, this will duplicate the shift and
// increase register pressure.
def : GCNPat <
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
index 2d5fc5cf22425..7672755c6b386 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
@@ -14503,14 +14503,14 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:388
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32
@@ -14527,16 +14527,16 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:84
; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:80
; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:76
-; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:72
-; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:68
+; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:72
+; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:68
; GFX9-NEXT: buffer_load_ushort v38, off, s[0:3], s32 offset:64
; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:60
-; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:56
-; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:52
+; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:56
+; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:52
; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:48
; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:44
-; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:40
-; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:36
+; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:40
+; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:36
; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:32
; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:28
; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:24
@@ -14644,31 +14644,31 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:364
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:188
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:360
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:184
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:356
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:180
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:352
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:176
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:348
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:172
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
@@ -14680,13 +14680,13 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:340
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:164
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:336
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:160
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
@@ -14748,8 +14748,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB14_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0xc0c0004
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v10, v55, v32, s6
@@ -14772,19 +14772,19 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s6
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_perm_b32 v16, v43, v16, s6
; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v1, v2, v1, s6
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s6
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
@@ -14847,11 +14847,11 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_perm_b32 v9, v39, v40, s6
; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; GFX9-NEXT: v_perm_b32 v10, v62, v63, s6
+; GFX9-NEXT: v_perm_b32 v10, v63, v62, s6
; GFX9-NEXT: v_lshl_or_b32 v10, v11, 16, v10
-; GFX9-NEXT: v_perm_b32 v11, v59, v54, s6
+; GFX9-NEXT: v_perm_b32 v11, v54, v59, s6
; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
-; GFX9-NEXT: v_perm_b32 v12, v58, v37, s6
+; GFX9-NEXT: v_perm_b32 v12, v37, v58, s6
; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; GFX9-NEXT: v_perm_b32 v13, v47, v52, s6
; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
@@ -14867,12 +14867,12 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr40
-; GFX9-NEXT: ; implicit-def: $vgpr62
; GFX9-NEXT: ; implicit-def: $vgpr63
-; GFX9-NEXT: ; implicit-def: $vgpr59
+; GFX9-NEXT: ; implicit-def: $vgpr62
; GFX9-NEXT: ; implicit-def: $vgpr54
-; GFX9-NEXT: ; implicit-def: $vgpr58
+; GFX9-NEXT: ; implicit-def: $vgpr59
; GFX9-NEXT: ; implicit-def: $vgpr37
+; GFX9-NEXT: ; implicit-def: $vgpr58
; GFX9-NEXT: ; implicit-def: $vgpr47
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr33
@@ -14895,21 +14895,21 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v18, v19, v18, s6
; GFX9-NEXT: v_lshl_or_b32 v17, v18, 16, v17
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v18, v19, v18, s6
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v19, v20, v19, s6
; GFX9-NEXT: v_lshl_or_b32 v18, v19, 16, v18
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v19, v20, v19, s6
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v20, v21, v20, s6
; GFX9-NEXT: v_lshl_or_b32 v19, v20, 16, v19
@@ -15218,23 +15218,22 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB14_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; GFX9-NEXT: s_movk_i32 s6, 0x300
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
@@ -15257,19 +15256,16 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(24)
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: s_waitcnt vmcnt(22)
-; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v8
; GFX9-NEXT: s_waitcnt vmcnt(21)
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v2
; GFX9-NEXT: s_waitcnt vmcnt(20)
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3
-; GFX9-NEXT: s_waitcnt vmcnt(19)
-; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4
+; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v8
; GFX9-NEXT: v_lshlrev_b16_e32 v18, 8, v18
-; GFX9-NEXT: s_waitcnt vmcnt(18)
-; GFX9-NEXT: v_lshlrev_b16_e32 v21, 8, v21
+; GFX9-NEXT: s_waitcnt vmcnt(17)
+; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4
; GFX9-NEXT: s_waitcnt vmcnt(16)
; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v17
; GFX9-NEXT: s_waitcnt vmcnt(15)
@@ -15282,10 +15278,10 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v6
; GFX9-NEXT: s_waitcnt vmcnt(11)
; GFX9-NEXT: v_lshlrev_b16_e32 v20, 8, v20
-; GFX9-NEXT: s_waitcnt vmcnt(10)
-; GFX9-NEXT: v_lshlrev_b16_e32 v22, 8, v22
+; GFX9-NEXT: v_lshlrev_b16_e32 v21, 8, v21
; GFX9-NEXT: s_waitcnt vmcnt(9)
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v7
+; GFX9-NEXT: v_lshlrev_b16_e32 v22, 8, v22
; GFX9-NEXT: s_waitcnt vmcnt(8)
; GFX9-NEXT: v_lshlrev_b16_e32 v23, 8, v23
; GFX9-NEXT: v_lshlrev_b16_e32 v24, 8, v24
@@ -15307,19 +15303,19 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v1, 3, v1
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v2, 3, v2
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v3, 3, v3
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
@@ -15335,8 +15331,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v3, 3, v3
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -15349,8 +15345,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v4, 3, v4
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -15363,8 +15359,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v5, 3, v5
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -15377,8 +15373,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v6, 3, v6
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -15391,8 +15387,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v7, 3, v7
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -15405,72 +15401,72 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v8, 3, v8
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_add_u16_e32 v8, 3, v35
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v42
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 3, v41
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
-; GFX9-NEXT: v_add_u16_sdwa v9, v9, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_add_u16_e32 v9, 3, v39
; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v40
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v10, 3, v55
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
-; GFX9-NEXT: v_add_u16_sdwa v10, v10, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
-; GFX9-NEXT: v_add_u16_e32 v10, 3, v62
-; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v63
+; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; GFX9-NEXT: v_add_u16_e32 v10, 3, v63
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v62
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 3, v61
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
-; GFX9-NEXT: v_add_u16_sdwa v11, v11, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX9-NEXT: v_add_u16_e32 v11, 3, v59
-; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v54
+; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
+; GFX9-NEXT: v_lshl_or_b32 v10, v11, 16, v10
+; GFX9-NEXT: v_add_u16_e32 v11, 3, v54
+; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v59
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v12, 3, v53
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
-; GFX9-NEXT: v_add_u16_sdwa v12, v12, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
-; GFX9-NEXT: v_add_u16_e32 v12, 3, v58
-; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v37
+; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX9-NEXT: v_add_u16_e32 v12, 3, v37
+; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v58
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v13, 3, v57
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
-; GFX9-NEXT: v_add_u16_sdwa v13, v13, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v12, v12, v13
+; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
+; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; GFX9-NEXT: v_add_u16_e32 v13, 3, v47
; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v52
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v14, 3, v51
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
-; GFX9-NEXT: v_add_u16_sdwa v14, v14, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; GFX9-NEXT: v_add_u16_e32 v14, 3, v33
; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v46
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v15, 3, v45
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
-; GFX9-NEXT: v_add_u16_sdwa v15, v15, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v14, v14, v15
+; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
+; GFX9-NEXT: v_lshl_or_b32 v14, v15, 16, v14
; GFX9-NEXT: v_add_u16_e32 v15, 3, v49
; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v44
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v16, 3, v43
; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
-; GFX9-NEXT: v_add_u16_sdwa v16, v16, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v15, v15, v16
+; GFX9-NEXT: v_add_u16_e32 v16, 0x300, v16
+; GFX9-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
@@ -15486,8 +15482,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v17, 3, v17
; GFX9-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v17, v17, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v16, v16, v17
+; GFX9-NEXT: v_add_u16_e32 v17, 0x300, v17
+; GFX9-NEXT: v_lshl_or_b32 v16, v17, 16, v16
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -15500,10 +15496,10 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v18, 3, v18
; GFX9-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v18, v18, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v17, v17, v18
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u16_e32 v18, 0x300, v18
+; GFX9-NEXT: v_lshl_or_b32 v17, v18, 16, v17
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v18, 3, v18
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -15514,22 +15510,22 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v19, 3, v19
; GFX9-NEXT: v_or_b32_sdwa v19, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v19, v19, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v18, v18, v19
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u16_e32 v19, 0x300, v19
+; GFX9-NEXT: v_lshl_or_b32 v18, v19, 16, v18
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v19, 3, v19
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v20, 8, v20
; GFX9-NEXT: v_or_b32_sdwa v19, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v19, 0x300, v19
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v20, 3, v20
; GFX9-NEXT: v_or_b32_sdwa v20, v21, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v20, v20, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v19, v19, v20
+; GFX9-NEXT: v_add_u16_e32 v20, 0x300, v20
+; GFX9-NEXT: v_lshl_or_b32 v19, v20, 16, v19
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -15542,8 +15538,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v21, 3, v21
; GFX9-NEXT: v_or_b32_sdwa v21, v22, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v21, v21, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v20, v20, v21
+; GFX9-NEXT: v_add_u16_e32 v21, 0x300, v21
+; GFX9-NEXT: v_lshl_or_b32 v20, v21, 16, v20
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -15556,8 +15552,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v22, 3, v22
; GFX9-NEXT: v_or_b32_sdwa v22, v23, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v22, v22, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v21, v21, v22
+; GFX9-NEXT: v_add_u16_e32 v22, 0x300, v22
+; GFX9-NEXT: v_lshl_or_b32 v21, v22, 16, v21
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -15570,8 +15566,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v23, 3, v23
; GFX9-NEXT: v_or_b32_sdwa v23, v24, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v23, v23, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v22, v22, v23
+; GFX9-NEXT: v_add_u16_e32 v23, 0x300, v23
+; GFX9-NEXT: v_lshl_or_b32 v22, v23, 16, v22
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -15584,8 +15580,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v24, 3, v24
; GFX9-NEXT: v_or_b32_sdwa v24, v25, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v24, v24, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v23, v23, v24
+; GFX9-NEXT: v_add_u16_e32 v24, 0x300, v24
+; GFX9-NEXT: v_lshl_or_b32 v23, v24, 16, v23
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -15598,8 +15594,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v25, 3, v25
; GFX9-NEXT: v_or_b32_sdwa v25, v26, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v25, v25, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v24, v24, v25
+; GFX9-NEXT: v_add_u16_e32 v25, 0x300, v25
+; GFX9-NEXT: v_lshl_or_b32 v24, v25, 16, v24
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -15612,8 +15608,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v26, 3, v26
; GFX9-NEXT: v_or_b32_sdwa v26, v27, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v26, v26, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v25, v25, v26
+; GFX9-NEXT: v_add_u16_e32 v26, 0x300, v26
+; GFX9-NEXT: v_lshl_or_b32 v25, v26, 16, v25
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -15626,8 +15622,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: v_or_b32_sdwa v27, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v27, v27, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v26, v26, v27
+; GFX9-NEXT: v_add_u16_e32 v27, 0x300, v27
+; GFX9-NEXT: v_lshl_or_b32 v26, v27, 16, v26
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -15640,8 +15636,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v28, 3, v28
; GFX9-NEXT: v_or_b32_sdwa v28, v29, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v28, v28, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v27, v27, v28
+; GFX9-NEXT: v_add_u16_e32 v28, 0x300, v28
+; GFX9-NEXT: v_lshl_or_b32 v27, v28, 16, v27
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -15654,8 +15650,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v29, 3, v29
; GFX9-NEXT: v_or_b32_sdwa v29, v30, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v29, v29, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v28, v28, v29
+; GFX9-NEXT: v_add_u16_e32 v29, 0x300, v29
+; GFX9-NEXT: v_lshl_or_b32 v28, v29, 16, v28
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -15668,8 +15664,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v30, 3, v30
; GFX9-NEXT: v_or_b32_sdwa v30, v31, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v30, v30, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v29, v29, v30
+; GFX9-NEXT: v_add_u16_e32 v30, 0x300, v30
+; GFX9-NEXT: v_lshl_or_b32 v29, v30, 16, v29
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -15682,8 +15678,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v31, 3, v31
; GFX9-NEXT: v_or_b32_sdwa v31, v32, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v31, v31, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v30, v30, v31
+; GFX9-NEXT: v_add_u16_e32 v31, 0x300, v31
+; GFX9-NEXT: v_lshl_or_b32 v30, v31, 16, v30
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -15694,8 +15690,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u16_e32 v32, 3, v36
; GFX9-NEXT: v_or_b32_sdwa v32, v33, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v31, 0x300, v31
-; GFX9-NEXT: v_add_u16_sdwa v32, v32, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v31, v31, v32
+; GFX9-NEXT: v_add_u16_e32 v32, 0x300, v32
+; GFX9-NEXT: v_lshl_or_b32 v31, v32, 16, v31
; GFX9-NEXT: .LBB14_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
@@ -16665,119 +16661,119 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:384
; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:380
-; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:376
-; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:372
-; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:368
-; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:364
+; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:376
+; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:372
+; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:368
+; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:364
; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:360
; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:356
; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:352
; GFX11-FAKE16-NEXT: scratch_load_u16 v112, off, s32 offset:348
-; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:344
-; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:340
-; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:336
-; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:332
-; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:328
-; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:324
-; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32 offset:320
-; GFX11-FAKE16-NEXT: scratch_load_u16 v129, off, s32 offset:316
-; GFX11-FAKE16-NEXT: scratch_load_u16 v128, off, s32 offset:312
+; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:344
+; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:340
+; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:336
+; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:332
+; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:328
+; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32 offset:324
+; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:320
+; GFX11-FAKE16-NEXT: scratch_load_u16 v128, off, s32 offset:316
+; GFX11-FAKE16-NEXT: scratch_load_u16 v129, off, s32 offset:312
; GFX11-FAKE16-NEXT: scratch_load_u16 v130, off, s32 offset:308
; GFX11-FAKE16-NEXT: scratch_load_u16 v131, off, s32 offset:304
; GFX11-FAKE16-NEXT: scratch_load_u16 v133, off, s32 offset:300
-; GFX11-FAKE16-NEXT: scratch_load_u16 v132, off, s32 offset:296
-; GFX11-FAKE16-NEXT: scratch_load_u16 v134, off, s32 offset:292
-; GFX11-FAKE16-NEXT: scratch_load_u16 v135, off, s32 offset:288
-; GFX11-FAKE16-NEXT: scratch_load_u16 v145, off, s32 offset:284
+; GFX11-FAKE16-NEXT: scratch_load_u16 v134, off, s32 offset:296
+; GFX11-FAKE16-NEXT: scratch_load_u16 v145, off, s32 offset:292
+; GFX11-FAKE16-NEXT: scratch_load_u16 v132, off, s32 offset:288
+; GFX11-FAKE16-NEXT: scratch_load_u16 v135, off, s32 offset:284
; GFX11-FAKE16-NEXT: scratch_load_u16 v144, off, s32 offset:280
; GFX11-FAKE16-NEXT: scratch_load_u16 v146, off, s32 offset:276
; GFX11-FAKE16-NEXT: scratch_load_u16 v147, off, s32 offset:272
-; GFX11-FAKE16-NEXT: scratch_load_u16 v148, off, s32 offset:268
-; GFX11-FAKE16-NEXT: scratch_load_u16 v149, off, s32 offset:264
-; GFX11-FAKE16-NEXT: scratch_load_u16 v150, off, s32 offset:260
+; GFX11-FAKE16-NEXT: scratch_load_u16 v149, off, s32 offset:268
+; GFX11-FAKE16-NEXT: scratch_load_u16 v150, off, s32 offset:264
+; GFX11-FAKE16-NEXT: scratch_load_u16 v161, off, s32 offset:260
; GFX11-FAKE16-NEXT: s_clause 0x1f
-; GFX11-FAKE16-NEXT: scratch_load_u16 v151, off, s32 offset:256
-; GFX11-FAKE16-NEXT: scratch_load_u16 v161, off, s32 offset:252
+; GFX11-FAKE16-NEXT: scratch_load_u16 v148, off, s32 offset:256
+; GFX11-FAKE16-NEXT: scratch_load_u16 v151, off, s32 offset:252
; GFX11-FAKE16-NEXT: scratch_load_u16 v160, off, s32 offset:248
-; GFX11-FAKE16-NEXT: scratch_load_u16 v162, off, s32 offset:244
-; GFX11-FAKE16-NEXT: scratch_load_u16 v163, off, s32 offset:240
-; GFX11-FAKE16-NEXT: scratch_load_u16 v165, off, s32 offset:236
-; GFX11-FAKE16-NEXT: scratch_load_u16 v164, off, s32 offset:232
+; GFX11-FAKE16-NEXT: scratch_load_u16 v163, off, s32 offset:244
+; GFX11-FAKE16-NEXT: scratch_load_u16 v162, off, s32 offset:240
+; GFX11-FAKE16-NEXT: scratch_load_u16 v164, off, s32 offset:236
+; GFX11-FAKE16-NEXT: scratch_load_u16 v165, off, s32 offset:232
; GFX11-FAKE16-NEXT: scratch_load_u16 v166, off, s32 offset:228
; GFX11-FAKE16-NEXT: scratch_load_u16 v167, off, s32 offset:224
; GFX11-FAKE16-NEXT: scratch_load_u16 v177, off, s32 offset:220
-; GFX11-FAKE16-NEXT: scratch_load_u16 v176, off, s32 offset:216
-; GFX11-FAKE16-NEXT: scratch_load_u16 v178, off, s32 offset:212
-; GFX11-FAKE16-NEXT: scratch_load_u16 v179, off, s32 offset:208
-; GFX11-FAKE16-NEXT: scratch_load_u16 v181, off, s32 offset:204
-; GFX11-FAKE16-NEXT: scratch_load_u16 v180, off, s32 offset:200
-; GFX11-FAKE16-NEXT: scratch_load_u16 v182, off, s32 offset:196
-; GFX11-FAKE16-NEXT: scratch_load_u16 v183, off, s32 offset:192
+; GFX11-FAKE16-NEXT: scratch_load_u16 v178, off, s32 offset:216
+; GFX11-FAKE16-NEXT: scratch_load_u16 v180, off, s32 offset:212
+; GFX11-FAKE16-NEXT: scratch_load_u16 v176, off, s32 offset:208
+; GFX11-FAKE16-NEXT: scratch_load_u16 v179, off, s32 offset:204
+; GFX11-FAKE16-NEXT: scratch_load_u16 v181, off, s32 offset:200
+; GFX11-FAKE16-NEXT: scratch_load_u16 v183, off, s32 offset:196
+; GFX11-FAKE16-NEXT: scratch_load_u16 v182, off, s32 offset:192
; GFX11-FAKE16-NEXT: scratch_load_u16 v40, off, s32 offset:188
; GFX11-FAKE16-NEXT: scratch_load_u16 v41, off, s32 offset:184
; GFX11-FAKE16-NEXT: scratch_load_u16 v42, off, s32 offset:180
; GFX11-FAKE16-NEXT: scratch_load_u16 v43, off, s32 offset:176
-; GFX11-FAKE16-NEXT: scratch_load_u16 v45, off, s32 offset:172
-; GFX11-FAKE16-NEXT: scratch_load_u16 v44, off, s32 offset:168
-; GFX11-FAKE16-NEXT: scratch_load_u16 v46, off, s32 offset:164
-; GFX11-FAKE16-NEXT: scratch_load_u16 v47, off, s32 offset:160
-; GFX11-FAKE16-NEXT: scratch_load_u16 v57, off, s32 offset:156
-; GFX11-FAKE16-NEXT: scratch_load_u16 v56, off, s32 offset:152
+; GFX11-FAKE16-NEXT: scratch_load_u16 v44, off, s32 offset:172
+; GFX11-FAKE16-NEXT: scratch_load_u16 v45, off, s32 offset:168
+; GFX11-FAKE16-NEXT: scratch_load_u16 v47, off, s32 offset:164
+; GFX11-FAKE16-NEXT: scratch_load_u16 v46, off, s32 offset:160
+; GFX11-FAKE16-NEXT: scratch_load_u16 v56, off, s32 offset:156
+; GFX11-FAKE16-NEXT: scratch_load_u16 v57, off, s32 offset:152
; GFX11-FAKE16-NEXT: scratch_load_u16 v58, off, s32 offset:148
; GFX11-FAKE16-NEXT: scratch_load_u16 v59, off, s32 offset:144
-; GFX11-FAKE16-NEXT: scratch_load_u16 v61, off, s32 offset:140
-; GFX11-FAKE16-NEXT: scratch_load_u16 v60, off, s32 offset:136
+; GFX11-FAKE16-NEXT: scratch_load_u16 v60, off, s32 offset:140
+; GFX11-FAKE16-NEXT: scratch_load_u16 v61, off, s32 offset:136
; GFX11-FAKE16-NEXT: scratch_load_u16 v62, off, s32 offset:132
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_load_u16 v63, off, s32 offset:128
; GFX11-FAKE16-NEXT: scratch_load_u16 v73, off, s32 offset:124
-; GFX11-FAKE16-NEXT: scratch_load_u16 v72, off, s32 offset:120
-; GFX11-FAKE16-NEXT: scratch_load_u16 v74, off, s32 offset:116
-; GFX11-FAKE16-NEXT: scratch_load_u16 v75, off, s32 offset:112
-; GFX11-FAKE16-NEXT: scratch_load_u16 v76, off, s32 offset:108
+; GFX11-FAKE16-NEXT: scratch_load_u16 v74, off, s32 offset:120
+; GFX11-FAKE16-NEXT: scratch_load_u16 v76, off, s32 offset:116
+; GFX11-FAKE16-NEXT: scratch_load_u16 v72, off, s32 offset:112
+; GFX11-FAKE16-NEXT: scratch_load_u16 v75, off, s32 offset:108
; GFX11-FAKE16-NEXT: scratch_load_u16 v77, off, s32 offset:104
; GFX11-FAKE16-NEXT: scratch_load_u16 v78, off, s32 offset:100
; GFX11-FAKE16-NEXT: scratch_load_u16 v79, off, s32 offset:96
; GFX11-FAKE16-NEXT: scratch_load_u16 v89, off, s32 offset:92
-; GFX11-FAKE16-NEXT: scratch_load_u16 v88, off, s32 offset:88
-; GFX11-FAKE16-NEXT: scratch_load_u16 v90, off, s32 offset:84
-; GFX11-FAKE16-NEXT: scratch_load_u16 v91, off, s32 offset:80
-; GFX11-FAKE16-NEXT: scratch_load_u16 v93, off, s32 offset:76
+; GFX11-FAKE16-NEXT: scratch_load_u16 v90, off, s32 offset:88
+; GFX11-FAKE16-NEXT: scratch_load_u16 v93, off, s32 offset:84
+; GFX11-FAKE16-NEXT: scratch_load_u16 v88, off, s32 offset:80
+; GFX11-FAKE16-NEXT: scratch_load_u16 v91, off, s32 offset:76
; GFX11-FAKE16-NEXT: scratch_load_u16 v92, off, s32 offset:72
; GFX11-FAKE16-NEXT: scratch_load_u16 v94, off, s32 offset:68
; GFX11-FAKE16-NEXT: scratch_load_u16 v95, off, s32 offset:64
-; GFX11-FAKE16-NEXT: scratch_load_u16 v105, off, s32 offset:60
-; GFX11-FAKE16-NEXT: scratch_load_u16 v104, off, s32 offset:56
-; GFX11-FAKE16-NEXT: scratch_load_u16 v106, off, s32 offset:52
-; GFX11-FAKE16-NEXT: scratch_load_u16 v107, off, s32 offset:48
-; GFX11-FAKE16-NEXT: scratch_load_u16 v109, off, s32 offset:44
-; GFX11-FAKE16-NEXT: scratch_load_u16 v108, off, s32 offset:40
-; GFX11-FAKE16-NEXT: scratch_load_u16 v110, off, s32 offset:36
-; GFX11-FAKE16-NEXT: scratch_load_u16 v111, off, s32 offset:32
+; GFX11-FAKE16-NEXT: scratch_load_u16 v104, off, s32 offset:60
+; GFX11-FAKE16-NEXT: scratch_load_u16 v105, off, s32 offset:56
+; GFX11-FAKE16-NEXT: scratch_load_u16 v107, off, s32 offset:52
+; GFX11-FAKE16-NEXT: scratch_load_u16 v106, off, s32 offset:48
+; GFX11-FAKE16-NEXT: scratch_load_u16 v108, off, s32 offset:44
+; GFX11-FAKE16-NEXT: scratch_load_u16 v109, off, s32 offset:40
+; GFX11-FAKE16-NEXT: scratch_load_u16 v111, off, s32 offset:36
+; GFX11-FAKE16-NEXT: scratch_load_u16 v110, off, s32 offset:32
; GFX11-FAKE16-NEXT: scratch_load_u16 v120, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_u16 v121, off, s32 offset:24
; GFX11-FAKE16-NEXT: scratch_load_u16 v122, off, s32 offset:20
; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:388
; GFX11-FAKE16-NEXT: scratch_load_u16 v123, off, s32 offset:16
; GFX11-FAKE16-NEXT: scratch_load_u16 v125, off, s32 offset:12
-; GFX11-FAKE16-NEXT: scratch_load_u16 v124, off, s32 offset:8
+; GFX11-FAKE16-NEXT: scratch_load_u16 v126, off, s32 offset:8
; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: scratch_load_u16 v126, off, s32 offset:4
-; GFX11-FAKE16-NEXT: scratch_load_u16 v127, off, s32
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v30 :: v_dual_mov_b32 v32, v29
+; GFX11-FAKE16-NEXT: scratch_load_u16 v127, off, s32 offset:4
+; GFX11-FAKE16-NEXT: scratch_load_u16 v124, off, s32
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v29
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v28 :: v_dual_mov_b32 v35, v27
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v26 :: v_dual_mov_b32 v36, v25
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v24 :: v_dual_mov_b32 v39, v23
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, v22 :: v_dual_mov_b32 v48, v21
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v20 :: v_dual_mov_b32 v51, v19
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v26 :: v_dual_mov_b32 v37, v25
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v24 :: v_dual_mov_b32 v38, v23
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v22 :: v_dual_mov_b32 v49, v21
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v20 :: v_dual_mov_b32 v50, v19
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v18 :: v_dual_mov_b32 v53, v17
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v16 :: v_dual_mov_b32 v55, v15
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v65, v14 :: v_dual_mov_b32 v64, v13
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v12 :: v_dual_mov_b32 v67, v11
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v69, v10 :: v_dual_mov_b32 v68, v9
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v65, v14 :: v_dual_mov_b32 v66, v13
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v69, v12 :: v_dual_mov_b32 v64, v11
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v67, v10 :: v_dual_mov_b32 v68, v9
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v8 :: v_dual_mov_b32 v71, v7
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v6 :: v_dual_mov_b32 v81, v5
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v4 :: v_dual_mov_b32 v83, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v6 :: v_dual_mov_b32 v83, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v5 :: v_dual_mov_b32 v81, v3
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v85, v2 :: v_dual_mov_b32 v84, v1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
@@ -16788,96 +16784,96 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB14_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v86, v84, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v85, v83, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v82, v81, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v80, v71, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v66, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v85, v81, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v83, v80, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v82, v71, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v69, v66, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v65, v55, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v54, v53, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v70, v68, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v69, v67, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v52, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v50, v48, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v49, v39, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v38, v36, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v37, v35, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v67, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v52, v50, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v51, v49, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v48, v38, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v39, v37, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v36, v35, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v7, 16, v6
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v9, 16, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v11, 16, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v34, v32, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v34, v33, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v33, v127, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v126, v124, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v32, v124, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v127, v126, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v125, v123, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v122, v121, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v120, v111, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v110, v108, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v109, v107, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v106, v104, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v105, v95, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v120, v110, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v111, v109, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v108, v106, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v107, v105, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v104, v95, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v10, 16, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v14, 16, v13
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v16, 16, v15
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v94, v92, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v93, v91, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v90, v88, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v91, v88, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v93, v90, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v89, v79, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v78, v77, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v76, v75, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v74, v72, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v75, v72, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v76, v74, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v73, v63, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v62, v60, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v61, v59, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v62, v61, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v60, v59, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v15, 16, v14
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v17, 16, v16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v19, 16, v18
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v21, 16, v20
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v58, v56, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v57, v47, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v46, v44, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v45, v43, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v58, v57, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v56, v46, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v47, v45, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v44, v43, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v42, v41, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v40, v183, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v182, v180, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v181, v179, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v178, v176, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v40, v182, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v183, v181, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v179, v176, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v180, v178, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v177, v167, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v18, 16, v17
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v20, 16, v19
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v22, 16, v21
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v24, 16, v23
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v26, 16, v25
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v166, v164, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v165, v163, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v162, v160, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v161, v151, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v150, v149, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v148, v147, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v166, v165, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v164, v162, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v163, v160, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v151, v148, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v161, v150, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v149, v147, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v146, v144, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v145, v135, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v30, v134, v132, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v135, v132, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v145, v134, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v31, v133, v131, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v23, 16, v22
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v25, 16, v24
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v27, 16, v26
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v29, 16, v28
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v31, 16, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v130, v128, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v129, v119, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v118, v116, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v30, v117, v114, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v115, v113, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v130, v129, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v128, v117, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v119, v118, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v115, v113, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v116, v114, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v32, v112, v102, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v33, v103, v100, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v34, v101, v98, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v35, v99, v96, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v34, v99, v96, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v35, v101, v98, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v36, v97, v87, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v28, 16, v27
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v30, 16, v29
@@ -16887,129 +16883,129 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr124
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr127
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr126
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr124
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr125
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr123
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr122
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr121
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr120
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr111
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr110
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr108
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr111
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr109
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr107
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr108
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr106
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr104
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr107
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr105
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr104
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr95
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr94
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr92
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr93
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr91
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr90
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr88
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr93
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr90
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr89
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr79
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr78
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr77
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr76
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr75
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr74
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr72
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr76
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr74
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr73
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr63
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr62
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr60
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr61
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr60
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr59
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr58
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr56
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr57
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr47
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr56
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr46
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr44
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr47
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr45
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr44
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr43
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr42
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr41
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr40
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr183
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr182
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr180
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr183
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr181
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr179
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr178
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr176
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr180
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr178
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr177
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr167
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr166
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr164
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr165
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr163
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr164
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr162
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr163
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr160
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr161
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr151
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr148
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr161
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr150
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr149
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr148
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr147
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr146
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr144
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr145
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr133
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
; GFX11-FAKE16-NEXT: .LBB14_2: ; %Flow
@@ -17017,422 +17013,392 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB14_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v86, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v83, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v85, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v84
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v83
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v84
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v82, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v80
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v80, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v81
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v81
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v71
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v71
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v6, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v69, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v69, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v70, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v67
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v66
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v65, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v68
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v66, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v54, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v65, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v64
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v68
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v67, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v55
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v64
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v54, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v48, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v39, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v53
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v52, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v51
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v50, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v49, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v39
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v51, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v50
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v48
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v38, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v37, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v49
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v36, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v126
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v38
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v37
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v9, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v36
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v35
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v125, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v35
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v34, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v8
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v127, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v34, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v33, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v32
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v33
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v32, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v127
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v126, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v125, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v8, 16, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v120, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v124
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v123
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v122, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v12, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v13
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v123
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v121
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v122, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v120, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v111
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v110, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v109, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v107
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v108
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v121
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v111, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v107, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v10, 16, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v110
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v106, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v105, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v109
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v108, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v90
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v13, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v106
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v105
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v104
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v95
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v16, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v94, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v104, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v11, 16, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v95
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v94, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v11, 16, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v93, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v92
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v91, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v91
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v90, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v89, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v89, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v17
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v16
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v88
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v79
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v78, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v17, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v18
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v79
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v16, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v18
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v77
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v77
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v18, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v78, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v16
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v76, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v75
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v74, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v73, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v63
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v76, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v13, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v15, 16, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v16, 16, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v75, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v20
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v74
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v73, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v72
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v62, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v18
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v72
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v62, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v61, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v63
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v19, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v61
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v18, v17
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v20
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v60
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v21
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v59
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v60, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v15
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v17
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v21, v20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v16
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v20
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v59
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v58, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v17, 16, v16
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v19
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, v58, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v17, v20
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v57, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v20, v19
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v57
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v56, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v47, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v56
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v47
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v46, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v16, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v45, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v20, v19
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v21, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v44
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v18
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v43
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v42, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v17
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v20
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v46
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v45
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v44, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v20, v19
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v22, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v43
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v42, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v40, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v21, v20
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v22, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v23
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v22
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v41
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, v183, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v20
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v22, v21
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v40, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v19, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v20
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v183
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v182, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, v181, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v179
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v22, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v23
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v180
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v178, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, v177, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v182
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v181
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v18, 16, v17
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v20, 16, v19
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v23, v22
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v24, v19
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v25
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v176
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v26
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v167
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v22
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v180, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v179, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v25, v24
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v178
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v177, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v20
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v176
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v24, v23
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v26, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v19
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v20, v21
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v23
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, 0x300, v24
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, v166, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v22, v25
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v165, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v164
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v163
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v162, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v21, v23
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v161, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, v166, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v24, v20
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v25
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v167
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v27, v23
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v26
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v165
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v20
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v25, v24
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v26, v22
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v27
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v160
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v23
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v151
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v150, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v24
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v19
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, 0x300, v23
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v22
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v26, v25
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v28, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff, v20
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v24
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v23, 16, v25
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v163, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v161, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v22, 16, v21
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v26
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, v164, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v24, 16, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v160
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v151, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v25
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v150
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v149, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v26
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v162
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v27, v23
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v28
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v149
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v24
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v28
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v148
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v29, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v30
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v147
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v26, v24
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v28, v27
; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v30, v29
; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, 0x300, v23
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v27, v26
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v148, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v24, v22
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v25
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v27
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v147
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v24
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v146, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v24, v23
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, v145, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v135
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v27, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v28
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v144
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v134, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, v133, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff, v23
; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v26
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v24, 16, v22
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v134
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v27, 16, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v28
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v144
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v135, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v26, 16, v23
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, v145, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v133, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v27, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v28
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v132
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v26
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, v130, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v25
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v32, v115, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v28, v27
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v29, v24
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v30
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v132
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v31
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v131
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v29, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v30
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v131
; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v24
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v29, v28
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v31, v30
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff, v27
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v24
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v25, v26
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v28
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v29
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v29, v130, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v27, v30
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v129, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v26
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v33, 8, v117
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v30, v29
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v31
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v129
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v27, 16, v25
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v119, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v26
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v29
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v128
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v27
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v119
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v26, v28
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v118, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v28
; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v30, v29
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v117, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v128, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v27
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v118
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v28, 16, v26
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v29
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v30
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v116, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v31, v27
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, v115, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v28
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v32, 8, v116
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v34, 8, v114
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xff, v32
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v32, 8, v113
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v30
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v33, 8, v114
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xff, v31
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v34, 8, v113
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v32, v28
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v33, v29
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v36, 8, v100
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v32, v31
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v34, v30
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v27
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v103, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v34, v101, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v32, v112, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v33, v30
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v33, v103, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v35, v101, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v36, v99, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v38, v97, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v34, v31
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v37, v99, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v38, 8, v98
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xff, v34
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v39, v97, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xff, v32
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v34, 8, v102
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xff, v33
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v37, 8, v100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xff, v35
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v39, 8, v98
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xff, v36
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v48, 8, v96
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xff, v38
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v49, 8, v87
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, v34, v32
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, v37, v33
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, v39, v35
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, v48, v36
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, v49, v38
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v29, 0x300, v29
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v28
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v35, 8, v102
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v36, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xff, v37
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v37, 8, v96
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, v38, v34
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xff, v39
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v39, 8, v87
; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, 0x300, v30
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, v35, v32
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, v37, v36
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v34, 0x300, v34
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, v39, v38
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v28
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v29, 0x300, v29
; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, 0x300, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v30
; GFX11-FAKE16-NEXT: v_add_nc_u16 v32, 0x300, v32
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v33, 0x300, v33
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v34, 0x300, v34
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff, v27
; GFX11-FAKE16-NEXT: v_add_nc_u16 v35, 0x300, v35
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v34
; GFX11-FAKE16-NEXT: v_add_nc_u16 v36, 0x300, v36
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff, v29
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v28
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff, v31
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v32
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v33
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v34
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff, v35
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v36
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v29, v27
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v28, v30
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v31, v32
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v33, v34
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v35, v36
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v29, 16, v28
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v31, 16, v33
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v32, 16, v30
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v35, 16, v37
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v36, 16, v34
; GFX11-FAKE16-NEXT: .LBB14_4: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload
@@ -50391,14 +50357,14 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:388
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32
@@ -50415,16 +50381,16 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:84
; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:80
; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:76
-; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:72
-; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:68
+; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:72
+; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:68
; GFX9-NEXT: buffer_load_ushort v38, off, s[0:3], s32 offset:64
; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:60
-; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:56
-; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:52
+; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:56
+; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:52
; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:48
; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:44
-; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:40
-; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:36
+; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:40
+; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:36
; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:32
; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:28
; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:24
@@ -50532,31 +50498,31 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:364
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:188
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:360
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:184
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:356
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:180
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:352
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:176
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:348
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:172
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
@@ -50568,13 +50534,13 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:340
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:164
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:336
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:160
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
@@ -50636,8 +50602,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB38_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0xc0c0004
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v10, v55, v32, s6
@@ -50660,19 +50626,19 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s6
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_perm_b32 v16, v43, v16, s6
; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v1, v2, v1, s6
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s6
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
@@ -50735,11 +50701,11 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_perm_b32 v9, v39, v40, s6
; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; GFX9-NEXT: v_perm_b32 v10, v62, v63, s6
+; GFX9-NEXT: v_perm_b32 v10, v63, v62, s6
; GFX9-NEXT: v_lshl_or_b32 v10, v11, 16, v10
-; GFX9-NEXT: v_perm_b32 v11, v59, v54, s6
+; GFX9-NEXT: v_perm_b32 v11, v54, v59, s6
; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
-; GFX9-NEXT: v_perm_b32 v12, v58, v37, s6
+; GFX9-NEXT: v_perm_b32 v12, v37, v58, s6
; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; GFX9-NEXT: v_perm_b32 v13, v47, v52, s6
; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
@@ -50755,12 +50721,12 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr40
-; GFX9-NEXT: ; implicit-def: $vgpr62
; GFX9-NEXT: ; implicit-def: $vgpr63
-; GFX9-NEXT: ; implicit-def: $vgpr59
+; GFX9-NEXT: ; implicit-def: $vgpr62
; GFX9-NEXT: ; implicit-def: $vgpr54
-; GFX9-NEXT: ; implicit-def: $vgpr58
+; GFX9-NEXT: ; implicit-def: $vgpr59
; GFX9-NEXT: ; implicit-def: $vgpr37
+; GFX9-NEXT: ; implicit-def: $vgpr58
; GFX9-NEXT: ; implicit-def: $vgpr47
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr33
@@ -50783,21 +50749,21 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v18, v19, v18, s6
; GFX9-NEXT: v_lshl_or_b32 v17, v18, 16, v17
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v18, v19, v18, s6
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v19, v20, v19, s6
; GFX9-NEXT: v_lshl_or_b32 v18, v19, 16, v18
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v19, v20, v19, s6
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v20, v21, v20, s6
; GFX9-NEXT: v_lshl_or_b32 v19, v20, 16, v19
@@ -51106,23 +51072,22 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB38_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; GFX9-NEXT: s_movk_i32 s6, 0x300
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
@@ -51145,19 +51110,16 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(24)
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: s_waitcnt vmcnt(22)
-; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v8
; GFX9-NEXT: s_waitcnt vmcnt(21)
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v2
; GFX9-NEXT: s_waitcnt vmcnt(20)
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3
-; GFX9-NEXT: s_waitcnt vmcnt(19)
-; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4
+; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v8
; GFX9-NEXT: v_lshlrev_b16_e32 v18, 8, v18
-; GFX9-NEXT: s_waitcnt vmcnt(18)
-; GFX9-NEXT: v_lshlrev_b16_e32 v21, 8, v21
+; GFX9-NEXT: s_waitcnt vmcnt(17)
+; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4
; GFX9-NEXT: s_waitcnt vmcnt(16)
; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v17
; GFX9-NEXT: s_waitcnt vmcnt(15)
@@ -51170,10 +51132,10 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v6
; GFX9-NEXT: s_waitcnt vmcnt(11)
; GFX9-NEXT: v_lshlrev_b16_e32 v20, 8, v20
-; GFX9-NEXT: s_waitcnt vmcnt(10)
-; GFX9-NEXT: v_lshlrev_b16_e32 v22, 8, v22
+; GFX9-NEXT: v_lshlrev_b16_e32 v21, 8, v21
; GFX9-NEXT: s_waitcnt vmcnt(9)
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v7
+; GFX9-NEXT: v_lshlrev_b16_e32 v22, 8, v22
; GFX9-NEXT: s_waitcnt vmcnt(8)
; GFX9-NEXT: v_lshlrev_b16_e32 v23, 8, v23
; GFX9-NEXT: v_lshlrev_b16_e32 v24, 8, v24
@@ -51195,19 +51157,19 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v1, 3, v1
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v2, 3, v2
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v3, 3, v3
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
@@ -51223,8 +51185,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v3, 3, v3
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -51237,8 +51199,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v4, 3, v4
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -51251,8 +51213,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v5, 3, v5
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -51265,8 +51227,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v6, 3, v6
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -51279,8 +51241,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v7, 3, v7
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -51293,72 +51255,72 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v8, 3, v8
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_add_u16_e32 v8, 3, v35
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v42
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 3, v41
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
-; GFX9-NEXT: v_add_u16_sdwa v9, v9, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_add_u16_e32 v9, 3, v39
; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v40
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v10, 3, v55
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
-; GFX9-NEXT: v_add_u16_sdwa v10, v10, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
-; GFX9-NEXT: v_add_u16_e32 v10, 3, v62
-; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v63
+; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; GFX9-NEXT: v_add_u16_e32 v10, 3, v63
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v62
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 3, v61
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
-; GFX9-NEXT: v_add_u16_sdwa v11, v11, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX9-NEXT: v_add_u16_e32 v11, 3, v59
-; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v54
+; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
+; GFX9-NEXT: v_lshl_or_b32 v10, v11, 16, v10
+; GFX9-NEXT: v_add_u16_e32 v11, 3, v54
+; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v59
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v12, 3, v53
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
-; GFX9-NEXT: v_add_u16_sdwa v12, v12, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
-; GFX9-NEXT: v_add_u16_e32 v12, 3, v58
-; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v37
+; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX9-NEXT: v_add_u16_e32 v12, 3, v37
+; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v58
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v13, 3, v57
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
-; GFX9-NEXT: v_add_u16_sdwa v13, v13, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v12, v12, v13
+; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
+; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; GFX9-NEXT: v_add_u16_e32 v13, 3, v47
; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v52
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v14, 3, v51
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
-; GFX9-NEXT: v_add_u16_sdwa v14, v14, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; GFX9-NEXT: v_add_u16_e32 v14, 3, v33
; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v46
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v15, 3, v45
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
-; GFX9-NEXT: v_add_u16_sdwa v15, v15, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v14, v14, v15
+; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
+; GFX9-NEXT: v_lshl_or_b32 v14, v15, 16, v14
; GFX9-NEXT: v_add_u16_e32 v15, 3, v49
; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v44
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v16, 3, v43
; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
-; GFX9-NEXT: v_add_u16_sdwa v16, v16, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v15, v15, v16
+; GFX9-NEXT: v_add_u16_e32 v16, 0x300, v16
+; GFX9-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
@@ -51374,8 +51336,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v17, 3, v17
; GFX9-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v17, v17, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v16, v16, v17
+; GFX9-NEXT: v_add_u16_e32 v17, 0x300, v17
+; GFX9-NEXT: v_lshl_or_b32 v16, v17, 16, v16
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -51388,10 +51350,10 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v18, 3, v18
; GFX9-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v18, v18, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v17, v17, v18
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u16_e32 v18, 0x300, v18
+; GFX9-NEXT: v_lshl_or_b32 v17, v18, 16, v17
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v18, 3, v18
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -51402,22 +51364,22 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v19, 3, v19
; GFX9-NEXT: v_or_b32_sdwa v19, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v19, v19, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v18, v18, v19
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u16_e32 v19, 0x300, v19
+; GFX9-NEXT: v_lshl_or_b32 v18, v19, 16, v18
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v19, 3, v19
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v20, 8, v20
; GFX9-NEXT: v_or_b32_sdwa v19, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v19, 0x300, v19
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v20, 3, v20
; GFX9-NEXT: v_or_b32_sdwa v20, v21, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v20, v20, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v19, v19, v20
+; GFX9-NEXT: v_add_u16_e32 v20, 0x300, v20
+; GFX9-NEXT: v_lshl_or_b32 v19, v20, 16, v19
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -51430,8 +51392,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v21, 3, v21
; GFX9-NEXT: v_or_b32_sdwa v21, v22, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v21, v21, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v20, v20, v21
+; GFX9-NEXT: v_add_u16_e32 v21, 0x300, v21
+; GFX9-NEXT: v_lshl_or_b32 v20, v21, 16, v20
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -51444,8 +51406,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v22, 3, v22
; GFX9-NEXT: v_or_b32_sdwa v22, v23, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v22, v22, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v21, v21, v22
+; GFX9-NEXT: v_add_u16_e32 v22, 0x300, v22
+; GFX9-NEXT: v_lshl_or_b32 v21, v22, 16, v21
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -51458,8 +51420,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v23, 3, v23
; GFX9-NEXT: v_or_b32_sdwa v23, v24, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v23, v23, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v22, v22, v23
+; GFX9-NEXT: v_add_u16_e32 v23, 0x300, v23
+; GFX9-NEXT: v_lshl_or_b32 v22, v23, 16, v22
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -51472,8 +51434,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v24, 3, v24
; GFX9-NEXT: v_or_b32_sdwa v24, v25, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v24, v24, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v23, v23, v24
+; GFX9-NEXT: v_add_u16_e32 v24, 0x300, v24
+; GFX9-NEXT: v_lshl_or_b32 v23, v24, 16, v23
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -51486,8 +51448,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v25, 3, v25
; GFX9-NEXT: v_or_b32_sdwa v25, v26, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v25, v25, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v24, v24, v25
+; GFX9-NEXT: v_add_u16_e32 v25, 0x300, v25
+; GFX9-NEXT: v_lshl_or_b32 v24, v25, 16, v24
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -51500,8 +51462,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v26, 3, v26
; GFX9-NEXT: v_or_b32_sdwa v26, v27, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v26, v26, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v25, v25, v26
+; GFX9-NEXT: v_add_u16_e32 v26, 0x300, v26
+; GFX9-NEXT: v_lshl_or_b32 v25, v26, 16, v25
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -51514,8 +51476,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: v_or_b32_sdwa v27, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v27, v27, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v26, v26, v27
+; GFX9-NEXT: v_add_u16_e32 v27, 0x300, v27
+; GFX9-NEXT: v_lshl_or_b32 v26, v27, 16, v26
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -51528,8 +51490,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v28, 3, v28
; GFX9-NEXT: v_or_b32_sdwa v28, v29, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v28, v28, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v27, v27, v28
+; GFX9-NEXT: v_add_u16_e32 v28, 0x300, v28
+; GFX9-NEXT: v_lshl_or_b32 v27, v28, 16, v27
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -51542,8 +51504,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v29, 3, v29
; GFX9-NEXT: v_or_b32_sdwa v29, v30, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v29, v29, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v28, v28, v29
+; GFX9-NEXT: v_add_u16_e32 v29, 0x300, v29
+; GFX9-NEXT: v_lshl_or_b32 v28, v29, 16, v28
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -51556,8 +51518,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v30, 3, v30
; GFX9-NEXT: v_or_b32_sdwa v30, v31, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v30, v30, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v29, v29, v30
+; GFX9-NEXT: v_add_u16_e32 v30, 0x300, v30
+; GFX9-NEXT: v_lshl_or_b32 v29, v30, 16, v29
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -51570,8 +51532,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v31, 3, v31
; GFX9-NEXT: v_or_b32_sdwa v31, v32, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v31, v31, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v30, v30, v31
+; GFX9-NEXT: v_add_u16_e32 v31, 0x300, v31
+; GFX9-NEXT: v_lshl_or_b32 v30, v31, 16, v30
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -51582,8 +51544,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u16_e32 v32, 3, v36
; GFX9-NEXT: v_or_b32_sdwa v32, v33, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v31, 0x300, v31
-; GFX9-NEXT: v_add_u16_sdwa v32, v32, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v31, v31, v32
+; GFX9-NEXT: v_add_u16_e32 v32, 0x300, v32
+; GFX9-NEXT: v_lshl_or_b32 v31, v32, 16, v31
; GFX9-NEXT: .LBB38_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
@@ -52553,119 +52515,119 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:384
; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:380
-; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:376
-; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:372
-; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:368
-; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:364
+; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:376
+; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:372
+; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:368
+; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:364
; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:360
; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:356
; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:352
; GFX11-FAKE16-NEXT: scratch_load_u16 v112, off, s32 offset:348
-; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:344
-; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:340
-; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:336
-; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:332
-; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:328
-; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:324
-; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32 offset:320
-; GFX11-FAKE16-NEXT: scratch_load_u16 v129, off, s32 offset:316
-; GFX11-FAKE16-NEXT: scratch_load_u16 v128, off, s32 offset:312
+; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:344
+; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:340
+; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:336
+; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:332
+; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:328
+; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32 offset:324
+; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:320
+; GFX11-FAKE16-NEXT: scratch_load_u16 v128, off, s32 offset:316
+; GFX11-FAKE16-NEXT: scratch_load_u16 v129, off, s32 offset:312
; GFX11-FAKE16-NEXT: scratch_load_u16 v130, off, s32 offset:308
; GFX11-FAKE16-NEXT: scratch_load_u16 v131, off, s32 offset:304
; GFX11-FAKE16-NEXT: scratch_load_u16 v133, off, s32 offset:300
-; GFX11-FAKE16-NEXT: scratch_load_u16 v132, off, s32 offset:296
-; GFX11-FAKE16-NEXT: scratch_load_u16 v134, off, s32 offset:292
-; GFX11-FAKE16-NEXT: scratch_load_u16 v135, off, s32 offset:288
-; GFX11-FAKE16-NEXT: scratch_load_u16 v145, off, s32 offset:284
+; GFX11-FAKE16-NEXT: scratch_load_u16 v134, off, s32 offset:296
+; GFX11-FAKE16-NEXT: scratch_load_u16 v145, off, s32 offset:292
+; GFX11-FAKE16-NEXT: scratch_load_u16 v132, off, s32 offset:288
+; GFX11-FAKE16-NEXT: scratch_load_u16 v135, off, s32 offset:284
; GFX11-FAKE16-NEXT: scratch_load_u16 v144, off, s32 offset:280
; GFX11-FAKE16-NEXT: scratch_load_u16 v146, off, s32 offset:276
; GFX11-FAKE16-NEXT: scratch_load_u16 v147, off, s32 offset:272
-; GFX11-FAKE16-NEXT: scratch_load_u16 v148, off, s32 offset:268
-; GFX11-FAKE16-NEXT: scratch_load_u16 v149, off, s32 offset:264
-; GFX11-FAKE16-NEXT: scratch_load_u16 v150, off, s32 offset:260
+; GFX11-FAKE16-NEXT: scratch_load_u16 v149, off, s32 offset:268
+; GFX11-FAKE16-NEXT: scratch_load_u16 v150, off, s32 offset:264
+; GFX11-FAKE16-NEXT: scratch_load_u16 v161, off, s32 offset:260
; GFX11-FAKE16-NEXT: s_clause 0x1f
-; GFX11-FAKE16-NEXT: scratch_load_u16 v151, off, s32 offset:256
-; GFX11-FAKE16-NEXT: scratch_load_u16 v161, off, s32 offset:252
+; GFX11-FAKE16-NEXT: scratch_load_u16 v148, off, s32 offset:256
+; GFX11-FAKE16-NEXT: scratch_load_u16 v151, off, s32 offset:252
; GFX11-FAKE16-NEXT: scratch_load_u16 v160, off, s32 offset:248
-; GFX11-FAKE16-NEXT: scratch_load_u16 v162, off, s32 offset:244
-; GFX11-FAKE16-NEXT: scratch_load_u16 v163, off, s32 offset:240
-; GFX11-FAKE16-NEXT: scratch_load_u16 v165, off, s32 offset:236
-; GFX11-FAKE16-NEXT: scratch_load_u16 v164, off, s32 offset:232
+; GFX11-FAKE16-NEXT: scratch_load_u16 v163, off, s32 offset:244
+; GFX11-FAKE16-NEXT: scratch_load_u16 v162, off, s32 offset:240
+; GFX11-FAKE16-NEXT: scratch_load_u16 v164, off, s32 offset:236
+; GFX11-FAKE16-NEXT: scratch_load_u16 v165, off, s32 offset:232
; GFX11-FAKE16-NEXT: scratch_load_u16 v166, off, s32 offset:228
; GFX11-FAKE16-NEXT: scratch_load_u16 v167, off, s32 offset:224
; GFX11-FAKE16-NEXT: scratch_load_u16 v177, off, s32 offset:220
-; GFX11-FAKE16-NEXT: scratch_load_u16 v176, off, s32 offset:216
-; GFX11-FAKE16-NEXT: scratch_load_u16 v178, off, s32 offset:212
-; GFX11-FAKE16-NEXT: scratch_load_u16 v179, off, s32 offset:208
-; GFX11-FAKE16-NEXT: scratch_load_u16 v181, off, s32 offset:204
-; GFX11-FAKE16-NEXT: scratch_load_u16 v180, off, s32 offset:200
-; GFX11-FAKE16-NEXT: scratch_load_u16 v182, off, s32 offset:196
-; GFX11-FAKE16-NEXT: scratch_load_u16 v183, off, s32 offset:192
+; GFX11-FAKE16-NEXT: scratch_load_u16 v178, off, s32 offset:216
+; GFX11-FAKE16-NEXT: scratch_load_u16 v180, off, s32 offset:212
+; GFX11-FAKE16-NEXT: scratch_load_u16 v176, off, s32 offset:208
+; GFX11-FAKE16-NEXT: scratch_load_u16 v179, off, s32 offset:204
+; GFX11-FAKE16-NEXT: scratch_load_u16 v181, off, s32 offset:200
+; GFX11-FAKE16-NEXT: scratch_load_u16 v183, off, s32 offset:196
+; GFX11-FAKE16-NEXT: scratch_load_u16 v182, off, s32 offset:192
; GFX11-FAKE16-NEXT: scratch_load_u16 v40, off, s32 offset:188
; GFX11-FAKE16-NEXT: scratch_load_u16 v41, off, s32 offset:184
; GFX11-FAKE16-NEXT: scratch_load_u16 v42, off, s32 offset:180
; GFX11-FAKE16-NEXT: scratch_load_u16 v43, off, s32 offset:176
-; GFX11-FAKE16-NEXT: scratch_load_u16 v45, off, s32 offset:172
-; GFX11-FAKE16-NEXT: scratch_load_u16 v44, off, s32 offset:168
-; GFX11-FAKE16-NEXT: scratch_load_u16 v46, off, s32 offset:164
-; GFX11-FAKE16-NEXT: scratch_load_u16 v47, off, s32 offset:160
-; GFX11-FAKE16-NEXT: scratch_load_u16 v57, off, s32 offset:156
-; GFX11-FAKE16-NEXT: scratch_load_u16 v56, off, s32 offset:152
+; GFX11-FAKE16-NEXT: scratch_load_u16 v44, off, s32 offset:172
+; GFX11-FAKE16-NEXT: scratch_load_u16 v45, off, s32 offset:168
+; GFX11-FAKE16-NEXT: scratch_load_u16 v47, off, s32 offset:164
+; GFX11-FAKE16-NEXT: scratch_load_u16 v46, off, s32 offset:160
+; GFX11-FAKE16-NEXT: scratch_load_u16 v56, off, s32 offset:156
+; GFX11-FAKE16-NEXT: scratch_load_u16 v57, off, s32 offset:152
; GFX11-FAKE16-NEXT: scratch_load_u16 v58, off, s32 offset:148
; GFX11-FAKE16-NEXT: scratch_load_u16 v59, off, s32 offset:144
-; GFX11-FAKE16-NEXT: scratch_load_u16 v61, off, s32 offset:140
-; GFX11-FAKE16-NEXT: scratch_load_u16 v60, off, s32 offset:136
+; GFX11-FAKE16-NEXT: scratch_load_u16 v60, off, s32 offset:140
+; GFX11-FAKE16-NEXT: scratch_load_u16 v61, off, s32 offset:136
; GFX11-FAKE16-NEXT: scratch_load_u16 v62, off, s32 offset:132
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_load_u16 v63, off, s32 offset:128
; GFX11-FAKE16-NEXT: scratch_load_u16 v73, off, s32 offset:124
-; GFX11-FAKE16-NEXT: scratch_load_u16 v72, off, s32 offset:120
-; GFX11-FAKE16-NEXT: scratch_load_u16 v74, off, s32 offset:116
-; GFX11-FAKE16-NEXT: scratch_load_u16 v75, off, s32 offset:112
-; GFX11-FAKE16-NEXT: scratch_load_u16 v76, off, s32 offset:108
+; GFX11-FAKE16-NEXT: scratch_load_u16 v74, off, s32 offset:120
+; GFX11-FAKE16-NEXT: scratch_load_u16 v76, off, s32 offset:116
+; GFX11-FAKE16-NEXT: scratch_load_u16 v72, off, s32 offset:112
+; GFX11-FAKE16-NEXT: scratch_load_u16 v75, off, s32 offset:108
; GFX11-FAKE16-NEXT: scratch_load_u16 v77, off, s32 offset:104
; GFX11-FAKE16-NEXT: scratch_load_u16 v78, off, s32 offset:100
; GFX11-FAKE16-NEXT: scratch_load_u16 v79, off, s32 offset:96
; GFX11-FAKE16-NEXT: scratch_load_u16 v89, off, s32 offset:92
-; GFX11-FAKE16-NEXT: scratch_load_u16 v88, off, s32 offset:88
-; GFX11-FAKE16-NEXT: scratch_load_u16 v90, off, s32 offset:84
-; GFX11-FAKE16-NEXT: scratch_load_u16 v91, off, s32 offset:80
-; GFX11-FAKE16-NEXT: scratch_load_u16 v93, off, s32 offset:76
+; GFX11-FAKE16-NEXT: scratch_load_u16 v90, off, s32 offset:88
+; GFX11-FAKE16-NEXT: scratch_load_u16 v93, off, s32 offset:84
+; GFX11-FAKE16-NEXT: scratch_load_u16 v88, off, s32 offset:80
+; GFX11-FAKE16-NEXT: scratch_load_u16 v91, off, s32 offset:76
; GFX11-FAKE16-NEXT: scratch_load_u16 v92, off, s32 offset:72
; GFX11-FAKE16-NEXT: scratch_load_u16 v94, off, s32 offset:68
; GFX11-FAKE16-NEXT: scratch_load_u16 v95, off, s32 offset:64
-; GFX11-FAKE16-NEXT: scratch_load_u16 v105, off, s32 offset:60
-; GFX11-FAKE16-NEXT: scratch_load_u16 v104, off, s32 offset:56
-; GFX11-FAKE16-NEXT: scratch_load_u16 v106, off, s32 offset:52
-; GFX11-FAKE16-NEXT: scratch_load_u16 v107, off, s32 offset:48
-; GFX11-FAKE16-NEXT: scratch_load_u16 v109, off, s32 offset:44
-; GFX11-FAKE16-NEXT: scratch_load_u16 v108, off, s32 offset:40
-; GFX11-FAKE16-NEXT: scratch_load_u16 v110, off, s32 offset:36
-; GFX11-FAKE16-NEXT: scratch_load_u16 v111, off, s32 offset:32
+; GFX11-FAKE16-NEXT: scratch_load_u16 v104, off, s32 offset:60
+; GFX11-FAKE16-NEXT: scratch_load_u16 v105, off, s32 offset:56
+; GFX11-FAKE16-NEXT: scratch_load_u16 v107, off, s32 offset:52
+; GFX11-FAKE16-NEXT: scratch_load_u16 v106, off, s32 offset:48
+; GFX11-FAKE16-NEXT: scratch_load_u16 v108, off, s32 offset:44
+; GFX11-FAKE16-NEXT: scratch_load_u16 v109, off, s32 offset:40
+; GFX11-FAKE16-NEXT: scratch_load_u16 v111, off, s32 offset:36
+; GFX11-FAKE16-NEXT: scratch_load_u16 v110, off, s32 offset:32
; GFX11-FAKE16-NEXT: scratch_load_u16 v120, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_u16 v121, off, s32 offset:24
; GFX11-FAKE16-NEXT: scratch_load_u16 v122, off, s32 offset:20
; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:388
; GFX11-FAKE16-NEXT: scratch_load_u16 v123, off, s32 offset:16
; GFX11-FAKE16-NEXT: scratch_load_u16 v125, off, s32 offset:12
-; GFX11-FAKE16-NEXT: scratch_load_u16 v124, off, s32 offset:8
+; GFX11-FAKE16-NEXT: scratch_load_u16 v126, off, s32 offset:8
; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: scratch_load_u16 v126, off, s32 offset:4
-; GFX11-FAKE16-NEXT: scratch_load_u16 v127, off, s32
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v30 :: v_dual_mov_b32 v32, v29
+; GFX11-FAKE16-NEXT: scratch_load_u16 v127, off, s32 offset:4
+; GFX11-FAKE16-NEXT: scratch_load_u16 v124, off, s32
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v29
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v28 :: v_dual_mov_b32 v35, v27
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v26 :: v_dual_mov_b32 v36, v25
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v24 :: v_dual_mov_b32 v39, v23
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, v22 :: v_dual_mov_b32 v48, v21
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v20 :: v_dual_mov_b32 v51, v19
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v26 :: v_dual_mov_b32 v37, v25
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v24 :: v_dual_mov_b32 v38, v23
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v22 :: v_dual_mov_b32 v49, v21
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v20 :: v_dual_mov_b32 v50, v19
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v18 :: v_dual_mov_b32 v53, v17
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v16 :: v_dual_mov_b32 v55, v15
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v65, v14 :: v_dual_mov_b32 v64, v13
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v12 :: v_dual_mov_b32 v67, v11
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v69, v10 :: v_dual_mov_b32 v68, v9
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v65, v14 :: v_dual_mov_b32 v66, v13
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v69, v12 :: v_dual_mov_b32 v64, v11
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v67, v10 :: v_dual_mov_b32 v68, v9
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v8 :: v_dual_mov_b32 v71, v7
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v6 :: v_dual_mov_b32 v81, v5
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v4 :: v_dual_mov_b32 v83, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v6 :: v_dual_mov_b32 v83, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v5 :: v_dual_mov_b32 v81, v3
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v85, v2 :: v_dual_mov_b32 v84, v1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
@@ -52676,96 +52638,96 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB38_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v86, v84, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v85, v83, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v82, v81, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v80, v71, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v66, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v85, v81, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v83, v80, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v82, v71, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v69, v66, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v65, v55, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v54, v53, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v70, v68, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v69, v67, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v52, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v50, v48, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v49, v39, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v38, v36, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v37, v35, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v67, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v52, v50, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v51, v49, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v48, v38, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v39, v37, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v36, v35, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v7, 16, v6
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v9, 16, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v11, 16, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v34, v32, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v34, v33, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v33, v127, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v126, v124, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v32, v124, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v127, v126, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v125, v123, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v122, v121, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v120, v111, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v110, v108, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v109, v107, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v106, v104, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v105, v95, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v120, v110, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v111, v109, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v108, v106, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v107, v105, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v104, v95, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v10, 16, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v14, 16, v13
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v16, 16, v15
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v94, v92, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v93, v91, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v90, v88, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v91, v88, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v93, v90, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v89, v79, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v78, v77, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v76, v75, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v74, v72, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v75, v72, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v76, v74, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v73, v63, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v62, v60, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v61, v59, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v62, v61, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v60, v59, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v15, 16, v14
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v17, 16, v16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v19, 16, v18
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v21, 16, v20
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v58, v56, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v57, v47, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v46, v44, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v45, v43, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v58, v57, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v56, v46, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v47, v45, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v44, v43, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v42, v41, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v40, v183, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v182, v180, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v181, v179, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v178, v176, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v40, v182, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v183, v181, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v179, v176, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v180, v178, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v177, v167, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v18, 16, v17
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v20, 16, v19
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v22, 16, v21
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v24, 16, v23
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v26, 16, v25
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v166, v164, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v165, v163, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v162, v160, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v161, v151, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v150, v149, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v148, v147, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v166, v165, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v164, v162, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v163, v160, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v151, v148, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v161, v150, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v149, v147, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v146, v144, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v145, v135, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v30, v134, v132, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v135, v132, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v145, v134, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v31, v133, v131, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v23, 16, v22
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v25, 16, v24
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v27, 16, v26
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v29, 16, v28
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v31, 16, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v130, v128, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v129, v119, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v118, v116, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v30, v117, v114, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v115, v113, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v130, v129, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v128, v117, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v119, v118, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v115, v113, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v116, v114, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v32, v112, v102, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v33, v103, v100, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v34, v101, v98, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v35, v99, v96, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v34, v99, v96, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v35, v101, v98, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v36, v97, v87, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v28, 16, v27
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v30, 16, v29
@@ -52775,129 +52737,129 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr124
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr127
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr126
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr124
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr125
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr123
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr122
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr121
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr120
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr111
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr110
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr108
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr111
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr109
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr107
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr108
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr106
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr104
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr107
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr105
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr104
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr95
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr94
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr92
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr93
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr91
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr90
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr88
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr93
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr90
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr89
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr79
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr78
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr77
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr76
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr75
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr74
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr72
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr76
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr74
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr73
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr63
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr62
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr60
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr61
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr60
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr59
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr58
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr56
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr57
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr47
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr56
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr46
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr44
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr47
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr45
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr44
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr43
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr42
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr41
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr40
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr183
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr182
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr180
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr183
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr181
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr179
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr178
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr176
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr180
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr178
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr177
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr167
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr166
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr164
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr165
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr163
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr164
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr162
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr163
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr160
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr161
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr151
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr148
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr161
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr150
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr149
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr148
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr147
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr146
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr144
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr145
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr133
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
; GFX11-FAKE16-NEXT: .LBB38_2: ; %Flow
@@ -52905,422 +52867,392 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB38_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v86, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v83, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v85, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v84
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v83
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v84
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v82, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v80
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v80, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v81
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v81
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v71
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v71
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v6, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v69, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v69, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v70, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v67
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v66
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v65, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v68
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v66, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v54, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v65, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v64
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v68
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v67, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v55
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v64
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v54, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v48, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v39, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v53
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v52, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v51
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v50, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v49, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v39
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v51, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v50
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v48
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v38, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v37, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v49
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v36, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v126
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v38
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v37
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v9, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v36
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v35
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v125, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v35
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v34, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v8
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v127, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v34, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v33, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v32
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v33
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v32, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v127
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v126, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v125, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v8, 16, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v120, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v124
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v123
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v122, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v12, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v13
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v123
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v121
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v122, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v120, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v111
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v110, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v109, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v107
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v108
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v121
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v111, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v107, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v10, 16, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v110
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v106, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v105, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v109
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v108, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v90
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v13, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v106
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v105
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v104
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v95
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v16, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v94, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v104, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v11, 16, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v95
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v94, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v11, 16, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v93, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v92
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v91, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v91
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v90, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v89, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v89, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v17
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v16
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v88
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v79
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v78, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v17, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v18
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v79
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v16, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v18
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v77
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v77
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v18, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v78, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v16
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v76, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v75
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v74, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v73, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v63
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v76, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v13, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v15, 16, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v16, 16, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v75, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v20
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v74
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v73, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v72
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v62, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v18
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v72
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v62, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v61, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v63
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v19, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v61
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v18, v17
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v20
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v60
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v21
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v59
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v60, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v15
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v17
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v21, v20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v16
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v20
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v59
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v58, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v17, 16, v16
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v19
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, v58, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v17, v20
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v57, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v20, v19
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v57
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v56, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v47, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v56
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v47
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v46, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v16, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v45, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v20, v19
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v21, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v44
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v18
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v43
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v42, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v17
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v20
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v46
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v45
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v44, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v20, v19
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v22, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v43
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v42, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v40, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v21, v20
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v22, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v23
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v22
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v41
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, v183, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v20
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v22, v21
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v40, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v19, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v20
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v183
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v182, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, v181, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v179
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v22, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v23
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v180
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v178, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, v177, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v182
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v181
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v18, 16, v17
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v20, 16, v19
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v23, v22
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v24, v19
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v25
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v176
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v26
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v167
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v22
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v180, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v179, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v25, v24
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v178
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v177, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v20
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v176
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v24, v23
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v26, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v19
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v20, v21
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v23
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, 0x300, v24
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, v166, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v22, v25
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v165, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v164
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v163
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v162, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v21, v23
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v161, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, v166, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v24, v20
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v25
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v167
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v27, v23
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v26
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v165
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v20
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v25, v24
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v26, v22
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v27
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v160
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v23
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v151
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v150, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v24
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v19
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, 0x300, v23
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v22
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v26, v25
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v28, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff, v20
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v24
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v23, 16, v25
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v163, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v161, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v22, 16, v21
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v26
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, v164, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v24, 16, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v160
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v151, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v25
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v150
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v149, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v26
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v162
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v27, v23
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v28
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v149
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v24
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v28
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v148
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v29, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v30
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v147
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v26, v24
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v28, v27
; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v30, v29
; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, 0x300, v23
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v27, v26
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v148, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v24, v22
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v25
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v27
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v147
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v24
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v146, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v24, v23
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, v145, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v135
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v27, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v28
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v144
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v134, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, v133, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff, v23
; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v26
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v24, 16, v22
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v134
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v27, 16, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v28
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v144
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v135, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v26, 16, v23
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, v145, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v133, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v27, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v28
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v132
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v26
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, v130, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v25
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v32, v115, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v28, v27
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v29, v24
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v30
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v132
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v31
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v131
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v29, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v30
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v131
; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v24
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v29, v28
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v31, v30
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff, v27
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v24
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v25, v26
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v28
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v29
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v29, v130, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v27, v30
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v129, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v26
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v33, 8, v117
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v30, v29
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v31
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v129
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v27, 16, v25
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v119, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v26
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v29
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v128
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v27
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v119
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v26, v28
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v118, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v28
; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v30, v29
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v117, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v128, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v27
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v118
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v28, 16, v26
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v29
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v30
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v116, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v31, v27
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, v115, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v28
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v32, 8, v116
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v34, 8, v114
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xff, v32
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v32, 8, v113
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v30
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v33, 8, v114
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xff, v31
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v34, 8, v113
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v32, v28
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v33, v29
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v36, 8, v100
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v32, v31
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v34, v30
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v27
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v103, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v34, v101, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v32, v112, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v33, v30
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v33, v103, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v35, v101, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v36, v99, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v38, v97, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v34, v31
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v37, v99, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v38, 8, v98
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xff, v34
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v39, v97, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xff, v32
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v34, 8, v102
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xff, v33
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v37, 8, v100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xff, v35
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v39, 8, v98
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xff, v36
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v48, 8, v96
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xff, v38
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v49, 8, v87
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, v34, v32
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, v37, v33
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, v39, v35
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, v48, v36
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, v49, v38
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v29, 0x300, v29
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v28
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v35, 8, v102
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v36, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xff, v37
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v37, 8, v96
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, v38, v34
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xff, v39
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v39, 8, v87
; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, 0x300, v30
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, v35, v32
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, v37, v36
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v34, 0x300, v34
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, v39, v38
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v28
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v29, 0x300, v29
; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, 0x300, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v30
; GFX11-FAKE16-NEXT: v_add_nc_u16 v32, 0x300, v32
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v33, 0x300, v33
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v34, 0x300, v34
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff, v27
; GFX11-FAKE16-NEXT: v_add_nc_u16 v35, 0x300, v35
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v34
; GFX11-FAKE16-NEXT: v_add_nc_u16 v36, 0x300, v36
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff, v29
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v28
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff, v31
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v32
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v33
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v34
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff, v35
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v36
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v29, v27
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v28, v30
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v31, v32
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v33, v34
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v35, v36
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v29, 16, v28
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v31, 16, v33
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v32, 16, v30
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v35, 16, v37
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v36, 16, v34
; GFX11-FAKE16-NEXT: .LBB38_4: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload
@@ -84281,14 +84213,14 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:388
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32
@@ -84305,16 +84237,16 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:84
; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:80
; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:76
-; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:72
-; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:68
+; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:72
+; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:68
; GFX9-NEXT: buffer_load_ushort v38, off, s[0:3], s32 offset:64
; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:60
-; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:56
-; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:52
+; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:56
+; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:52
; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:48
; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:44
-; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:40
-; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:36
+; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:40
+; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:36
; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:32
; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:28
; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:24
@@ -84422,31 +84354,31 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:364
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:188
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:360
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:184
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:356
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:180
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:352
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:176
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:348
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:172
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
@@ -84458,13 +84390,13 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:340
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:164
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:336
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:160
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
@@ -84526,8 +84458,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB58_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0xc0c0004
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v10, v55, v32, s6
@@ -84550,19 +84482,19 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s6
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_perm_b32 v16, v43, v16, s6
; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v1, v2, v1, s6
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s6
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
@@ -84625,11 +84557,11 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_perm_b32 v9, v39, v40, s6
; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; GFX9-NEXT: v_perm_b32 v10, v62, v63, s6
+; GFX9-NEXT: v_perm_b32 v10, v63, v62, s6
; GFX9-NEXT: v_lshl_or_b32 v10, v11, 16, v10
-; GFX9-NEXT: v_perm_b32 v11, v59, v54, s6
+; GFX9-NEXT: v_perm_b32 v11, v54, v59, s6
; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
-; GFX9-NEXT: v_perm_b32 v12, v58, v37, s6
+; GFX9-NEXT: v_perm_b32 v12, v37, v58, s6
; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; GFX9-NEXT: v_perm_b32 v13, v47, v52, s6
; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
@@ -84645,12 +84577,12 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr40
-; GFX9-NEXT: ; implicit-def: $vgpr62
; GFX9-NEXT: ; implicit-def: $vgpr63
-; GFX9-NEXT: ; implicit-def: $vgpr59
+; GFX9-NEXT: ; implicit-def: $vgpr62
; GFX9-NEXT: ; implicit-def: $vgpr54
-; GFX9-NEXT: ; implicit-def: $vgpr58
+; GFX9-NEXT: ; implicit-def: $vgpr59
; GFX9-NEXT: ; implicit-def: $vgpr37
+; GFX9-NEXT: ; implicit-def: $vgpr58
; GFX9-NEXT: ; implicit-def: $vgpr47
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr33
@@ -84673,21 +84605,21 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v18, v19, v18, s6
; GFX9-NEXT: v_lshl_or_b32 v17, v18, 16, v17
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v18, v19, v18, s6
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v19, v20, v19, s6
; GFX9-NEXT: v_lshl_or_b32 v18, v19, 16, v18
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v19, v20, v19, s6
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v20, v21, v20, s6
; GFX9-NEXT: v_lshl_or_b32 v19, v20, 16, v19
@@ -84996,23 +84928,22 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB58_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; GFX9-NEXT: s_movk_i32 s6, 0x300
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
@@ -85035,19 +84966,16 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(24)
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: s_waitcnt vmcnt(22)
-; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v8
; GFX9-NEXT: s_waitcnt vmcnt(21)
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v2
; GFX9-NEXT: s_waitcnt vmcnt(20)
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3
-; GFX9-NEXT: s_waitcnt vmcnt(19)
-; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4
+; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v8
; GFX9-NEXT: v_lshlrev_b16_e32 v18, 8, v18
-; GFX9-NEXT: s_waitcnt vmcnt(18)
-; GFX9-NEXT: v_lshlrev_b16_e32 v21, 8, v21
+; GFX9-NEXT: s_waitcnt vmcnt(17)
+; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4
; GFX9-NEXT: s_waitcnt vmcnt(16)
; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v17
; GFX9-NEXT: s_waitcnt vmcnt(15)
@@ -85060,10 +84988,10 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v6
; GFX9-NEXT: s_waitcnt vmcnt(11)
; GFX9-NEXT: v_lshlrev_b16_e32 v20, 8, v20
-; GFX9-NEXT: s_waitcnt vmcnt(10)
-; GFX9-NEXT: v_lshlrev_b16_e32 v22, 8, v22
+; GFX9-NEXT: v_lshlrev_b16_e32 v21, 8, v21
; GFX9-NEXT: s_waitcnt vmcnt(9)
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v7
+; GFX9-NEXT: v_lshlrev_b16_e32 v22, 8, v22
; GFX9-NEXT: s_waitcnt vmcnt(8)
; GFX9-NEXT: v_lshlrev_b16_e32 v23, 8, v23
; GFX9-NEXT: v_lshlrev_b16_e32 v24, 8, v24
@@ -85085,19 +85013,19 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v1, 3, v1
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v2, 3, v2
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v3, 3, v3
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
@@ -85113,8 +85041,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v3, 3, v3
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -85127,8 +85055,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v4, 3, v4
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -85141,8 +85069,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v5, 3, v5
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -85155,8 +85083,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v6, 3, v6
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -85169,8 +85097,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v7, 3, v7
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -85183,72 +85111,72 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v8, 3, v8
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_add_u16_e32 v8, 3, v35
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v42
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 3, v41
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
-; GFX9-NEXT: v_add_u16_sdwa v9, v9, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_add_u16_e32 v9, 3, v39
; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v40
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v10, 3, v55
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
-; GFX9-NEXT: v_add_u16_sdwa v10, v10, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
-; GFX9-NEXT: v_add_u16_e32 v10, 3, v62
-; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v63
+; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; GFX9-NEXT: v_add_u16_e32 v10, 3, v63
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v62
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 3, v61
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
-; GFX9-NEXT: v_add_u16_sdwa v11, v11, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX9-NEXT: v_add_u16_e32 v11, 3, v59
-; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v54
+; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
+; GFX9-NEXT: v_lshl_or_b32 v10, v11, 16, v10
+; GFX9-NEXT: v_add_u16_e32 v11, 3, v54
+; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v59
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v12, 3, v53
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
-; GFX9-NEXT: v_add_u16_sdwa v12, v12, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
-; GFX9-NEXT: v_add_u16_e32 v12, 3, v58
-; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v37
+; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX9-NEXT: v_add_u16_e32 v12, 3, v37
+; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v58
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v13, 3, v57
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
-; GFX9-NEXT: v_add_u16_sdwa v13, v13, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v12, v12, v13
+; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
+; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; GFX9-NEXT: v_add_u16_e32 v13, 3, v47
; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v52
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v14, 3, v51
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
-; GFX9-NEXT: v_add_u16_sdwa v14, v14, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; GFX9-NEXT: v_add_u16_e32 v14, 3, v33
; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v46
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v15, 3, v45
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
-; GFX9-NEXT: v_add_u16_sdwa v15, v15, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v14, v14, v15
+; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
+; GFX9-NEXT: v_lshl_or_b32 v14, v15, 16, v14
; GFX9-NEXT: v_add_u16_e32 v15, 3, v49
; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v44
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v16, 3, v43
; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
-; GFX9-NEXT: v_add_u16_sdwa v16, v16, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v15, v15, v16
+; GFX9-NEXT: v_add_u16_e32 v16, 0x300, v16
+; GFX9-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
@@ -85264,8 +85192,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v17, 3, v17
; GFX9-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v17, v17, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v16, v16, v17
+; GFX9-NEXT: v_add_u16_e32 v17, 0x300, v17
+; GFX9-NEXT: v_lshl_or_b32 v16, v17, 16, v16
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -85278,10 +85206,10 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v18, 3, v18
; GFX9-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v18, v18, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v17, v17, v18
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u16_e32 v18, 0x300, v18
+; GFX9-NEXT: v_lshl_or_b32 v17, v18, 16, v17
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v18, 3, v18
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -85292,22 +85220,22 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v19, 3, v19
; GFX9-NEXT: v_or_b32_sdwa v19, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v19, v19, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v18, v18, v19
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u16_e32 v19, 0x300, v19
+; GFX9-NEXT: v_lshl_or_b32 v18, v19, 16, v18
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v19, 3, v19
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v20, 8, v20
; GFX9-NEXT: v_or_b32_sdwa v19, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v19, 0x300, v19
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v20, 3, v20
; GFX9-NEXT: v_or_b32_sdwa v20, v21, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v20, v20, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v19, v19, v20
+; GFX9-NEXT: v_add_u16_e32 v20, 0x300, v20
+; GFX9-NEXT: v_lshl_or_b32 v19, v20, 16, v19
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -85320,8 +85248,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v21, 3, v21
; GFX9-NEXT: v_or_b32_sdwa v21, v22, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v21, v21, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v20, v20, v21
+; GFX9-NEXT: v_add_u16_e32 v21, 0x300, v21
+; GFX9-NEXT: v_lshl_or_b32 v20, v21, 16, v20
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -85334,8 +85262,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v22, 3, v22
; GFX9-NEXT: v_or_b32_sdwa v22, v23, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v22, v22, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v21, v21, v22
+; GFX9-NEXT: v_add_u16_e32 v22, 0x300, v22
+; GFX9-NEXT: v_lshl_or_b32 v21, v22, 16, v21
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -85348,8 +85276,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v23, 3, v23
; GFX9-NEXT: v_or_b32_sdwa v23, v24, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v23, v23, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v22, v22, v23
+; GFX9-NEXT: v_add_u16_e32 v23, 0x300, v23
+; GFX9-NEXT: v_lshl_or_b32 v22, v23, 16, v22
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -85362,8 +85290,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v24, 3, v24
; GFX9-NEXT: v_or_b32_sdwa v24, v25, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v24, v24, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v23, v23, v24
+; GFX9-NEXT: v_add_u16_e32 v24, 0x300, v24
+; GFX9-NEXT: v_lshl_or_b32 v23, v24, 16, v23
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -85376,8 +85304,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v25, 3, v25
; GFX9-NEXT: v_or_b32_sdwa v25, v26, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v25, v25, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v24, v24, v25
+; GFX9-NEXT: v_add_u16_e32 v25, 0x300, v25
+; GFX9-NEXT: v_lshl_or_b32 v24, v25, 16, v24
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -85390,8 +85318,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v26, 3, v26
; GFX9-NEXT: v_or_b32_sdwa v26, v27, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v26, v26, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v25, v25, v26
+; GFX9-NEXT: v_add_u16_e32 v26, 0x300, v26
+; GFX9-NEXT: v_lshl_or_b32 v25, v26, 16, v25
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -85404,8 +85332,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: v_or_b32_sdwa v27, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v27, v27, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v26, v26, v27
+; GFX9-NEXT: v_add_u16_e32 v27, 0x300, v27
+; GFX9-NEXT: v_lshl_or_b32 v26, v27, 16, v26
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -85418,8 +85346,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v28, 3, v28
; GFX9-NEXT: v_or_b32_sdwa v28, v29, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v28, v28, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v27, v27, v28
+; GFX9-NEXT: v_add_u16_e32 v28, 0x300, v28
+; GFX9-NEXT: v_lshl_or_b32 v27, v28, 16, v27
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -85432,8 +85360,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v29, 3, v29
; GFX9-NEXT: v_or_b32_sdwa v29, v30, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v29, v29, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v28, v28, v29
+; GFX9-NEXT: v_add_u16_e32 v29, 0x300, v29
+; GFX9-NEXT: v_lshl_or_b32 v28, v29, 16, v28
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -85446,8 +85374,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v30, 3, v30
; GFX9-NEXT: v_or_b32_sdwa v30, v31, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v30, v30, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v29, v29, v30
+; GFX9-NEXT: v_add_u16_e32 v30, 0x300, v30
+; GFX9-NEXT: v_lshl_or_b32 v29, v30, 16, v29
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -85460,8 +85388,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v31, 3, v31
; GFX9-NEXT: v_or_b32_sdwa v31, v32, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v31, v31, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v30, v30, v31
+; GFX9-NEXT: v_add_u16_e32 v31, 0x300, v31
+; GFX9-NEXT: v_lshl_or_b32 v30, v31, 16, v30
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -85472,8 +85400,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u16_e32 v32, 3, v36
; GFX9-NEXT: v_or_b32_sdwa v32, v33, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v31, 0x300, v31
-; GFX9-NEXT: v_add_u16_sdwa v32, v32, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v31, v31, v32
+; GFX9-NEXT: v_add_u16_e32 v32, 0x300, v32
+; GFX9-NEXT: v_lshl_or_b32 v31, v32, 16, v31
; GFX9-NEXT: .LBB58_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
@@ -86443,119 +86371,119 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:384
; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:380
-; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:376
-; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:372
-; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:368
-; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:364
+; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:376
+; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:372
+; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:368
+; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:364
; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:360
; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:356
; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:352
; GFX11-FAKE16-NEXT: scratch_load_u16 v112, off, s32 offset:348
-; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:344
-; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:340
-; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:336
-; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:332
-; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:328
-; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:324
-; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32 offset:320
-; GFX11-FAKE16-NEXT: scratch_load_u16 v129, off, s32 offset:316
-; GFX11-FAKE16-NEXT: scratch_load_u16 v128, off, s32 offset:312
+; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:344
+; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:340
+; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:336
+; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:332
+; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:328
+; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32 offset:324
+; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:320
+; GFX11-FAKE16-NEXT: scratch_load_u16 v128, off, s32 offset:316
+; GFX11-FAKE16-NEXT: scratch_load_u16 v129, off, s32 offset:312
; GFX11-FAKE16-NEXT: scratch_load_u16 v130, off, s32 offset:308
; GFX11-FAKE16-NEXT: scratch_load_u16 v131, off, s32 offset:304
; GFX11-FAKE16-NEXT: scratch_load_u16 v133, off, s32 offset:300
-; GFX11-FAKE16-NEXT: scratch_load_u16 v132, off, s32 offset:296
-; GFX11-FAKE16-NEXT: scratch_load_u16 v134, off, s32 offset:292
-; GFX11-FAKE16-NEXT: scratch_load_u16 v135, off, s32 offset:288
-; GFX11-FAKE16-NEXT: scratch_load_u16 v145, off, s32 offset:284
+; GFX11-FAKE16-NEXT: scratch_load_u16 v134, off, s32 offset:296
+; GFX11-FAKE16-NEXT: scratch_load_u16 v145, off, s32 offset:292
+; GFX11-FAKE16-NEXT: scratch_load_u16 v132, off, s32 offset:288
+; GFX11-FAKE16-NEXT: scratch_load_u16 v135, off, s32 offset:284
; GFX11-FAKE16-NEXT: scratch_load_u16 v144, off, s32 offset:280
; GFX11-FAKE16-NEXT: scratch_load_u16 v146, off, s32 offset:276
; GFX11-FAKE16-NEXT: scratch_load_u16 v147, off, s32 offset:272
-; GFX11-FAKE16-NEXT: scratch_load_u16 v148, off, s32 offset:268
-; GFX11-FAKE16-NEXT: scratch_load_u16 v149, off, s32 offset:264
-; GFX11-FAKE16-NEXT: scratch_load_u16 v150, off, s32 offset:260
+; GFX11-FAKE16-NEXT: scratch_load_u16 v149, off, s32 offset:268
+; GFX11-FAKE16-NEXT: scratch_load_u16 v150, off, s32 offset:264
+; GFX11-FAKE16-NEXT: scratch_load_u16 v161, off, s32 offset:260
; GFX11-FAKE16-NEXT: s_clause 0x1f
-; GFX11-FAKE16-NEXT: scratch_load_u16 v151, off, s32 offset:256
-; GFX11-FAKE16-NEXT: scratch_load_u16 v161, off, s32 offset:252
+; GFX11-FAKE16-NEXT: scratch_load_u16 v148, off, s32 offset:256
+; GFX11-FAKE16-NEXT: scratch_load_u16 v151, off, s32 offset:252
; GFX11-FAKE16-NEXT: scratch_load_u16 v160, off, s32 offset:248
-; GFX11-FAKE16-NEXT: scratch_load_u16 v162, off, s32 offset:244
-; GFX11-FAKE16-NEXT: scratch_load_u16 v163, off, s32 offset:240
-; GFX11-FAKE16-NEXT: scratch_load_u16 v165, off, s32 offset:236
-; GFX11-FAKE16-NEXT: scratch_load_u16 v164, off, s32 offset:232
+; GFX11-FAKE16-NEXT: scratch_load_u16 v163, off, s32 offset:244
+; GFX11-FAKE16-NEXT: scratch_load_u16 v162, off, s32 offset:240
+; GFX11-FAKE16-NEXT: scratch_load_u16 v164, off, s32 offset:236
+; GFX11-FAKE16-NEXT: scratch_load_u16 v165, off, s32 offset:232
; GFX11-FAKE16-NEXT: scratch_load_u16 v166, off, s32 offset:228
; GFX11-FAKE16-NEXT: scratch_load_u16 v167, off, s32 offset:224
; GFX11-FAKE16-NEXT: scratch_load_u16 v177, off, s32 offset:220
-; GFX11-FAKE16-NEXT: scratch_load_u16 v176, off, s32 offset:216
-; GFX11-FAKE16-NEXT: scratch_load_u16 v178, off, s32 offset:212
-; GFX11-FAKE16-NEXT: scratch_load_u16 v179, off, s32 offset:208
-; GFX11-FAKE16-NEXT: scratch_load_u16 v181, off, s32 offset:204
-; GFX11-FAKE16-NEXT: scratch_load_u16 v180, off, s32 offset:200
-; GFX11-FAKE16-NEXT: scratch_load_u16 v182, off, s32 offset:196
-; GFX11-FAKE16-NEXT: scratch_load_u16 v183, off, s32 offset:192
+; GFX11-FAKE16-NEXT: scratch_load_u16 v178, off, s32 offset:216
+; GFX11-FAKE16-NEXT: scratch_load_u16 v180, off, s32 offset:212
+; GFX11-FAKE16-NEXT: scratch_load_u16 v176, off, s32 offset:208
+; GFX11-FAKE16-NEXT: scratch_load_u16 v179, off, s32 offset:204
+; GFX11-FAKE16-NEXT: scratch_load_u16 v181, off, s32 offset:200
+; GFX11-FAKE16-NEXT: scratch_load_u16 v183, off, s32 offset:196
+; GFX11-FAKE16-NEXT: scratch_load_u16 v182, off, s32 offset:192
; GFX11-FAKE16-NEXT: scratch_load_u16 v40, off, s32 offset:188
; GFX11-FAKE16-NEXT: scratch_load_u16 v41, off, s32 offset:184
; GFX11-FAKE16-NEXT: scratch_load_u16 v42, off, s32 offset:180
; GFX11-FAKE16-NEXT: scratch_load_u16 v43, off, s32 offset:176
-; GFX11-FAKE16-NEXT: scratch_load_u16 v45, off, s32 offset:172
-; GFX11-FAKE16-NEXT: scratch_load_u16 v44, off, s32 offset:168
-; GFX11-FAKE16-NEXT: scratch_load_u16 v46, off, s32 offset:164
-; GFX11-FAKE16-NEXT: scratch_load_u16 v47, off, s32 offset:160
-; GFX11-FAKE16-NEXT: scratch_load_u16 v57, off, s32 offset:156
-; GFX11-FAKE16-NEXT: scratch_load_u16 v56, off, s32 offset:152
+; GFX11-FAKE16-NEXT: scratch_load_u16 v44, off, s32 offset:172
+; GFX11-FAKE16-NEXT: scratch_load_u16 v45, off, s32 offset:168
+; GFX11-FAKE16-NEXT: scratch_load_u16 v47, off, s32 offset:164
+; GFX11-FAKE16-NEXT: scratch_load_u16 v46, off, s32 offset:160
+; GFX11-FAKE16-NEXT: scratch_load_u16 v56, off, s32 offset:156
+; GFX11-FAKE16-NEXT: scratch_load_u16 v57, off, s32 offset:152
; GFX11-FAKE16-NEXT: scratch_load_u16 v58, off, s32 offset:148
; GFX11-FAKE16-NEXT: scratch_load_u16 v59, off, s32 offset:144
-; GFX11-FAKE16-NEXT: scratch_load_u16 v61, off, s32 offset:140
-; GFX11-FAKE16-NEXT: scratch_load_u16 v60, off, s32 offset:136
+; GFX11-FAKE16-NEXT: scratch_load_u16 v60, off, s32 offset:140
+; GFX11-FAKE16-NEXT: scratch_load_u16 v61, off, s32 offset:136
; GFX11-FAKE16-NEXT: scratch_load_u16 v62, off, s32 offset:132
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_load_u16 v63, off, s32 offset:128
; GFX11-FAKE16-NEXT: scratch_load_u16 v73, off, s32 offset:124
-; GFX11-FAKE16-NEXT: scratch_load_u16 v72, off, s32 offset:120
-; GFX11-FAKE16-NEXT: scratch_load_u16 v74, off, s32 offset:116
-; GFX11-FAKE16-NEXT: scratch_load_u16 v75, off, s32 offset:112
-; GFX11-FAKE16-NEXT: scratch_load_u16 v76, off, s32 offset:108
+; GFX11-FAKE16-NEXT: scratch_load_u16 v74, off, s32 offset:120
+; GFX11-FAKE16-NEXT: scratch_load_u16 v76, off, s32 offset:116
+; GFX11-FAKE16-NEXT: scratch_load_u16 v72, off, s32 offset:112
+; GFX11-FAKE16-NEXT: scratch_load_u16 v75, off, s32 offset:108
; GFX11-FAKE16-NEXT: scratch_load_u16 v77, off, s32 offset:104
; GFX11-FAKE16-NEXT: scratch_load_u16 v78, off, s32 offset:100
; GFX11-FAKE16-NEXT: scratch_load_u16 v79, off, s32 offset:96
; GFX11-FAKE16-NEXT: scratch_load_u16 v89, off, s32 offset:92
-; GFX11-FAKE16-NEXT: scratch_load_u16 v88, off, s32 offset:88
-; GFX11-FAKE16-NEXT: scratch_load_u16 v90, off, s32 offset:84
-; GFX11-FAKE16-NEXT: scratch_load_u16 v91, off, s32 offset:80
-; GFX11-FAKE16-NEXT: scratch_load_u16 v93, off, s32 offset:76
+; GFX11-FAKE16-NEXT: scratch_load_u16 v90, off, s32 offset:88
+; GFX11-FAKE16-NEXT: scratch_load_u16 v93, off, s32 offset:84
+; GFX11-FAKE16-NEXT: scratch_load_u16 v88, off, s32 offset:80
+; GFX11-FAKE16-NEXT: scratch_load_u16 v91, off, s32 offset:76
; GFX11-FAKE16-NEXT: scratch_load_u16 v92, off, s32 offset:72
; GFX11-FAKE16-NEXT: scratch_load_u16 v94, off, s32 offset:68
; GFX11-FAKE16-NEXT: scratch_load_u16 v95, off, s32 offset:64
-; GFX11-FAKE16-NEXT: scratch_load_u16 v105, off, s32 offset:60
-; GFX11-FAKE16-NEXT: scratch_load_u16 v104, off, s32 offset:56
-; GFX11-FAKE16-NEXT: scratch_load_u16 v106, off, s32 offset:52
-; GFX11-FAKE16-NEXT: scratch_load_u16 v107, off, s32 offset:48
-; GFX11-FAKE16-NEXT: scratch_load_u16 v109, off, s32 offset:44
-; GFX11-FAKE16-NEXT: scratch_load_u16 v108, off, s32 offset:40
-; GFX11-FAKE16-NEXT: scratch_load_u16 v110, off, s32 offset:36
-; GFX11-FAKE16-NEXT: scratch_load_u16 v111, off, s32 offset:32
+; GFX11-FAKE16-NEXT: scratch_load_u16 v104, off, s32 offset:60
+; GFX11-FAKE16-NEXT: scratch_load_u16 v105, off, s32 offset:56
+; GFX11-FAKE16-NEXT: scratch_load_u16 v107, off, s32 offset:52
+; GFX11-FAKE16-NEXT: scratch_load_u16 v106, off, s32 offset:48
+; GFX11-FAKE16-NEXT: scratch_load_u16 v108, off, s32 offset:44
+; GFX11-FAKE16-NEXT: scratch_load_u16 v109, off, s32 offset:40
+; GFX11-FAKE16-NEXT: scratch_load_u16 v111, off, s32 offset:36
+; GFX11-FAKE16-NEXT: scratch_load_u16 v110, off, s32 offset:32
; GFX11-FAKE16-NEXT: scratch_load_u16 v120, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_u16 v121, off, s32 offset:24
; GFX11-FAKE16-NEXT: scratch_load_u16 v122, off, s32 offset:20
; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:388
; GFX11-FAKE16-NEXT: scratch_load_u16 v123, off, s32 offset:16
; GFX11-FAKE16-NEXT: scratch_load_u16 v125, off, s32 offset:12
-; GFX11-FAKE16-NEXT: scratch_load_u16 v124, off, s32 offset:8
+; GFX11-FAKE16-NEXT: scratch_load_u16 v126, off, s32 offset:8
; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: scratch_load_u16 v126, off, s32 offset:4
-; GFX11-FAKE16-NEXT: scratch_load_u16 v127, off, s32
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v30 :: v_dual_mov_b32 v32, v29
+; GFX11-FAKE16-NEXT: scratch_load_u16 v127, off, s32 offset:4
+; GFX11-FAKE16-NEXT: scratch_load_u16 v124, off, s32
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v29
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v28 :: v_dual_mov_b32 v35, v27
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v26 :: v_dual_mov_b32 v36, v25
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v24 :: v_dual_mov_b32 v39, v23
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, v22 :: v_dual_mov_b32 v48, v21
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v20 :: v_dual_mov_b32 v51, v19
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v26 :: v_dual_mov_b32 v37, v25
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v24 :: v_dual_mov_b32 v38, v23
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v22 :: v_dual_mov_b32 v49, v21
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v20 :: v_dual_mov_b32 v50, v19
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v18 :: v_dual_mov_b32 v53, v17
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v16 :: v_dual_mov_b32 v55, v15
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v65, v14 :: v_dual_mov_b32 v64, v13
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v12 :: v_dual_mov_b32 v67, v11
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v69, v10 :: v_dual_mov_b32 v68, v9
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v65, v14 :: v_dual_mov_b32 v66, v13
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v69, v12 :: v_dual_mov_b32 v64, v11
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v67, v10 :: v_dual_mov_b32 v68, v9
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v8 :: v_dual_mov_b32 v71, v7
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v6 :: v_dual_mov_b32 v81, v5
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v4 :: v_dual_mov_b32 v83, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v6 :: v_dual_mov_b32 v83, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v5 :: v_dual_mov_b32 v81, v3
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v85, v2 :: v_dual_mov_b32 v84, v1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
@@ -86566,96 +86494,96 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB58_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v86, v84, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v85, v83, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v82, v81, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v80, v71, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v66, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v85, v81, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v83, v80, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v82, v71, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v69, v66, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v65, v55, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v54, v53, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v70, v68, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v69, v67, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v52, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v50, v48, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v49, v39, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v38, v36, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v37, v35, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v67, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v52, v50, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v51, v49, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v48, v38, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v39, v37, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v36, v35, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v7, 16, v6
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v9, 16, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v11, 16, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v34, v32, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v34, v33, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v33, v127, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v126, v124, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v32, v124, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v127, v126, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v125, v123, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v122, v121, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v120, v111, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v110, v108, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v109, v107, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v106, v104, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v105, v95, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v120, v110, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v111, v109, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v108, v106, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v107, v105, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v104, v95, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v10, 16, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v14, 16, v13
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v16, 16, v15
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v94, v92, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v93, v91, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v90, v88, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v91, v88, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v93, v90, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v89, v79, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v78, v77, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v76, v75, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v74, v72, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v75, v72, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v76, v74, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v73, v63, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v62, v60, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v61, v59, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v62, v61, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v60, v59, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v15, 16, v14
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v17, 16, v16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v19, 16, v18
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v21, 16, v20
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v58, v56, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v57, v47, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v46, v44, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v45, v43, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v58, v57, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v56, v46, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v47, v45, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v44, v43, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v42, v41, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v40, v183, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v182, v180, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v181, v179, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v178, v176, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v40, v182, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v183, v181, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v179, v176, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v180, v178, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v177, v167, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v18, 16, v17
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v20, 16, v19
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v22, 16, v21
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v24, 16, v23
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v26, 16, v25
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v166, v164, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v165, v163, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v162, v160, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v161, v151, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v150, v149, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v148, v147, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v166, v165, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v164, v162, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v163, v160, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v151, v148, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v161, v150, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v149, v147, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v146, v144, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v145, v135, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v30, v134, v132, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v135, v132, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v145, v134, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v31, v133, v131, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v23, 16, v22
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v25, 16, v24
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v27, 16, v26
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v29, 16, v28
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v31, 16, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v130, v128, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v129, v119, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v118, v116, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v30, v117, v114, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v115, v113, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v130, v129, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v128, v117, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v119, v118, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v115, v113, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v116, v114, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v32, v112, v102, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v33, v103, v100, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v34, v101, v98, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v35, v99, v96, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v34, v99, v96, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v35, v101, v98, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v36, v97, v87, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v28, 16, v27
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v30, 16, v29
@@ -86665,129 +86593,129 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr124
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr127
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr126
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr124
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr125
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr123
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr122
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr121
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr120
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr111
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr110
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr108
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr111
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr109
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr107
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr108
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr106
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr104
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr107
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr105
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr104
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr95
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr94
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr92
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr93
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr91
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr90
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr88
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr93
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr90
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr89
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr79
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr78
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr77
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr76
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr75
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr74
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr72
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr76
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr74
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr73
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr63
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr62
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr60
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr61
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr60
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr59
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr58
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr56
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr57
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr47
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr56
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr46
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr44
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr47
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr45
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr44
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr43
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr42
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr41
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr40
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr183
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr182
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr180
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr183
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr181
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr179
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr178
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr176
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr180
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr178
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr177
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr167
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr166
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr164
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr165
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr163
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr164
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr162
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr163
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr160
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr161
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr151
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr148
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr161
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr150
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr149
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr148
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr147
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr146
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr144
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr145
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr133
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
; GFX11-FAKE16-NEXT: .LBB58_2: ; %Flow
@@ -86795,422 +86723,392 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB58_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v86, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v83, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v85, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v84
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v83
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v84
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v82, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v80
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v80, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v81
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v81
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v71
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v71
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v6, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v69, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v69, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v70, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v67
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v66
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v65, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v68
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v66, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v54, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v65, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v64
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v68
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v67, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v55
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v64
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v54, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v48, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v39, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v53
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v52, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v51
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v50, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v49, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v39
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v51, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v50
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v48
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v38, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v37, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v49
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v36, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v126
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v38
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v37
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v9, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v36
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v35
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v125, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v35
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v34, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v8
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v127, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v34, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v33, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v32
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v33
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v32, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v127
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v126, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v125, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v8, 16, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v120, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v124
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v123
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v122, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v12, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v13
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v123
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v121
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v122, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v120, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v111
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v110, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v109, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v107
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v108
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v121
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v111, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v107, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v10, 16, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v110
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v106, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v105, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v109
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v108, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v90
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v13, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v106
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v105
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v104
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v95
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v16, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v94, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v104, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v11, 16, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v95
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v94, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v11, 16, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v93, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v92
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v91, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v91
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v90, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v89, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v89, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v17
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v16
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v88
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v79
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v78, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v17, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v18
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v79
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v16, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v18
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v77
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v77
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v18, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v78, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v16
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v76, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v75
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v74, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v73, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v63
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v76, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v13, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v15, 16, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v16, 16, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v75, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v20
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v74
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v73, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v72
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v62, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v18
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v72
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v62, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v61, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v63
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v19, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v61
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v18, v17
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v20
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v60
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v21
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v59
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v60, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v15
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v17
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v21, v20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v16
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v20
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v59
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v58, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v17, 16, v16
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v19
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, v58, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v17, v20
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v57, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v20, v19
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v57
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v56, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v47, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v56
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v47
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v46, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v16, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v45, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v20, v19
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v21, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v44
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v18
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v43
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v42, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v17
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v20
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v46
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v45
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v44, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v20, v19
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v22, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v43
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v42, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v40, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v21, v20
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v22, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v23
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v22
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v41
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, v183, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v20
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v22, v21
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v40, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v19, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v20
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v183
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v182, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, v181, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v179
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v22, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v23
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v180
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v178, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, v177, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v182
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v181
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v18, 16, v17
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v20, 16, v19
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v23, v22
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v24, v19
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v25
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v176
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v26
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v167
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v22
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v180, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v179, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v25, v24
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v178
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v177, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v20
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v176
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v24, v23
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v26, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v19
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v20, v21
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v23
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, 0x300, v24
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, v166, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v22, v25
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v165, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v164
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v163
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v162, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v21, v23
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v161, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, v166, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v24, v20
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v25
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v167
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v27, v23
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v26
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v165
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v20
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v25, v24
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v26, v22
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v27
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v160
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v23
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v151
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v150, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v24
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v19
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, 0x300, v23
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v22
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v26, v25
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v28, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff, v20
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v24
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v23, 16, v25
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v163, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v161, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v22, 16, v21
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v26
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, v164, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v24, 16, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v160
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v151, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v25
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v150
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v149, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v26
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v162
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v27, v23
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v28
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v149
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v24
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v28
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v148
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v29, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v30
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v147
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v26, v24
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v28, v27
; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v30, v29
; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, 0x300, v23
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v27, v26
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v148, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v24, v22
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v25
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v27
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v147
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v24
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v146, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v24, v23
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, v145, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v135
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v27, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v28
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v144
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v134, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, v133, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff, v23
; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v26
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v24, 16, v22
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v134
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v27, 16, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v28
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v144
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v135, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v26, 16, v23
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, v145, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v133, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v27, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v28
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v132
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v26
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, v130, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v25
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v32, v115, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v28, v27
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v29, v24
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v30
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v132
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v31
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v131
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v29, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v30
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v131
; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v24
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v29, v28
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v31, v30
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff, v27
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v24
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v25, v26
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v28
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v29
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v29, v130, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v27, v30
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v129, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v26
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v33, 8, v117
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v30, v29
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v31
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v129
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v27, 16, v25
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v119, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v26
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v29
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v128
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v27
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v119
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v26, v28
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v118, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v28
; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v30, v29
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v117, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v128, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v27
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v118
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v28, 16, v26
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v29
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v30
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v116, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v31, v27
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, v115, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v28
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v32, 8, v116
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v34, 8, v114
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xff, v32
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v32, 8, v113
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v30
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v33, 8, v114
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xff, v31
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v34, 8, v113
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v32, v28
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v33, v29
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v36, 8, v100
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v32, v31
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v34, v30
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v27
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v103, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v34, v101, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v32, v112, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v33, v30
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v33, v103, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v35, v101, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v36, v99, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v38, v97, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v34, v31
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v37, v99, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v38, 8, v98
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xff, v34
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v39, v97, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xff, v32
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v34, 8, v102
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xff, v33
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v37, 8, v100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xff, v35
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v39, 8, v98
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xff, v36
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v48, 8, v96
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xff, v38
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v49, 8, v87
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, v34, v32
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, v37, v33
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, v39, v35
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, v48, v36
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, v49, v38
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v29, 0x300, v29
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v28
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v35, 8, v102
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v36, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xff, v37
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v37, 8, v96
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, v38, v34
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xff, v39
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v39, 8, v87
; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, 0x300, v30
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, v35, v32
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, v37, v36
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v34, 0x300, v34
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, v39, v38
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v28
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v29, 0x300, v29
; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, 0x300, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v30
; GFX11-FAKE16-NEXT: v_add_nc_u16 v32, 0x300, v32
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v33, 0x300, v33
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v34, 0x300, v34
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff, v27
; GFX11-FAKE16-NEXT: v_add_nc_u16 v35, 0x300, v35
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v34
; GFX11-FAKE16-NEXT: v_add_nc_u16 v36, 0x300, v36
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff, v29
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v28
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff, v31
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v32
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v33
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v34
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff, v35
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v36
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v29, v27
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v28, v30
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v31, v32
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v33, v34
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v35, v36
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v29, 16, v28
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v31, 16, v33
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v32, 16, v30
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v35, 16, v37
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v36, 16, v34
; GFX11-FAKE16-NEXT: .LBB58_4: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload
@@ -117236,14 +117134,14 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:388
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32
@@ -117260,16 +117158,16 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:84
; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:80
; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:76
-; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:72
-; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:68
+; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:72
+; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:68
; GFX9-NEXT: buffer_load_ushort v38, off, s[0:3], s32 offset:64
; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:60
-; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:56
-; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:52
+; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:56
+; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:52
; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:48
; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:44
-; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:40
-; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:36
+; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:40
+; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:36
; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:32
; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:28
; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:24
@@ -117377,31 +117275,31 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:364
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:188
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:360
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:184
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:356
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:180
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:352
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:176
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:348
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:172
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
@@ -117413,13 +117311,13 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:340
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:164
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:336
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:160
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
@@ -117481,8 +117379,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB74_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0xc0c0004
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v10, v55, v32, s6
@@ -117505,19 +117403,19 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s6
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_perm_b32 v16, v43, v16, s6
; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v1, v2, v1, s6
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s6
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
@@ -117580,11 +117478,11 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_perm_b32 v9, v39, v40, s6
; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; GFX9-NEXT: v_perm_b32 v10, v62, v63, s6
+; GFX9-NEXT: v_perm_b32 v10, v63, v62, s6
; GFX9-NEXT: v_lshl_or_b32 v10, v11, 16, v10
-; GFX9-NEXT: v_perm_b32 v11, v59, v54, s6
+; GFX9-NEXT: v_perm_b32 v11, v54, v59, s6
; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
-; GFX9-NEXT: v_perm_b32 v12, v58, v37, s6
+; GFX9-NEXT: v_perm_b32 v12, v37, v58, s6
; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; GFX9-NEXT: v_perm_b32 v13, v47, v52, s6
; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
@@ -117600,12 +117498,12 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr40
-; GFX9-NEXT: ; implicit-def: $vgpr62
; GFX9-NEXT: ; implicit-def: $vgpr63
-; GFX9-NEXT: ; implicit-def: $vgpr59
+; GFX9-NEXT: ; implicit-def: $vgpr62
; GFX9-NEXT: ; implicit-def: $vgpr54
-; GFX9-NEXT: ; implicit-def: $vgpr58
+; GFX9-NEXT: ; implicit-def: $vgpr59
; GFX9-NEXT: ; implicit-def: $vgpr37
+; GFX9-NEXT: ; implicit-def: $vgpr58
; GFX9-NEXT: ; implicit-def: $vgpr47
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr33
@@ -117628,21 +117526,21 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v18, v19, v18, s6
; GFX9-NEXT: v_lshl_or_b32 v17, v18, 16, v17
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v18, v19, v18, s6
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v19, v20, v19, s6
; GFX9-NEXT: v_lshl_or_b32 v18, v19, 16, v18
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v19, v20, v19, s6
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v20, v21, v20, s6
; GFX9-NEXT: v_lshl_or_b32 v19, v20, 16, v19
@@ -117951,23 +117849,22 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB74_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; GFX9-NEXT: s_movk_i32 s6, 0x300
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
@@ -117990,19 +117887,16 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(24)
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: s_waitcnt vmcnt(22)
-; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v8
; GFX9-NEXT: s_waitcnt vmcnt(21)
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v2
; GFX9-NEXT: s_waitcnt vmcnt(20)
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3
-; GFX9-NEXT: s_waitcnt vmcnt(19)
-; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4
+; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v8
; GFX9-NEXT: v_lshlrev_b16_e32 v18, 8, v18
-; GFX9-NEXT: s_waitcnt vmcnt(18)
-; GFX9-NEXT: v_lshlrev_b16_e32 v21, 8, v21
+; GFX9-NEXT: s_waitcnt vmcnt(17)
+; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4
; GFX9-NEXT: s_waitcnt vmcnt(16)
; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v17
; GFX9-NEXT: s_waitcnt vmcnt(15)
@@ -118015,10 +117909,10 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v6
; GFX9-NEXT: s_waitcnt vmcnt(11)
; GFX9-NEXT: v_lshlrev_b16_e32 v20, 8, v20
-; GFX9-NEXT: s_waitcnt vmcnt(10)
-; GFX9-NEXT: v_lshlrev_b16_e32 v22, 8, v22
+; GFX9-NEXT: v_lshlrev_b16_e32 v21, 8, v21
; GFX9-NEXT: s_waitcnt vmcnt(9)
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v7
+; GFX9-NEXT: v_lshlrev_b16_e32 v22, 8, v22
; GFX9-NEXT: s_waitcnt vmcnt(8)
; GFX9-NEXT: v_lshlrev_b16_e32 v23, 8, v23
; GFX9-NEXT: v_lshlrev_b16_e32 v24, 8, v24
@@ -118040,19 +117934,19 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v1, 3, v1
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v2, 3, v2
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v3, 3, v3
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
@@ -118068,8 +117962,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v3, 3, v3
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -118082,8 +117976,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v4, 3, v4
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -118096,8 +117990,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v5, 3, v5
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -118110,8 +118004,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v6, 3, v6
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -118124,8 +118018,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v7, 3, v7
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -118138,72 +118032,72 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v8, 3, v8
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_add_u16_e32 v8, 3, v35
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v42
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 3, v41
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
-; GFX9-NEXT: v_add_u16_sdwa v9, v9, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_add_u16_e32 v9, 3, v39
; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v40
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v10, 3, v55
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
-; GFX9-NEXT: v_add_u16_sdwa v10, v10, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
-; GFX9-NEXT: v_add_u16_e32 v10, 3, v62
-; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v63
+; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; GFX9-NEXT: v_add_u16_e32 v10, 3, v63
+; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v62
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 3, v61
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
-; GFX9-NEXT: v_add_u16_sdwa v11, v11, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX9-NEXT: v_add_u16_e32 v11, 3, v59
-; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v54
+; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
+; GFX9-NEXT: v_lshl_or_b32 v10, v11, 16, v10
+; GFX9-NEXT: v_add_u16_e32 v11, 3, v54
+; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v59
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v12, 3, v53
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
-; GFX9-NEXT: v_add_u16_sdwa v12, v12, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
-; GFX9-NEXT: v_add_u16_e32 v12, 3, v58
-; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v37
+; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX9-NEXT: v_add_u16_e32 v12, 3, v37
+; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v58
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v13, 3, v57
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
-; GFX9-NEXT: v_add_u16_sdwa v13, v13, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v12, v12, v13
+; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
+; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; GFX9-NEXT: v_add_u16_e32 v13, 3, v47
; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v52
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v14, 3, v51
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
-; GFX9-NEXT: v_add_u16_sdwa v14, v14, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; GFX9-NEXT: v_add_u16_e32 v14, 3, v33
; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v46
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v15, 3, v45
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
-; GFX9-NEXT: v_add_u16_sdwa v15, v15, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v14, v14, v15
+; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
+; GFX9-NEXT: v_lshl_or_b32 v14, v15, 16, v14
; GFX9-NEXT: v_add_u16_e32 v15, 3, v49
; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v44
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v16, 3, v43
; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
-; GFX9-NEXT: v_add_u16_sdwa v16, v16, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v15, v15, v16
+; GFX9-NEXT: v_add_u16_e32 v16, 0x300, v16
+; GFX9-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
@@ -118219,8 +118113,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v17, 3, v17
; GFX9-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v17, v17, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v16, v16, v17
+; GFX9-NEXT: v_add_u16_e32 v17, 0x300, v17
+; GFX9-NEXT: v_lshl_or_b32 v16, v17, 16, v16
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -118233,10 +118127,10 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v18, 3, v18
; GFX9-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v18, v18, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v17, v17, v18
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u16_e32 v18, 0x300, v18
+; GFX9-NEXT: v_lshl_or_b32 v17, v18, 16, v17
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v18, 3, v18
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -118247,22 +118141,22 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v19, 3, v19
; GFX9-NEXT: v_or_b32_sdwa v19, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v19, v19, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v18, v18, v19
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u16_e32 v19, 0x300, v19
+; GFX9-NEXT: v_lshl_or_b32 v18, v19, 16, v18
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u16_e32 v19, 3, v19
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v20, 8, v20
; GFX9-NEXT: v_or_b32_sdwa v19, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v19, 0x300, v19
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v20, 3, v20
; GFX9-NEXT: v_or_b32_sdwa v20, v21, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v20, v20, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v19, v19, v20
+; GFX9-NEXT: v_add_u16_e32 v20, 0x300, v20
+; GFX9-NEXT: v_lshl_or_b32 v19, v20, 16, v19
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -118275,8 +118169,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v21, 3, v21
; GFX9-NEXT: v_or_b32_sdwa v21, v22, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v21, v21, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v20, v20, v21
+; GFX9-NEXT: v_add_u16_e32 v21, 0x300, v21
+; GFX9-NEXT: v_lshl_or_b32 v20, v21, 16, v20
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -118289,8 +118183,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v22, 3, v22
; GFX9-NEXT: v_or_b32_sdwa v22, v23, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v22, v22, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v21, v21, v22
+; GFX9-NEXT: v_add_u16_e32 v22, 0x300, v22
+; GFX9-NEXT: v_lshl_or_b32 v21, v22, 16, v21
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -118303,8 +118197,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v23, 3, v23
; GFX9-NEXT: v_or_b32_sdwa v23, v24, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v23, v23, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v22, v22, v23
+; GFX9-NEXT: v_add_u16_e32 v23, 0x300, v23
+; GFX9-NEXT: v_lshl_or_b32 v22, v23, 16, v22
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -118317,8 +118211,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v24, 3, v24
; GFX9-NEXT: v_or_b32_sdwa v24, v25, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v24, v24, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v23, v23, v24
+; GFX9-NEXT: v_add_u16_e32 v24, 0x300, v24
+; GFX9-NEXT: v_lshl_or_b32 v23, v24, 16, v23
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -118331,8 +118225,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v25, 3, v25
; GFX9-NEXT: v_or_b32_sdwa v25, v26, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v25, v25, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v24, v24, v25
+; GFX9-NEXT: v_add_u16_e32 v25, 0x300, v25
+; GFX9-NEXT: v_lshl_or_b32 v24, v25, 16, v24
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -118345,8 +118239,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v26, 3, v26
; GFX9-NEXT: v_or_b32_sdwa v26, v27, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v26, v26, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v25, v25, v26
+; GFX9-NEXT: v_add_u16_e32 v26, 0x300, v26
+; GFX9-NEXT: v_lshl_or_b32 v25, v26, 16, v25
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -118359,8 +118253,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v27, 3, v27
; GFX9-NEXT: v_or_b32_sdwa v27, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v27, v27, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v26, v26, v27
+; GFX9-NEXT: v_add_u16_e32 v27, 0x300, v27
+; GFX9-NEXT: v_lshl_or_b32 v26, v27, 16, v26
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -118373,8 +118267,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v28, 3, v28
; GFX9-NEXT: v_or_b32_sdwa v28, v29, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v28, v28, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v27, v27, v28
+; GFX9-NEXT: v_add_u16_e32 v28, 0x300, v28
+; GFX9-NEXT: v_lshl_or_b32 v27, v28, 16, v27
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -118387,8 +118281,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v29, 3, v29
; GFX9-NEXT: v_or_b32_sdwa v29, v30, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v29, v29, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v28, v28, v29
+; GFX9-NEXT: v_add_u16_e32 v29, 0x300, v29
+; GFX9-NEXT: v_lshl_or_b32 v28, v29, 16, v28
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -118401,8 +118295,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v30, 3, v30
; GFX9-NEXT: v_or_b32_sdwa v30, v31, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v30, v30, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v29, v29, v30
+; GFX9-NEXT: v_add_u16_e32 v30, 0x300, v30
+; GFX9-NEXT: v_lshl_or_b32 v29, v30, 16, v29
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -118415,8 +118309,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v31, 3, v31
; GFX9-NEXT: v_or_b32_sdwa v31, v32, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v31, v31, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v30, v30, v31
+; GFX9-NEXT: v_add_u16_e32 v31, 0x300, v31
+; GFX9-NEXT: v_lshl_or_b32 v30, v31, 16, v30
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -118427,8 +118321,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u16_e32 v32, 3, v36
; GFX9-NEXT: v_or_b32_sdwa v32, v33, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v31, 0x300, v31
-; GFX9-NEXT: v_add_u16_sdwa v32, v32, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v31, v31, v32
+; GFX9-NEXT: v_add_u16_e32 v32, 0x300, v32
+; GFX9-NEXT: v_lshl_or_b32 v31, v32, 16, v31
; GFX9-NEXT: .LBB74_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
@@ -119398,119 +119292,119 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:384
; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:380
-; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:376
-; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:372
-; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:368
-; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:364
+; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:376
+; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:372
+; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:368
+; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:364
; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:360
; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:356
; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:352
; GFX11-FAKE16-NEXT: scratch_load_u16 v112, off, s32 offset:348
-; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:344
-; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:340
-; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:336
-; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:332
-; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:328
-; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:324
-; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32 offset:320
-; GFX11-FAKE16-NEXT: scratch_load_u16 v129, off, s32 offset:316
-; GFX11-FAKE16-NEXT: scratch_load_u16 v128, off, s32 offset:312
+; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:344
+; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:340
+; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:336
+; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:332
+; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:328
+; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32 offset:324
+; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:320
+; GFX11-FAKE16-NEXT: scratch_load_u16 v128, off, s32 offset:316
+; GFX11-FAKE16-NEXT: scratch_load_u16 v129, off, s32 offset:312
; GFX11-FAKE16-NEXT: scratch_load_u16 v130, off, s32 offset:308
; GFX11-FAKE16-NEXT: scratch_load_u16 v131, off, s32 offset:304
; GFX11-FAKE16-NEXT: scratch_load_u16 v133, off, s32 offset:300
-; GFX11-FAKE16-NEXT: scratch_load_u16 v132, off, s32 offset:296
-; GFX11-FAKE16-NEXT: scratch_load_u16 v134, off, s32 offset:292
-; GFX11-FAKE16-NEXT: scratch_load_u16 v135, off, s32 offset:288
-; GFX11-FAKE16-NEXT: scratch_load_u16 v145, off, s32 offset:284
+; GFX11-FAKE16-NEXT: scratch_load_u16 v134, off, s32 offset:296
+; GFX11-FAKE16-NEXT: scratch_load_u16 v145, off, s32 offset:292
+; GFX11-FAKE16-NEXT: scratch_load_u16 v132, off, s32 offset:288
+; GFX11-FAKE16-NEXT: scratch_load_u16 v135, off, s32 offset:284
; GFX11-FAKE16-NEXT: scratch_load_u16 v144, off, s32 offset:280
; GFX11-FAKE16-NEXT: scratch_load_u16 v146, off, s32 offset:276
; GFX11-FAKE16-NEXT: scratch_load_u16 v147, off, s32 offset:272
-; GFX11-FAKE16-NEXT: scratch_load_u16 v148, off, s32 offset:268
-; GFX11-FAKE16-NEXT: scratch_load_u16 v149, off, s32 offset:264
-; GFX11-FAKE16-NEXT: scratch_load_u16 v150, off, s32 offset:260
+; GFX11-FAKE16-NEXT: scratch_load_u16 v149, off, s32 offset:268
+; GFX11-FAKE16-NEXT: scratch_load_u16 v150, off, s32 offset:264
+; GFX11-FAKE16-NEXT: scratch_load_u16 v161, off, s32 offset:260
; GFX11-FAKE16-NEXT: s_clause 0x1f
-; GFX11-FAKE16-NEXT: scratch_load_u16 v151, off, s32 offset:256
-; GFX11-FAKE16-NEXT: scratch_load_u16 v161, off, s32 offset:252
+; GFX11-FAKE16-NEXT: scratch_load_u16 v148, off, s32 offset:256
+; GFX11-FAKE16-NEXT: scratch_load_u16 v151, off, s32 offset:252
; GFX11-FAKE16-NEXT: scratch_load_u16 v160, off, s32 offset:248
-; GFX11-FAKE16-NEXT: scratch_load_u16 v162, off, s32 offset:244
-; GFX11-FAKE16-NEXT: scratch_load_u16 v163, off, s32 offset:240
-; GFX11-FAKE16-NEXT: scratch_load_u16 v165, off, s32 offset:236
-; GFX11-FAKE16-NEXT: scratch_load_u16 v164, off, s32 offset:232
+; GFX11-FAKE16-NEXT: scratch_load_u16 v163, off, s32 offset:244
+; GFX11-FAKE16-NEXT: scratch_load_u16 v162, off, s32 offset:240
+; GFX11-FAKE16-NEXT: scratch_load_u16 v164, off, s32 offset:236
+; GFX11-FAKE16-NEXT: scratch_load_u16 v165, off, s32 offset:232
; GFX11-FAKE16-NEXT: scratch_load_u16 v166, off, s32 offset:228
; GFX11-FAKE16-NEXT: scratch_load_u16 v167, off, s32 offset:224
; GFX11-FAKE16-NEXT: scratch_load_u16 v177, off, s32 offset:220
-; GFX11-FAKE16-NEXT: scratch_load_u16 v176, off, s32 offset:216
-; GFX11-FAKE16-NEXT: scratch_load_u16 v178, off, s32 offset:212
-; GFX11-FAKE16-NEXT: scratch_load_u16 v179, off, s32 offset:208
-; GFX11-FAKE16-NEXT: scratch_load_u16 v181, off, s32 offset:204
-; GFX11-FAKE16-NEXT: scratch_load_u16 v180, off, s32 offset:200
-; GFX11-FAKE16-NEXT: scratch_load_u16 v182, off, s32 offset:196
-; GFX11-FAKE16-NEXT: scratch_load_u16 v183, off, s32 offset:192
+; GFX11-FAKE16-NEXT: scratch_load_u16 v178, off, s32 offset:216
+; GFX11-FAKE16-NEXT: scratch_load_u16 v180, off, s32 offset:212
+; GFX11-FAKE16-NEXT: scratch_load_u16 v176, off, s32 offset:208
+; GFX11-FAKE16-NEXT: scratch_load_u16 v179, off, s32 offset:204
+; GFX11-FAKE16-NEXT: scratch_load_u16 v181, off, s32 offset:200
+; GFX11-FAKE16-NEXT: scratch_load_u16 v183, off, s32 offset:196
+; GFX11-FAKE16-NEXT: scratch_load_u16 v182, off, s32 offset:192
; GFX11-FAKE16-NEXT: scratch_load_u16 v40, off, s32 offset:188
; GFX11-FAKE16-NEXT: scratch_load_u16 v41, off, s32 offset:184
; GFX11-FAKE16-NEXT: scratch_load_u16 v42, off, s32 offset:180
; GFX11-FAKE16-NEXT: scratch_load_u16 v43, off, s32 offset:176
-; GFX11-FAKE16-NEXT: scratch_load_u16 v45, off, s32 offset:172
-; GFX11-FAKE16-NEXT: scratch_load_u16 v44, off, s32 offset:168
-; GFX11-FAKE16-NEXT: scratch_load_u16 v46, off, s32 offset:164
-; GFX11-FAKE16-NEXT: scratch_load_u16 v47, off, s32 offset:160
-; GFX11-FAKE16-NEXT: scratch_load_u16 v57, off, s32 offset:156
-; GFX11-FAKE16-NEXT: scratch_load_u16 v56, off, s32 offset:152
+; GFX11-FAKE16-NEXT: scratch_load_u16 v44, off, s32 offset:172
+; GFX11-FAKE16-NEXT: scratch_load_u16 v45, off, s32 offset:168
+; GFX11-FAKE16-NEXT: scratch_load_u16 v47, off, s32 offset:164
+; GFX11-FAKE16-NEXT: scratch_load_u16 v46, off, s32 offset:160
+; GFX11-FAKE16-NEXT: scratch_load_u16 v56, off, s32 offset:156
+; GFX11-FAKE16-NEXT: scratch_load_u16 v57, off, s32 offset:152
; GFX11-FAKE16-NEXT: scratch_load_u16 v58, off, s32 offset:148
; GFX11-FAKE16-NEXT: scratch_load_u16 v59, off, s32 offset:144
-; GFX11-FAKE16-NEXT: scratch_load_u16 v61, off, s32 offset:140
-; GFX11-FAKE16-NEXT: scratch_load_u16 v60, off, s32 offset:136
+; GFX11-FAKE16-NEXT: scratch_load_u16 v60, off, s32 offset:140
+; GFX11-FAKE16-NEXT: scratch_load_u16 v61, off, s32 offset:136
; GFX11-FAKE16-NEXT: scratch_load_u16 v62, off, s32 offset:132
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_load_u16 v63, off, s32 offset:128
; GFX11-FAKE16-NEXT: scratch_load_u16 v73, off, s32 offset:124
-; GFX11-FAKE16-NEXT: scratch_load_u16 v72, off, s32 offset:120
-; GFX11-FAKE16-NEXT: scratch_load_u16 v74, off, s32 offset:116
-; GFX11-FAKE16-NEXT: scratch_load_u16 v75, off, s32 offset:112
-; GFX11-FAKE16-NEXT: scratch_load_u16 v76, off, s32 offset:108
+; GFX11-FAKE16-NEXT: scratch_load_u16 v74, off, s32 offset:120
+; GFX11-FAKE16-NEXT: scratch_load_u16 v76, off, s32 offset:116
+; GFX11-FAKE16-NEXT: scratch_load_u16 v72, off, s32 offset:112
+; GFX11-FAKE16-NEXT: scratch_load_u16 v75, off, s32 offset:108
; GFX11-FAKE16-NEXT: scratch_load_u16 v77, off, s32 offset:104
; GFX11-FAKE16-NEXT: scratch_load_u16 v78, off, s32 offset:100
; GFX11-FAKE16-NEXT: scratch_load_u16 v79, off, s32 offset:96
; GFX11-FAKE16-NEXT: scratch_load_u16 v89, off, s32 offset:92
-; GFX11-FAKE16-NEXT: scratch_load_u16 v88, off, s32 offset:88
-; GFX11-FAKE16-NEXT: scratch_load_u16 v90, off, s32 offset:84
-; GFX11-FAKE16-NEXT: scratch_load_u16 v91, off, s32 offset:80
-; GFX11-FAKE16-NEXT: scratch_load_u16 v93, off, s32 offset:76
+; GFX11-FAKE16-NEXT: scratch_load_u16 v90, off, s32 offset:88
+; GFX11-FAKE16-NEXT: scratch_load_u16 v93, off, s32 offset:84
+; GFX11-FAKE16-NEXT: scratch_load_u16 v88, off, s32 offset:80
+; GFX11-FAKE16-NEXT: scratch_load_u16 v91, off, s32 offset:76
; GFX11-FAKE16-NEXT: scratch_load_u16 v92, off, s32 offset:72
; GFX11-FAKE16-NEXT: scratch_load_u16 v94, off, s32 offset:68
; GFX11-FAKE16-NEXT: scratch_load_u16 v95, off, s32 offset:64
-; GFX11-FAKE16-NEXT: scratch_load_u16 v105, off, s32 offset:60
-; GFX11-FAKE16-NEXT: scratch_load_u16 v104, off, s32 offset:56
-; GFX11-FAKE16-NEXT: scratch_load_u16 v106, off, s32 offset:52
-; GFX11-FAKE16-NEXT: scratch_load_u16 v107, off, s32 offset:48
-; GFX11-FAKE16-NEXT: scratch_load_u16 v109, off, s32 offset:44
-; GFX11-FAKE16-NEXT: scratch_load_u16 v108, off, s32 offset:40
-; GFX11-FAKE16-NEXT: scratch_load_u16 v110, off, s32 offset:36
-; GFX11-FAKE16-NEXT: scratch_load_u16 v111, off, s32 offset:32
+; GFX11-FAKE16-NEXT: scratch_load_u16 v104, off, s32 offset:60
+; GFX11-FAKE16-NEXT: scratch_load_u16 v105, off, s32 offset:56
+; GFX11-FAKE16-NEXT: scratch_load_u16 v107, off, s32 offset:52
+; GFX11-FAKE16-NEXT: scratch_load_u16 v106, off, s32 offset:48
+; GFX11-FAKE16-NEXT: scratch_load_u16 v108, off, s32 offset:44
+; GFX11-FAKE16-NEXT: scratch_load_u16 v109, off, s32 offset:40
+; GFX11-FAKE16-NEXT: scratch_load_u16 v111, off, s32 offset:36
+; GFX11-FAKE16-NEXT: scratch_load_u16 v110, off, s32 offset:32
; GFX11-FAKE16-NEXT: scratch_load_u16 v120, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_u16 v121, off, s32 offset:24
; GFX11-FAKE16-NEXT: scratch_load_u16 v122, off, s32 offset:20
; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:388
; GFX11-FAKE16-NEXT: scratch_load_u16 v123, off, s32 offset:16
; GFX11-FAKE16-NEXT: scratch_load_u16 v125, off, s32 offset:12
-; GFX11-FAKE16-NEXT: scratch_load_u16 v124, off, s32 offset:8
+; GFX11-FAKE16-NEXT: scratch_load_u16 v126, off, s32 offset:8
; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: scratch_load_u16 v126, off, s32 offset:4
-; GFX11-FAKE16-NEXT: scratch_load_u16 v127, off, s32
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v30 :: v_dual_mov_b32 v32, v29
+; GFX11-FAKE16-NEXT: scratch_load_u16 v127, off, s32 offset:4
+; GFX11-FAKE16-NEXT: scratch_load_u16 v124, off, s32
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, v30 :: v_dual_mov_b32 v33, v29
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, v28 :: v_dual_mov_b32 v35, v27
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v26 :: v_dual_mov_b32 v36, v25
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, v24 :: v_dual_mov_b32 v39, v23
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, v22 :: v_dual_mov_b32 v48, v21
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, v20 :: v_dual_mov_b32 v51, v19
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, v26 :: v_dual_mov_b32 v37, v25
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v24 :: v_dual_mov_b32 v38, v23
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v22 :: v_dual_mov_b32 v49, v21
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v20 :: v_dual_mov_b32 v50, v19
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v18 :: v_dual_mov_b32 v53, v17
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v16 :: v_dual_mov_b32 v55, v15
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v65, v14 :: v_dual_mov_b32 v64, v13
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, v12 :: v_dual_mov_b32 v67, v11
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v69, v10 :: v_dual_mov_b32 v68, v9
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v65, v14 :: v_dual_mov_b32 v66, v13
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v69, v12 :: v_dual_mov_b32 v64, v11
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v67, v10 :: v_dual_mov_b32 v68, v9
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, v8 :: v_dual_mov_b32 v71, v7
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v6 :: v_dual_mov_b32 v81, v5
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v4 :: v_dual_mov_b32 v83, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, v6 :: v_dual_mov_b32 v83, v4
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, v5 :: v_dual_mov_b32 v81, v3
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v85, v2 :: v_dual_mov_b32 v84, v1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
@@ -119521,96 +119415,96 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB74_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v86, v84, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v85, v83, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v82, v81, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v80, v71, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v66, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v85, v81, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v83, v80, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v82, v71, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v69, v66, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v65, v55, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v54, v53, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v70, v68, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v69, v67, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v52, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v50, v48, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v49, v39, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v38, v36, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v37, v35, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v67, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v52, v50, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v51, v49, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v48, v38, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v39, v37, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v36, v35, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v7, 16, v6
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v9, 16, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v11, 16, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v34, v32, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v34, v33, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v33, v127, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v126, v124, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v32, v124, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v127, v126, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v125, v123, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v122, v121, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v120, v111, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v110, v108, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v109, v107, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v106, v104, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v105, v95, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v120, v110, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v111, v109, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v108, v106, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v107, v105, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v104, v95, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v10, 16, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v14, 16, v13
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v16, 16, v15
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v94, v92, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v93, v91, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v90, v88, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v91, v88, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v93, v90, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v89, v79, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v78, v77, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v76, v75, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v74, v72, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v75, v72, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v76, v74, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v73, v63, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v62, v60, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v61, v59, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v62, v61, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v60, v59, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v15, 16, v14
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v17, 16, v16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v19, 16, v18
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v21, 16, v20
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v58, v56, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v57, v47, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v46, v44, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v45, v43, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v58, v57, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v56, v46, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v47, v45, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v44, v43, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v42, v41, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v40, v183, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v182, v180, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v181, v179, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v178, v176, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v40, v182, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v183, v181, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v179, v176, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v180, v178, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v177, v167, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v18, 16, v17
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v20, 16, v19
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v22, 16, v21
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v24, 16, v23
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v26, 16, v25
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v166, v164, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v165, v163, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v162, v160, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v161, v151, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v150, v149, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v148, v147, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v166, v165, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v164, v162, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v163, v160, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v151, v148, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v161, v150, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v149, v147, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v146, v144, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v145, v135, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v30, v134, v132, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v135, v132, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v145, v134, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v31, v133, v131, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v23, 16, v22
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v25, 16, v24
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v27, 16, v26
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v29, 16, v28
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v31, 16, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v130, v128, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v129, v119, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v118, v116, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v30, v117, v114, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v115, v113, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v130, v129, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v128, v117, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v119, v118, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v115, v113, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v116, v114, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v32, v112, v102, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v33, v103, v100, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v34, v101, v98, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v35, v99, v96, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v34, v99, v96, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v35, v101, v98, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v36, v97, v87, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v28, 16, v27
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v30, 16, v29
@@ -119620,129 +119514,129 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr124
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr127
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr126
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr124
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr125
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr123
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr122
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr121
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr120
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr111
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr110
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr108
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr111
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr109
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr107
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr108
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr106
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr104
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr107
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr105
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr104
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr95
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr94
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr92
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr93
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr91
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr90
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr88
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr93
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr90
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr89
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr79
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr78
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr77
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr76
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr75
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr74
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr72
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr76
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr74
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr73
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr63
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr62
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr60
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr61
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr60
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr59
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr58
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr56
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr57
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr47
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr56
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr46
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr44
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr47
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr45
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr44
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr43
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr42
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr41
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr40
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr183
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr182
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr180
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr183
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr181
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr179
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr178
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr176
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr180
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr178
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr177
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr167
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr166
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr164
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr165
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr163
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr164
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr162
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr163
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr160
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr161
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr151
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr148
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr161
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr150
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr149
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr148
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr147
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr146
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr144
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr145
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr135
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr132
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr145
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr134
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr133
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr131
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr130
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr129
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr128
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
; GFX11-FAKE16-NEXT: .LBB74_2: ; %Flow
@@ -119750,422 +119644,392 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB74_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v86, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v83, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v85, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v84
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v83
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v84
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v82, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v80
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v80, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v81
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v81
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v71
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v71
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v6, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v69, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v69, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v70, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v67
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v66
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v65, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v68
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v66, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v54, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v65, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v64
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v68
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v67, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v55
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v64
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v54, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v48, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v39, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v53
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v52, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v51
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v50, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v49, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v39
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v51, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v50
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v48
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v38, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v37, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v49
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v36, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v126
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v38
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v37
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v9, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v36
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v35
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v125, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v35
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v34, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v8
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v127, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v34, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v33, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v32
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v33
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v32, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v127
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v126, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v125, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v8, 16, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v120, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v124
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v123
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v122, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v12, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v13
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v123
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v121
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v122, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v120, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v111
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v110, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v109, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v107
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v108
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v121
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v111, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v107, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v10, 16, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v110
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v106, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v105, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v109
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v108, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v90
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v13, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v106
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v105
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v104
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v95
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v16, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v94, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v104, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v11, 16, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v95
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v94, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v11, 16, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v93, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v92
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v91, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v91
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v90, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v89, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v89, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v17
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v16
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v88
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v79
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v78, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v17, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v18
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v79
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v16, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v18
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v77
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v77
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v18, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v78, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v16
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v76, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v75
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v74, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v73, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v63
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v76, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v13, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v15, 16, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v16, 16, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v75, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v20
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v74
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v73, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v72
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v15
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v62, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v18
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v72
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v62, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v61, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v63
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v19, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v61
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v18, v17
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v20
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v60
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v21
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v59
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v60, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v15
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v17
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v21, v20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v16
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v20
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v59
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v58, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v17, 16, v16
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v19
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, v58, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v17, v20
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v57, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v20, v19
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v57
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v56, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v47, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v56
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v47
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v46, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v16, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v45, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v20, v19
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v21, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v44
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v18
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v43
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v42, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v17
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v20
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v46
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v45
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v44, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v20, v19
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v22, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v43
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v42, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v40, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v21, v20
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v22, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v23
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v22
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v41
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, v183, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v20
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v22, v21
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v40, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v19, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v20
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v183
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v182, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, v181, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v179
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v22, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v23
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v180
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v178, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, v177, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v182
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v181
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v18, 16, v17
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v20, 16, v19
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v23, v22
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v24, v19
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v25
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v176
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v26
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v167
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v22
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v180, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v179, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v25, v24
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v178
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v177, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v20
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v176
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v24, v23
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v26, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v19
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v20, v21
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v23
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, 0x300, v24
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, v166, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v22, v25
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v165, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v164
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v163
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v162, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v21, v23
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v161, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, v166, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v24, v20
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v25
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v167
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v27, v23
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v26
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v165
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v20
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v25, v24
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v26, v22
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v27
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v160
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v23
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v151
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v150, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v24
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v19
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, 0x300, v23
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v22
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v26, v25
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v28, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff, v20
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v24
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v23, 16, v25
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v163, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v161, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v22, 16, v21
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v26
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, v164, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v24, 16, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v160
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v151, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v25
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v150
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v149, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v26
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v162
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v27, v23
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v28
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v149
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v24
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v28
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v148
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v29, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v30
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v147
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v26, v24
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v28, v27
; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v30, v29
; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, 0x300, v23
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v27, v26
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v148, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v24, v22
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v25
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v27
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v147
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v24
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v146, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v24, v23
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, v145, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v135
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v27, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v28
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v144
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v134, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, v133, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff, v23
; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v26
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v24, 16, v22
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v134
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v27, 16, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v28
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v144
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v135, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v26, 16, v23
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, v145, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v133, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v27, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v28
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v132
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v26
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, v130, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v25
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v32, v115, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v28, v27
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v29, v24
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v30
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v132
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v31
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v131
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v29, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v30
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v131
; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v24
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v29, v28
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v31, v30
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff, v27
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v24
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v25, v26
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v28
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v29
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v29, v130, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v27, v30
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v129, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v26
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v33, 8, v117
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v30, v29
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v31
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v129
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v27, 16, v25
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v119, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v26
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v29
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v128
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v27
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v119
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v26, v28
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v118, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v28
; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v30, v29
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v117, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v128, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v27
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v118
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v28, 16, v26
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v29
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v30
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v116, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v31, v27
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, v115, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v28
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v32, 8, v116
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v34, 8, v114
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xff, v32
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v32, 8, v113
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v30
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v33, 8, v114
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xff, v31
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v34, 8, v113
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v32, v28
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v33, v29
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v36, 8, v100
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v32, v31
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v34, v30
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v27
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v103, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v34, v101, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v32, v112, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v33, v30
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v33, v103, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v35, v101, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v36, v99, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v38, v97, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v34, v31
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v37, v99, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v38, 8, v98
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xff, v34
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v39, v97, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xff, v32
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v34, 8, v102
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xff, v33
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v37, 8, v100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xff, v35
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v39, 8, v98
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xff, v36
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v48, 8, v96
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xff, v38
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v49, 8, v87
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, v34, v32
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, v37, v33
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, v39, v35
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, v48, v36
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, v49, v38
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v29, 0x300, v29
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v28
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v35, 8, v102
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v36, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xff, v37
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v37, 8, v96
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, v38, v34
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xff, v39
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v39, 8, v87
; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, 0x300, v30
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, v35, v32
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, v37, v36
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v34, 0x300, v34
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, v39, v38
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v28
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v29, 0x300, v29
; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, 0x300, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v30
; GFX11-FAKE16-NEXT: v_add_nc_u16 v32, 0x300, v32
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v33, 0x300, v33
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v34, 0x300, v34
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff, v27
; GFX11-FAKE16-NEXT: v_add_nc_u16 v35, 0x300, v35
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v34
; GFX11-FAKE16-NEXT: v_add_nc_u16 v36, 0x300, v36
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff, v29
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v28
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff, v31
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v32
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v33
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v34
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff, v35
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v36
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v29, v27
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v28, v30
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v31, v32
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v33, v34
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v35, v36
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v29, 16, v28
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v31, 16, v33
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v32, 16, v30
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v35, 16, v37
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v36, 16, v34
; GFX11-FAKE16-NEXT: .LBB74_4: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
index 7e231f48de12a..402080aba33d8 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
@@ -4238,11 +4238,10 @@ define <4 x i32> @bitcast_v16i8_to_v4i32(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v17
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v20
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -4250,8 +4249,8 @@ define <4 x i32> @bitcast_v16i8_to_v4i32(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v7
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_add_u16_e32 v2, 3, v8
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v9
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -4259,8 +4258,8 @@ define <4 x i32> @bitcast_v16i8_to_v4i32(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v11
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_add_u16_e32 v3, 3, v12
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v13
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -4268,8 +4267,8 @@ define <4 x i32> @bitcast_v16i8_to_v4i32(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v15
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
-; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -4370,8 +4369,8 @@ define <4 x i32> @bitcast_v16i8_to_v4i32(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-LABEL: bitcast_v16i8_to_v4i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v20, v3 :: v_dual_mov_b32 v17, v1
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, v2 :: v_dual_mov_b32 v19, v0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v20, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, v1 :: v_dual_mov_b32 v19, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v16
@@ -4384,8 +4383,8 @@ define <4 x i32> @bitcast_v16i8_to_v4i32(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB26_3: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v19, v17, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v18, v20, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v19, v18, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v20, v17, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
@@ -4396,9 +4395,9 @@ define <4 x i32> @bitcast_v16i8_to_v4i32(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr5
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr8
@@ -4416,61 +4415,56 @@ define <4 x i32> @bitcast_v16i8_to_v4i32(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB26_2
; GFX11-FAKE16-NEXT: .LBB26_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v4, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v20, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v19, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v18, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v4, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v8, 3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v6, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v10, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v12, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v14, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v8, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v11, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v12, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v12, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v6, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v10, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v14, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v3, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v6, 16, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v5
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -8765,11 +8759,10 @@ define <4 x float> @bitcast_v16i8_to_v4f32(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v17
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v20
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -8777,8 +8770,8 @@ define <4 x float> @bitcast_v16i8_to_v4f32(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v7
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_add_u16_e32 v2, 3, v8
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v9
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -8786,8 +8779,8 @@ define <4 x float> @bitcast_v16i8_to_v4f32(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v11
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_add_u16_e32 v3, 3, v12
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v13
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -8795,8 +8788,8 @@ define <4 x float> @bitcast_v16i8_to_v4f32(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v15
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
-; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -8897,8 +8890,8 @@ define <4 x float> @bitcast_v16i8_to_v4f32(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-LABEL: bitcast_v16i8_to_v4f32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v20, v3 :: v_dual_mov_b32 v17, v1
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, v2 :: v_dual_mov_b32 v19, v0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v20, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, v1 :: v_dual_mov_b32 v19, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v16
@@ -8911,8 +8904,8 @@ define <4 x float> @bitcast_v16i8_to_v4f32(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB50_3: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v19, v17, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v18, v20, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v19, v18, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v20, v17, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
@@ -8923,9 +8916,9 @@ define <4 x float> @bitcast_v16i8_to_v4f32(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr5
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr8
@@ -8943,61 +8936,56 @@ define <4 x float> @bitcast_v16i8_to_v4f32(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB50_2
; GFX11-FAKE16-NEXT: .LBB50_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v4, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v20, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v19, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v18, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v4, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v8, 3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v6, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v10, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v12, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v14, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v8, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v11, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v12, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v12, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v6, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v10, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v14, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v3, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v6, 16, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v5
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -12877,11 +12865,10 @@ define <2 x i64> @bitcast_v16i8_to_v2i64(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v17
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v20
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -12889,8 +12876,8 @@ define <2 x i64> @bitcast_v16i8_to_v2i64(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v7
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_add_u16_e32 v2, 3, v8
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v9
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -12898,8 +12885,8 @@ define <2 x i64> @bitcast_v16i8_to_v2i64(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v11
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_add_u16_e32 v3, 3, v12
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v13
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -12907,8 +12894,8 @@ define <2 x i64> @bitcast_v16i8_to_v2i64(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v15
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
-; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -13009,8 +12996,8 @@ define <2 x i64> @bitcast_v16i8_to_v2i64(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-LABEL: bitcast_v16i8_to_v2i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v20, v3 :: v_dual_mov_b32 v17, v1
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, v2 :: v_dual_mov_b32 v19, v0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v20, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, v1 :: v_dual_mov_b32 v19, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v16
@@ -13023,8 +13010,8 @@ define <2 x i64> @bitcast_v16i8_to_v2i64(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB70_3: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v19, v17, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v18, v20, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v19, v18, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v20, v17, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
@@ -13035,9 +13022,9 @@ define <2 x i64> @bitcast_v16i8_to_v2i64(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr5
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr8
@@ -13055,61 +13042,56 @@ define <2 x i64> @bitcast_v16i8_to_v2i64(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB70_2
; GFX11-FAKE16-NEXT: .LBB70_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v4, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v20, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v19, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v18, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v4, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v8, 3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v6, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v10, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v12, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v14, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v8, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v11, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v12, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v12, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v6, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v10, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v14, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v3, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v6, 16, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v5
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -16627,11 +16609,10 @@ define <2 x double> @bitcast_v16i8_to_v2f64(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v17
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v20
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -16639,8 +16620,8 @@ define <2 x double> @bitcast_v16i8_to_v2f64(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v7
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_add_u16_e32 v2, 3, v8
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v9
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -16648,8 +16629,8 @@ define <2 x double> @bitcast_v16i8_to_v2f64(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v11
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_add_u16_e32 v3, 3, v12
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v13
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -16657,8 +16638,8 @@ define <2 x double> @bitcast_v16i8_to_v2f64(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v15
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
-; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -16759,8 +16740,8 @@ define <2 x double> @bitcast_v16i8_to_v2f64(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-LABEL: bitcast_v16i8_to_v2f64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v20, v3 :: v_dual_mov_b32 v17, v1
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, v2 :: v_dual_mov_b32 v19, v0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v20, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, v1 :: v_dual_mov_b32 v19, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v16
@@ -16773,8 +16754,8 @@ define <2 x double> @bitcast_v16i8_to_v2f64(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB86_3: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v19, v17, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v18, v20, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v19, v18, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v20, v17, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
@@ -16785,9 +16766,9 @@ define <2 x double> @bitcast_v16i8_to_v2f64(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr5
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr8
@@ -16805,61 +16786,56 @@ define <2 x double> @bitcast_v16i8_to_v2f64(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB86_2
; GFX11-FAKE16-NEXT: .LBB86_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v4, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v20, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v19, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v18, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v4, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v8, 3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v6, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v10, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v12, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v14, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v8, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v11, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v12, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v12, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v6, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v10, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v14, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v3, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v6, 16, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v5
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -20146,11 +20122,10 @@ define <8 x i16> @bitcast_v16i8_to_v8i16(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v17
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v20
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -20158,8 +20133,8 @@ define <8 x i16> @bitcast_v16i8_to_v8i16(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v7
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_add_u16_e32 v2, 3, v8
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v9
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -20167,8 +20142,8 @@ define <8 x i16> @bitcast_v16i8_to_v8i16(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v11
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_add_u16_e32 v3, 3, v12
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v13
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -20176,8 +20151,8 @@ define <8 x i16> @bitcast_v16i8_to_v8i16(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v15
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
-; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -20278,8 +20253,8 @@ define <8 x i16> @bitcast_v16i8_to_v8i16(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-LABEL: bitcast_v16i8_to_v8i16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v20, v3 :: v_dual_mov_b32 v17, v1
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, v2 :: v_dual_mov_b32 v19, v0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v20, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, v1 :: v_dual_mov_b32 v19, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v16
@@ -20292,8 +20267,8 @@ define <8 x i16> @bitcast_v16i8_to_v8i16(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB98_3: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v19, v17, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v18, v20, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v19, v18, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v20, v17, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
@@ -20304,9 +20279,9 @@ define <8 x i16> @bitcast_v16i8_to_v8i16(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr5
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr8
@@ -20324,61 +20299,56 @@ define <8 x i16> @bitcast_v16i8_to_v8i16(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB98_2
; GFX11-FAKE16-NEXT: .LBB98_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v4, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v20, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v19, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v18, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v4, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v8, 3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v6, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v10, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v12, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v14, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v8, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v11, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v12, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v12, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v6, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v10, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v14, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v3, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v6, 16, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v5
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -23142,11 +23112,10 @@ define <8 x half> @bitcast_v16i8_to_v8f16(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v17
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v20
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -23154,8 +23123,8 @@ define <8 x half> @bitcast_v16i8_to_v8f16(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v7
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_add_u16_e32 v2, 3, v8
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v9
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -23163,8 +23132,8 @@ define <8 x half> @bitcast_v16i8_to_v8f16(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v11
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_add_u16_e32 v3, 3, v12
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v13
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -23172,8 +23141,8 @@ define <8 x half> @bitcast_v16i8_to_v8f16(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v15
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
-; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -23274,8 +23243,8 @@ define <8 x half> @bitcast_v16i8_to_v8f16(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-LABEL: bitcast_v16i8_to_v8f16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v20, v3 :: v_dual_mov_b32 v17, v1
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, v2 :: v_dual_mov_b32 v19, v0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v20, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, v1 :: v_dual_mov_b32 v19, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v16
@@ -23288,8 +23257,8 @@ define <8 x half> @bitcast_v16i8_to_v8f16(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB106_3: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v19, v17, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v18, v20, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v19, v18, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v20, v17, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
@@ -23300,9 +23269,9 @@ define <8 x half> @bitcast_v16i8_to_v8f16(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr5
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr8
@@ -23320,61 +23289,56 @@ define <8 x half> @bitcast_v16i8_to_v8f16(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB106_2
; GFX11-FAKE16-NEXT: .LBB106_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v4, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v20, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v19, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v18, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v4, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v8, 3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v6, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v10, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v12, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v14, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v8, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v11, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v12, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v12, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v6, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v10, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v14, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v3, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v6, 16, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v5
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -25447,11 +25411,10 @@ define <8 x bfloat> @bitcast_v16i8_to_v8bf16(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v17
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v20
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -25459,8 +25422,8 @@ define <8 x bfloat> @bitcast_v16i8_to_v8bf16(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v7
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_add_u16_e32 v2, 3, v8
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v9
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -25468,8 +25431,8 @@ define <8 x bfloat> @bitcast_v16i8_to_v8bf16(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v11
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_add_u16_e32 v3, 3, v12
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v13
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -25477,8 +25440,8 @@ define <8 x bfloat> @bitcast_v16i8_to_v8bf16(<16 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v15
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
-; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -25579,8 +25542,8 @@ define <8 x bfloat> @bitcast_v16i8_to_v8bf16(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-LABEL: bitcast_v16i8_to_v8bf16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v20, v3 :: v_dual_mov_b32 v17, v1
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, v2 :: v_dual_mov_b32 v19, v0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v17, v3 :: v_dual_mov_b32 v20, v2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, v1 :: v_dual_mov_b32 v19, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v16
@@ -25593,8 +25556,8 @@ define <8 x bfloat> @bitcast_v16i8_to_v8bf16(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB110_3: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v19, v17, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v18, v20, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v19, v18, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v20, v17, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v4, v5, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v6, v7, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v8, v9, 0xc0c0004
@@ -25605,9 +25568,9 @@ define <8 x bfloat> @bitcast_v16i8_to_v8bf16(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr5
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr8
@@ -25625,61 +25588,56 @@ define <8 x bfloat> @bitcast_v16i8_to_v8bf16(<16 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB110_2
; GFX11-FAKE16-NEXT: .LBB110_4: ; %cmp.true
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v4, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v20, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v19, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v18, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v4, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v8, 3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v6, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v10, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v12, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v14, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v8, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v11, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v12, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v12, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v6, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v10, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v14, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v3, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v6, 16, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v5
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
index 224b73353c3bc..2d69881065f1e 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
@@ -6505,11 +6505,10 @@ define <8 x i32> @bitcast_v32i8_to_v8i32(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v36
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v35
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v34
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v33
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -6517,8 +6516,8 @@ define <8 x i32> @bitcast_v32i8_to_v8i32(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v31
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_add_u16_e32 v2, 3, v8
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v9
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -6526,8 +6525,8 @@ define <8 x i32> @bitcast_v32i8_to_v8i32(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v11
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_add_u16_e32 v3, 3, v12
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v13
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -6535,8 +6534,8 @@ define <8 x i32> @bitcast_v32i8_to_v8i32(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v15
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
-; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_add_u16_e32 v4, 3, v16
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v17
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -6544,8 +6543,8 @@ define <8 x i32> @bitcast_v32i8_to_v8i32(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v19
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
-; GFX9-NEXT: v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_add_u16_e32 v5, 3, v20
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v21
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -6553,8 +6552,8 @@ define <8 x i32> @bitcast_v32i8_to_v8i32(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v23
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
-; GFX9-NEXT: v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_add_u16_e32 v6, 3, v24
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v25
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -6562,8 +6561,8 @@ define <8 x i32> @bitcast_v32i8_to_v8i32(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v27
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
-; GFX9-NEXT: v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_add_u16_e32 v7, 3, v28
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v29
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -6572,8 +6571,8 @@ define <8 x i32> @bitcast_v32i8_to_v8i32(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v39
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
-; GFX9-NEXT: v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -6836,110 +6835,102 @@ define <8 x i32> @bitcast_v32i8_to_v8i32(<32 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB26_2
; GFX11-FAKE16-NEXT: .LBB26_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v38, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v36, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v37
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v36, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v35
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v34, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v32, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v33
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v32, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v8, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v10, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v31
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v10, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v6, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v8, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v12, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v12, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v14, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v16, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v14, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v6, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v16, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v20, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v18, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v19
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v20, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v18, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v8, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v21
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v19
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v24, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v28, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v22, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v26, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v28, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v30, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v24, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v26, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v29
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v30, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v27
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v29
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v23
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v13
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v27
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v14, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v39
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v13, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v15, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v16, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v17, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v39
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v11, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v15, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v9, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v13, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v12
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v7, 16, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v8, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v11, 16, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v12, 16, v10
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -13773,11 +13764,10 @@ define <8 x float> @bitcast_v32i8_to_v8f32(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v36
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v35
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v34
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v33
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -13785,8 +13775,8 @@ define <8 x float> @bitcast_v32i8_to_v8f32(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v31
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_add_u16_e32 v2, 3, v8
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v9
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -13794,8 +13784,8 @@ define <8 x float> @bitcast_v32i8_to_v8f32(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v11
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_add_u16_e32 v3, 3, v12
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v13
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -13803,8 +13793,8 @@ define <8 x float> @bitcast_v32i8_to_v8f32(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v15
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
-; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_add_u16_e32 v4, 3, v16
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v17
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -13812,8 +13802,8 @@ define <8 x float> @bitcast_v32i8_to_v8f32(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v19
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
-; GFX9-NEXT: v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_add_u16_e32 v5, 3, v20
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v21
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -13821,8 +13811,8 @@ define <8 x float> @bitcast_v32i8_to_v8f32(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v23
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
-; GFX9-NEXT: v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_add_u16_e32 v6, 3, v24
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v25
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -13830,8 +13820,8 @@ define <8 x float> @bitcast_v32i8_to_v8f32(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v27
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
-; GFX9-NEXT: v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_add_u16_e32 v7, 3, v28
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v29
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -13840,8 +13830,8 @@ define <8 x float> @bitcast_v32i8_to_v8f32(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v39
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
-; GFX9-NEXT: v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -14104,110 +14094,102 @@ define <8 x float> @bitcast_v32i8_to_v8f32(<32 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB50_2
; GFX11-FAKE16-NEXT: .LBB50_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v38, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v36, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v37
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v36, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v35
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v34, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v32, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v33
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v32, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v8, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v10, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v31
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v10, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v6, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v8, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v12, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v12, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v14, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v16, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v14, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v6, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v16, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v20, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v18, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v19
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v20, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v18, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v8, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v21
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v19
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v24, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v28, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v22, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v26, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v28, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v30, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v24, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v26, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v29
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v30, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v27
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v29
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v23
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v13
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v27
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v14, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v39
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v13, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v15, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v16, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v17, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v39
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v11, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v15, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v9, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v13, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v12
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v7, 16, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v8, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v11, 16, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v12, 16, v10
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -20502,11 +20484,10 @@ define <4 x i64> @bitcast_v32i8_to_v4i64(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v36
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v35
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v34
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v33
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -20514,8 +20495,8 @@ define <4 x i64> @bitcast_v32i8_to_v4i64(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v31
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_add_u16_e32 v2, 3, v8
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v9
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -20523,8 +20504,8 @@ define <4 x i64> @bitcast_v32i8_to_v4i64(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v11
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_add_u16_e32 v3, 3, v12
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v13
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -20532,8 +20513,8 @@ define <4 x i64> @bitcast_v32i8_to_v4i64(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v15
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
-; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_add_u16_e32 v4, 3, v16
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v17
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -20541,8 +20522,8 @@ define <4 x i64> @bitcast_v32i8_to_v4i64(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v19
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
-; GFX9-NEXT: v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_add_u16_e32 v5, 3, v20
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v21
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -20550,8 +20531,8 @@ define <4 x i64> @bitcast_v32i8_to_v4i64(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v23
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
-; GFX9-NEXT: v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_add_u16_e32 v6, 3, v24
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v25
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -20559,8 +20540,8 @@ define <4 x i64> @bitcast_v32i8_to_v4i64(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v27
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
-; GFX9-NEXT: v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_add_u16_e32 v7, 3, v28
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v29
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -20569,8 +20550,8 @@ define <4 x i64> @bitcast_v32i8_to_v4i64(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v39
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
-; GFX9-NEXT: v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -20833,110 +20814,102 @@ define <4 x i64> @bitcast_v32i8_to_v4i64(<32 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB70_2
; GFX11-FAKE16-NEXT: .LBB70_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v38, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v36, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v37
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v36, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v35
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v34, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v32, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v33
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v32, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v8, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v10, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v31
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v10, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v6, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v8, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v12, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v12, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v14, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v16, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v14, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v6, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v16, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v20, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v18, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v19
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v20, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v18, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v8, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v21
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v19
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v24, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v28, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v22, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v26, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v28, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v30, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v24, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v26, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v29
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v30, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v27
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v29
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v23
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v13
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v27
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v14, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v39
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v13, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v15, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v16, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v17, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v39
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v11, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v15, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v9, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v13, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v12
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v7, 16, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v8, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v11, 16, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v12, 16, v10
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -26764,11 +26737,10 @@ define <4 x double> @bitcast_v32i8_to_v4f64(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v36
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v35
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v34
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v33
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -26776,8 +26748,8 @@ define <4 x double> @bitcast_v32i8_to_v4f64(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v31
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_add_u16_e32 v2, 3, v8
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v9
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -26785,8 +26757,8 @@ define <4 x double> @bitcast_v32i8_to_v4f64(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v11
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_add_u16_e32 v3, 3, v12
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v13
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -26794,8 +26766,8 @@ define <4 x double> @bitcast_v32i8_to_v4f64(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v15
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
-; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_add_u16_e32 v4, 3, v16
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v17
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -26803,8 +26775,8 @@ define <4 x double> @bitcast_v32i8_to_v4f64(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v19
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
-; GFX9-NEXT: v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_add_u16_e32 v5, 3, v20
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v21
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -26812,8 +26784,8 @@ define <4 x double> @bitcast_v32i8_to_v4f64(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v23
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
-; GFX9-NEXT: v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_add_u16_e32 v6, 3, v24
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v25
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -26821,8 +26793,8 @@ define <4 x double> @bitcast_v32i8_to_v4f64(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v27
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
-; GFX9-NEXT: v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_add_u16_e32 v7, 3, v28
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v29
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -26831,8 +26803,8 @@ define <4 x double> @bitcast_v32i8_to_v4f64(<32 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v39
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
-; GFX9-NEXT: v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -27095,110 +27067,102 @@ define <4 x double> @bitcast_v32i8_to_v4f64(<32 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB86_2
; GFX11-FAKE16-NEXT: .LBB86_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v38, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v36, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v37
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v36, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v35
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v34, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v32, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v33
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v32, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v8, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v10, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v31
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v10, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v6, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v8, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v12, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v12, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v14, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v16, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v14, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v6, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v16, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v20, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v18, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v19
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v20, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v18, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v8, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v21
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v19
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v24, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v28, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v22, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v26, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v28, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v30, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v24, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v26, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v29
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v30, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v27
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v29
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v23
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v13
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v27
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v14, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v39
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v13, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v15, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v16, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v17, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v39
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v11, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v15, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v9, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v13, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v12
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v7, 16, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v8, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v11, 16, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v12, 16, v10
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
index aba9755a4f357..31375f792c6b2 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
@@ -4675,11 +4675,10 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v38
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v37
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v36
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v35
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -4687,8 +4686,8 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v33
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_add_u16_e32 v2, 3, v32
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v31
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -4696,8 +4695,8 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v11
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_add_u16_e32 v3, 3, v12
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v13
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -4705,8 +4704,8 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v15
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
-; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_add_u16_e32 v4, 3, v16
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v17
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -4714,8 +4713,8 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v19
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
-; GFX9-NEXT: v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_add_u16_e32 v5, 3, v20
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v21
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -4723,8 +4722,8 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v23
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
-; GFX9-NEXT: v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_add_u16_e32 v6, 3, v24
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v25
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -4732,8 +4731,8 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v27
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
-; GFX9-NEXT: v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_add_u16_e32 v7, 3, v28
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v29
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -4741,8 +4740,8 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v55
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
-; GFX9-NEXT: v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v8, 3, v41
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v40
@@ -4751,8 +4750,8 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v53
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
-; GFX9-NEXT: v_add_u16_sdwa v9, v9, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_add_u16_e32 v9, 3, v52
; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v51
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -4760,8 +4759,8 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v49
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
-; GFX9-NEXT: v_add_u16_sdwa v10, v10, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: .LBB14_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
@@ -4991,22 +4990,22 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v10i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v2 :: v_dual_mov_b32 v48, v0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v48, v0
; GFX11-FAKE16-NEXT: s_clause 0x9
; GFX11-FAKE16-NEXT: scratch_load_u16 v49, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v51, off, s32 offset:28
-; GFX11-FAKE16-NEXT: scratch_load_u16 v50, off, s32 offset:24
+; GFX11-FAKE16-NEXT: scratch_load_u16 v50, off, s32 offset:28
+; GFX11-FAKE16-NEXT: scratch_load_u16 v51, off, s32 offset:24
; GFX11-FAKE16-NEXT: scratch_load_u16 v53, off, s32 offset:20
; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:36
; GFX11-FAKE16-NEXT: scratch_load_u16 v52, off, s32 offset:16
-; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32 offset:12
-; GFX11-FAKE16-NEXT: scratch_load_u16 v54, off, s32 offset:8
+; GFX11-FAKE16-NEXT: scratch_load_u16 v54, off, s32 offset:12
+; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32 offset:8
; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v9 :: v_dual_mov_b32 v32, v8
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v34, v6
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v36, v4
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v38, v1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v38, v2
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
@@ -5022,8 +5021,8 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB14_3: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v48, v38, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v39, v37, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v48, v39, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v38, v37, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v36, v35, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v34, v33, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v32, v31, 0xc0c0004
@@ -5044,18 +5043,18 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v28, v29, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v30, v64, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v65, v54, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v55, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v51, v49, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v65, v55, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v54, v52, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v53, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v50, v49, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v8, 16, v7
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v10, 16, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v12, 16, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v14, 16, v13
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
@@ -5086,148 +5085,138 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB14_2
; GFX11-FAKE16-NEXT: .LBB14_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v48, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v39, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v38
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v37
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v39
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v36, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v32, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v38, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v34, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v35
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v34, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v10, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v37
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v33
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v32, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v31
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v10, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v12, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v14, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v15
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v12, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v16, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v14, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v18, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v16, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v18, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v19
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v7, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v19
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v20, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v22, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v20, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v23
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v24, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v24, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v26, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v22, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v6, 16, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v28, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v26, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v28, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v27
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v23
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v29
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v30, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v11, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v27
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v53, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v5
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v65, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v55, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v53, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v51, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v65, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v30, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v55
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v54, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v51
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v50, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v10
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v64
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v54
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v52
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v50
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v49
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v15, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v17, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v18, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v16
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v64
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v14, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v52
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v49
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v16
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v11, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v9, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v10, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v13, 16, v15
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v14, 16, v12
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -11395,11 +11384,10 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v38
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v37
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v36
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v35
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -11407,8 +11395,8 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v33
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_add_u16_e32 v2, 3, v32
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v31
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -11416,8 +11404,8 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v11
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_add_u16_e32 v3, 3, v12
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v13
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -11425,8 +11413,8 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v15
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
-; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_add_u16_e32 v4, 3, v16
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v17
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -11434,8 +11422,8 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v19
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
-; GFX9-NEXT: v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_add_u16_e32 v5, 3, v20
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v21
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -11443,8 +11431,8 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v23
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
-; GFX9-NEXT: v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_add_u16_e32 v6, 3, v24
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v25
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -11452,8 +11440,8 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v27
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
-; GFX9-NEXT: v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_add_u16_e32 v7, 3, v28
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v29
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -11461,8 +11449,8 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v55
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
-; GFX9-NEXT: v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v8, 3, v41
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v40
@@ -11471,8 +11459,8 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v53
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
-; GFX9-NEXT: v_add_u16_sdwa v9, v9, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_add_u16_e32 v9, 3, v52
; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v51
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -11480,8 +11468,8 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v49
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
-; GFX9-NEXT: v_add_u16_sdwa v10, v10, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: .LBB34_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
@@ -11711,22 +11699,22 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v10f32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v2 :: v_dual_mov_b32 v48, v0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v1 :: v_dual_mov_b32 v48, v0
; GFX11-FAKE16-NEXT: s_clause 0x9
; GFX11-FAKE16-NEXT: scratch_load_u16 v49, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v51, off, s32 offset:28
-; GFX11-FAKE16-NEXT: scratch_load_u16 v50, off, s32 offset:24
+; GFX11-FAKE16-NEXT: scratch_load_u16 v50, off, s32 offset:28
+; GFX11-FAKE16-NEXT: scratch_load_u16 v51, off, s32 offset:24
; GFX11-FAKE16-NEXT: scratch_load_u16 v53, off, s32 offset:20
; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:36
; GFX11-FAKE16-NEXT: scratch_load_u16 v52, off, s32 offset:16
-; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32 offset:12
-; GFX11-FAKE16-NEXT: scratch_load_u16 v54, off, s32 offset:8
+; GFX11-FAKE16-NEXT: scratch_load_u16 v54, off, s32 offset:12
+; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32 offset:8
; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v9 :: v_dual_mov_b32 v32, v8
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v34, v6
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v5 :: v_dual_mov_b32 v36, v4
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v38, v1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v3 :: v_dual_mov_b32 v38, v2
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
@@ -11742,8 +11730,8 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB34_3: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v48, v38, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v39, v37, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v48, v39, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v38, v37, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v36, v35, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v34, v33, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v32, v31, 0xc0c0004
@@ -11764,18 +11752,18 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v28, v29, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v30, v64, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v65, v54, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v55, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v51, v49, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v65, v55, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v54, v52, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v53, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v50, v49, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v8, 16, v7
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v10, 16, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v12, 16, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v14, 16, v13
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
@@ -11806,148 +11794,138 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB34_2
; GFX11-FAKE16-NEXT: .LBB34_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v48, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v39, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v38
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v37
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v39
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v36, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v32, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v38, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v34, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v35
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v34, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v10, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v37
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v33
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v32, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v31
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v10, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v12, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v14, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v15
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v12, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v16, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v14, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v18, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v16, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v18, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v19
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v7, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v19
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v20, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v22, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v20, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v23
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v24, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v24, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v26, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v22, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v6, 16, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v28, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v26, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v28, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v27
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v23
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v29
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v30, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v11, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v27
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v53, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v5
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v65, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v55, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v53, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v51, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v65, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v30, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v55
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v54, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v51
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v50, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v10
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v64
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v54
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v52
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v50
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v49
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v15, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v17, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v18, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v16
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v64
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v14, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v52
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v49
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v16
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v11, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v9, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v10, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v13, 16, v15
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v14, 16, v12
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -28555,11 +28533,10 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v52
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v51
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v50
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v49
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -28567,8 +28544,8 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v39
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_add_u16_e32 v2, 3, v38
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v37
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -28576,8 +28553,8 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v35
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_add_u16_e32 v3, 3, v34
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v33
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -28585,8 +28562,8 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v31
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
-; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_add_u16_e32 v4, 3, v16
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v17
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -28594,8 +28571,8 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v19
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
-; GFX9-NEXT: v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_add_u16_e32 v5, 3, v20
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v21
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -28603,8 +28580,8 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v23
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
-; GFX9-NEXT: v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_add_u16_e32 v6, 3, v24
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v25
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -28612,8 +28589,8 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v27
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
-; GFX9-NEXT: v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_add_u16_e32 v7, 3, v28
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v29
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -28621,8 +28598,8 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v45
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
-; GFX9-NEXT: v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v8, 3, v47
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v46
@@ -28631,8 +28608,8 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v43
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
-; GFX9-NEXT: v_add_u16_sdwa v9, v9, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_add_u16_e32 v9, 3, v42
; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v41
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -28640,8 +28617,8 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v55
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
-; GFX9-NEXT: v_add_u16_sdwa v10, v10, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: .LBB72_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
@@ -28884,25 +28861,25 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v5f64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v2 :: v_dual_mov_b32 v54, v0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v1 :: v_dual_mov_b32 v54, v0
; GFX11-FAKE16-NEXT: s_clause 0x9
; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:28
-; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:24
+; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:28
+; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:24
; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:20
; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:36
; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:16
-; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:12
-; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:8
+; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:12
+; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:8
; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v15 :: v_dual_mov_b32 v32, v13
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v14 :: v_dual_mov_b32 v34, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v15 :: v_dual_mov_b32 v32, v13
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v14 :: v_dual_mov_b32 v34, v12
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v11 :: v_dual_mov_b32 v36, v10
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v9 :: v_dual_mov_b32 v38, v8
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v7 :: v_dual_mov_b32 v48, v6
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, v5 :: v_dual_mov_b32 v50, v4
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v3 :: v_dual_mov_b32 v52, v1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v3 :: v_dual_mov_b32 v52, v2
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
@@ -28918,14 +28895,14 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB72_3: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v54, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v53, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v54, v53, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v52, v51, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v50, v49, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v48, v39, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v38, v37, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v36, v35, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v34, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v33, v31, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v31, v33, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v16, v17, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v18, v19, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
@@ -28940,18 +28917,18 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v28, v29, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v30, v70, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v71, v68, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v69, v66, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v67, v64, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v65, v55, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v71, v69, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v68, v66, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v67, v65, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v64, v55, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v8, 16, v7
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v10, 16, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v12, 16, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v14, 16, v13
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
@@ -28963,8 +28940,8 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr16
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
@@ -28982,148 +28959,138 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB72_2
; GFX11-FAKE16-NEXT: .LBB72_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v54, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v53, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v52
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v51
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v53
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v50, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v38, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v52, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v48, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v49
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v48, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v36, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v37
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v51
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v39
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v38, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v35
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v37
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v36, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v35
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v34, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v33, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v34, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v16, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v32
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v31, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v18, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v32
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v16, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v18, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v33
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v19
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v7, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v19
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v20, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v22, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v20, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v23
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v24, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v24, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v26, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v22, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v6, 16, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v28, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v26, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v28, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v27
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v23
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v29
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v30, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v11, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v27
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v67, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v5
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v71, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v69, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v67, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v65, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v71, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v30, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v69
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v68, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v65
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v64, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v10
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v70
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v68
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v66
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v64
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v55
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v15, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v17, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v18, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v16
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v70
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v14, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v66
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v55
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v16
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v11, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v9, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v10, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v13, 16, v15
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v14, 16, v12
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -32402,11 +32369,10 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v52
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v51
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v50
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v49
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -32414,8 +32380,8 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v39
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_add_u16_e32 v2, 3, v38
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v37
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -32423,8 +32389,8 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v35
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_add_u16_e32 v3, 3, v34
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v33
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -32432,8 +32398,8 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v31
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
-; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_add_u16_e32 v4, 3, v16
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v17
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -32441,8 +32407,8 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v19
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
-; GFX9-NEXT: v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_add_u16_e32 v5, 3, v20
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v21
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -32450,8 +32416,8 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v23
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
-; GFX9-NEXT: v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_add_u16_e32 v6, 3, v24
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v25
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -32459,8 +32425,8 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v27
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
-; GFX9-NEXT: v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_add_u16_e32 v7, 3, v28
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v29
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -32468,8 +32434,8 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v45
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
-; GFX9-NEXT: v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v8, 3, v47
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v46
@@ -32478,8 +32444,8 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v43
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
-; GFX9-NEXT: v_add_u16_sdwa v9, v9, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_add_u16_e32 v9, 3, v42
; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v41
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -32487,8 +32453,8 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v55
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
-; GFX9-NEXT: v_add_u16_sdwa v10, v10, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: .LBB76_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
@@ -32731,25 +32697,25 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-LABEL: bitcast_v40i8_to_v5i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v2 :: v_dual_mov_b32 v54, v0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v1 :: v_dual_mov_b32 v54, v0
; GFX11-FAKE16-NEXT: s_clause 0x9
; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:28
-; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:24
+; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:28
+; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:24
; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:20
; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:36
; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:16
-; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:12
-; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:8
+; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:12
+; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:8
; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:4
; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v15 :: v_dual_mov_b32 v32, v13
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v14 :: v_dual_mov_b32 v34, v12
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v15 :: v_dual_mov_b32 v32, v13
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v14 :: v_dual_mov_b32 v34, v12
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v11 :: v_dual_mov_b32 v36, v10
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v9 :: v_dual_mov_b32 v38, v8
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v7 :: v_dual_mov_b32 v48, v6
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, v5 :: v_dual_mov_b32 v50, v4
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v3 :: v_dual_mov_b32 v52, v1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v3 :: v_dual_mov_b32 v52, v2
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
@@ -32765,14 +32731,14 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB76_3: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v54, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v53, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v54, v53, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v52, v51, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v50, v49, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v48, v39, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v38, v37, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v36, v35, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v34, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v33, v31, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v31, v33, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v16, v17, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v18, v19, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
@@ -32787,18 +32753,18 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v28, v29, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v30, v70, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v71, v68, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v69, v66, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v67, v64, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v65, v55, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v71, v69, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v68, v66, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v67, v65, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v64, v55, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v8, 16, v7
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v10, 16, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v12, 16, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v14, 16, v13
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
@@ -32810,8 +32776,8 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr16
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
@@ -32829,148 +32795,138 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB76_2
; GFX11-FAKE16-NEXT: .LBB76_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v54, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v53, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v52
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v51
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v53
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v50, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v38, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v52, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v48, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v49
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v48, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v36, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v37
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v51
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v39
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v38, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v35
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v37
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v36, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v35
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v34, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v33, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v34, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v16, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v32
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v31, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v18, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v32
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v16, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v18, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v33
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v19
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v7, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v19
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v20, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v22, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v20, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v23
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v24, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v24, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v26, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v22, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v6, 16, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v28, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v26, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v28, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v27
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v23
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v29
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v30, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v11, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v27
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v67, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v5
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v71, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v69, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v67, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v65, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v71, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v30, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v69
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v68, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v65
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v64, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v10
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v70
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v68
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v66
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v64
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v55
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v15, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v17, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v18, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v16
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v70
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v14, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v66
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v55
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v16
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v11, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v13, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v9, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v10, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v13, 16, v15
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v14, 16, v12
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
index 123d1042e27c9..609b21d4e7482 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
@@ -2286,11 +2286,10 @@ define i32 @bitcast_v4i8_to_i32(<4 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v3
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -2365,23 +2364,21 @@ define i32 @bitcast_v4i8_to_i32(<4 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB22_2
; GFX11-FAKE16-NEXT: .LBB22_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v5, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v2, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v2, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -4549,11 +4546,10 @@ define float @bitcast_v4i8_to_f32(<4 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v3
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -4628,23 +4624,21 @@ define float @bitcast_v4i8_to_f32(<4 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB42_2
; GFX11-FAKE16-NEXT: .LBB42_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v5, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v2, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v2, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -6530,11 +6524,10 @@ define <2 x i16> @bitcast_v4i8_to_v2i16(<4 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v3
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -6609,23 +6602,21 @@ define <2 x i16> @bitcast_v4i8_to_v2i16(<4 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB58_2
; GFX11-FAKE16-NEXT: .LBB58_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v5, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v2, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v2, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -8189,11 +8180,10 @@ define <2 x half> @bitcast_v4i8_to_v2f16(<4 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v3
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -8268,23 +8258,21 @@ define <2 x half> @bitcast_v4i8_to_v2f16(<4 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB70_2
; GFX11-FAKE16-NEXT: .LBB70_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v5, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v2, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v2, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -9632,11 +9620,10 @@ define <2 x bfloat> @bitcast_v4i8_to_v2bf16(<4 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v3
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -9711,23 +9698,21 @@ define <2 x bfloat> @bitcast_v4i8_to_v2bf16(<4 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB78_2
; GFX11-FAKE16-NEXT: .LBB78_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v5, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v2, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v2, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -10316,11 +10301,10 @@ define <1 x i32> @bitcast_v4i8_to_v1i32(<4 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v3
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -10395,23 +10379,21 @@ define <1 x i32> @bitcast_v4i8_to_v1i32(<4 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB82_2
; GFX11-FAKE16-NEXT: .LBB82_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v5, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v2, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v2, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
index 092528a4feb1e..efa98471722fb 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
@@ -12694,13 +12694,12 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u16_e32 v3, 3, v48
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v39
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX9-NEXT: v_add_u16_e32 v2, 3, v38
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v37
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -12708,8 +12707,8 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v35
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_add_u16_e32 v3, 3, v34
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v33
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -12717,8 +12716,8 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v31
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
-; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_add_u16_e32 v4, 3, v16
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v17
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -12726,8 +12725,8 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v19
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
-; GFX9-NEXT: v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_add_u16_e32 v5, 3, v20
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v21
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -12735,8 +12734,8 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v23
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
-; GFX9-NEXT: v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
@@ -12765,8 +12764,8 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v7, 3, v7
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -12779,48 +12778,48 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v8, 3, v8
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_add_u16_e32 v8, 3, v24
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v25
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 3, v47
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
-; GFX9-NEXT: v_add_u16_sdwa v9, v9, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_add_u16_e32 v9, 3, v26
; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v27
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v10, 3, v45
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
-; GFX9-NEXT: v_add_u16_sdwa v10, v10, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: v_add_u16_e32 v10, 3, v28
; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v29
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 3, v42
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
-; GFX9-NEXT: v_add_u16_sdwa v11, v11, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v11
+; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
+; GFX9-NEXT: v_lshl_or_b32 v10, v11, 16, v10
; GFX9-NEXT: v_add_u16_e32 v11, 3, v41
; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v40
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v12, 3, v55
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
-; GFX9-NEXT: v_add_u16_sdwa v12, v12, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: v_add_u16_e32 v12, 3, v62
; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v61
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v13, 3, v60
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
-; GFX9-NEXT: v_add_u16_sdwa v13, v13, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v12, v12, v13
+; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
+; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; GFX9-NEXT: v_add_u16_e32 v13, 3, v58
; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v57
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -12829,8 +12828,8 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v14, 3, v14
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v14, v14, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -12843,8 +12842,8 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v15, 3, v15
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v15, v15, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v14, v14, v15
+; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
+; GFX9-NEXT: v_lshl_or_b32 v14, v15, 16, v14
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -12855,8 +12854,8 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u16_e32 v16, 3, v56
; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
-; GFX9-NEXT: v_add_u16_sdwa v16, v16, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v15, v15, v16
+; GFX9-NEXT: v_add_u16_e32 v16, 0x300, v16
+; GFX9-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; GFX9-NEXT: .LBB26_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
@@ -13232,50 +13231,50 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v16i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v2 :: v_dual_mov_b32 v54, v0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v1 :: v_dual_mov_b32 v54, v0
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32 offset:128
; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:124
-; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:120
-; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:116
-; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:112
-; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:108
+; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:120
+; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:116
+; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:112
+; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:108
; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:104
; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:100
; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32 offset:96
; GFX11-FAKE16-NEXT: scratch_load_u16 v80, off, s32 offset:92
-; GFX11-FAKE16-NEXT: scratch_load_u16 v81, off, s32 offset:88
-; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:84
-; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:80
-; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:76
-; GFX11-FAKE16-NEXT: scratch_load_u16 v84, off, s32 offset:72
-; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:68
-; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:64
-; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:60
-; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:56
+; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:88
+; GFX11-FAKE16-NEXT: scratch_load_u16 v84, off, s32 offset:84
+; GFX11-FAKE16-NEXT: scratch_load_u16 v81, off, s32 offset:80
+; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:76
+; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:72
+; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:68
+; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:64
+; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:60
+; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:56
; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:52
; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:48
; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:44
-; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:40
-; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:36
-; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:28
+; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:40
+; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:36
+; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:32
+; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_u16 v112, off, s32 offset:24
; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:20
; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:132
; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:16
-; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:12
-; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:8
+; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:12
+; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:8
; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:4
-; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32
+; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32 offset:4
+; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v15 :: v_dual_mov_b32 v32, v14
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v13 :: v_dual_mov_b32 v34, v12
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v11 :: v_dual_mov_b32 v36, v10
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v9 :: v_dual_mov_b32 v38, v8
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v7 :: v_dual_mov_b32 v48, v6
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, v5 :: v_dual_mov_b32 v50, v4
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v3 :: v_dual_mov_b32 v52, v1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v3 :: v_dual_mov_b32 v52, v2
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
@@ -13291,8 +13290,8 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB26_3: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v54, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v53, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v54, v53, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v52, v51, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v50, v49, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v48, v39, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v38, v37, 0xc0c0004
@@ -13313,27 +13312,27 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v26, v27, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v28, v29, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v30, v119, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v118, v117, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v116, v115, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v30, v116, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v119, v118, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v117, v115, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v114, v112, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v113, v103, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v102, v100, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v103, v100, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v113, v102, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v101, v99, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v11, 16, v10
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v13, 16, v12
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v15, 16, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v98, v96, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v97, v87, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v86, v84, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v85, v82, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v83, v81, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v98, v97, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v96, v85, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v87, v86, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v83, v81, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v84, v82, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v70, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v71, v68, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v66, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v67, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v67, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v69, v66, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v65, v55, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v14, 16, v13
@@ -13341,8 +13340,8 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v18, 16, v17
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v20, 16, v19
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
@@ -13371,251 +13370,236 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB26_2
; GFX11-FAKE16-NEXT: .LBB26_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v54, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v53, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v52
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v53
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v52, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v51
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v50, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v48, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v49
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v36, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v39
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v38, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v48, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v38, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v37
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v37
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v36, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v39
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v34, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v35
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v8, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v34, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v35
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v33
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v32, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v32, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v31
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v16, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v18, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v19
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v33
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v16, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v20, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v22, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v8, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v17
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v20, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v2, 16, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v18, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v22, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v24, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v19
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v23
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v25
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v24, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v26, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v25
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v7, 16, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v26, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v8, 16, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v28, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v9
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v119, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v29
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v30, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v118
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v117, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v27
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v28, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v30, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v29
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v11, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v119
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v118, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v116
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v13, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v115
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v117
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v116, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v115
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v114, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v113, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v103
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v112
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v102, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v101, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v14, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v114, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v8, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v10, 16, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v103, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v11, 16, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v13
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v112
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v113, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v102
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v101, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v98, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v100
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v83, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v85
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v13, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v99
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v99
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v12
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v98, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v97, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v82
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v15
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v97
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v11, 16, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v87, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v96
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v87
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v86, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v85, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v96, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v86
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v12, 16, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v84, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v15, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v83, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v84
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v16
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v81
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v82
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v81
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v68
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v16, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v80, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v71, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, v69, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v67, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v65, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v18, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v18, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v71, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v69, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v67, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v66
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v65, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v70
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v68
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v66
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v20
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v64
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v55
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v18, v16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v21, v17
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v23, v19
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v24, v20
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v25, v22
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v70
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v20, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v64
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v22, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v55
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v19, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v21, v20
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v23, v22
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v15
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v17
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v18
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v12, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v19, v20
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v13, 16, v12
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v15, 16, v17
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v16, 16, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v19, 16, v21
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v20, 16, v18
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -27687,13 +27671,12 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u16_e32 v3, 3, v48
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v39
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX9-NEXT: v_add_u16_e32 v2, 3, v38
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v37
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -27701,8 +27684,8 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v35
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_add_u16_e32 v3, 3, v34
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v33
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -27710,8 +27693,8 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v31
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
-; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_add_u16_e32 v4, 3, v16
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v17
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -27719,8 +27702,8 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v19
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
-; GFX9-NEXT: v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_add_u16_e32 v5, 3, v20
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v21
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -27728,8 +27711,8 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v23
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
-; GFX9-NEXT: v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
@@ -27758,8 +27741,8 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v7, 3, v7
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -27772,48 +27755,48 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v8, 3, v8
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_add_u16_e32 v8, 3, v24
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v25
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 3, v47
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
-; GFX9-NEXT: v_add_u16_sdwa v9, v9, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_add_u16_e32 v9, 3, v26
; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v27
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v10, 3, v45
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
-; GFX9-NEXT: v_add_u16_sdwa v10, v10, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: v_add_u16_e32 v10, 3, v28
; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v29
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 3, v42
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
-; GFX9-NEXT: v_add_u16_sdwa v11, v11, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v11
+; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
+; GFX9-NEXT: v_lshl_or_b32 v10, v11, 16, v10
; GFX9-NEXT: v_add_u16_e32 v11, 3, v41
; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v40
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v12, 3, v55
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
-; GFX9-NEXT: v_add_u16_sdwa v12, v12, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: v_add_u16_e32 v12, 3, v62
; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v61
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v13, 3, v60
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
-; GFX9-NEXT: v_add_u16_sdwa v13, v13, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v12, v12, v13
+; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
+; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; GFX9-NEXT: v_add_u16_e32 v13, 3, v58
; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v57
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -27822,8 +27805,8 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v14, 3, v14
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v14, v14, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -27836,8 +27819,8 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v15, 3, v15
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v15, v15, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v14, v14, v15
+; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
+; GFX9-NEXT: v_lshl_or_b32 v14, v15, 16, v14
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -27848,8 +27831,8 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u16_e32 v16, 3, v56
; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
-; GFX9-NEXT: v_add_u16_sdwa v16, v16, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v15, v15, v16
+; GFX9-NEXT: v_add_u16_e32 v16, 0x300, v16
+; GFX9-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; GFX9-NEXT: .LBB50_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
@@ -28225,50 +28208,50 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v16f32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v2 :: v_dual_mov_b32 v54, v0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v1 :: v_dual_mov_b32 v54, v0
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32 offset:128
; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:124
-; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:120
-; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:116
-; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:112
-; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:108
+; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:120
+; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:116
+; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:112
+; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:108
; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:104
; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:100
; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32 offset:96
; GFX11-FAKE16-NEXT: scratch_load_u16 v80, off, s32 offset:92
-; GFX11-FAKE16-NEXT: scratch_load_u16 v81, off, s32 offset:88
-; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:84
-; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:80
-; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:76
-; GFX11-FAKE16-NEXT: scratch_load_u16 v84, off, s32 offset:72
-; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:68
-; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:64
-; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:60
-; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:56
+; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:88
+; GFX11-FAKE16-NEXT: scratch_load_u16 v84, off, s32 offset:84
+; GFX11-FAKE16-NEXT: scratch_load_u16 v81, off, s32 offset:80
+; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:76
+; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:72
+; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:68
+; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:64
+; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:60
+; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:56
; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:52
; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:48
; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:44
-; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:40
-; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:36
-; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:28
+; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:40
+; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:36
+; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:32
+; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_u16 v112, off, s32 offset:24
; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:20
; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:132
; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:16
-; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:12
-; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:8
+; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:12
+; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:8
; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:4
-; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32
+; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32 offset:4
+; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v15 :: v_dual_mov_b32 v32, v14
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v13 :: v_dual_mov_b32 v34, v12
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v11 :: v_dual_mov_b32 v36, v10
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v9 :: v_dual_mov_b32 v38, v8
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v7 :: v_dual_mov_b32 v48, v6
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, v5 :: v_dual_mov_b32 v50, v4
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v3 :: v_dual_mov_b32 v52, v1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v3 :: v_dual_mov_b32 v52, v2
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
@@ -28284,8 +28267,8 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB50_3: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v54, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v53, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v54, v53, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v52, v51, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v50, v49, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v48, v39, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v38, v37, 0xc0c0004
@@ -28306,27 +28289,27 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v26, v27, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v28, v29, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v30, v119, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v118, v117, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v116, v115, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v30, v116, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v119, v118, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v117, v115, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v114, v112, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v113, v103, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v102, v100, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v103, v100, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v113, v102, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v101, v99, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v11, 16, v10
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v13, 16, v12
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v15, 16, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v98, v96, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v97, v87, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v86, v84, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v85, v82, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v83, v81, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v98, v97, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v96, v85, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v87, v86, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v83, v81, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v84, v82, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v70, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v71, v68, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v66, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v67, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v67, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v69, v66, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v65, v55, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v14, 16, v13
@@ -28334,8 +28317,8 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v18, 16, v17
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v20, 16, v19
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
@@ -28364,251 +28347,236 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB50_2
; GFX11-FAKE16-NEXT: .LBB50_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v54, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v53, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v52
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v53
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v52, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v51
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v50, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v48, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v49
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v36, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v39
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v38, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v48, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v38, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v37
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v37
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v36, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v39
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v34, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v35
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v8, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v34, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v35
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v33
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v32, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v32, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v31
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v16, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v18, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v19
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v33
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v16, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v20, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v22, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v8, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v17
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v20, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v2, 16, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v18, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v22, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v24, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v19
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v23
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v25
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v24, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v26, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v25
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v7, 16, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v26, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v8, 16, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v28, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v9
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v119, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v29
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v30, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v118
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v117, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v27
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v28, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v30, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v29
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v11, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v119
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v118, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v116
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v13, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v115
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v117
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v116, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v115
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v114, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v113, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v103
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v112
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v102, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v101, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v14, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v114, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v8, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v10, 16, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v103, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v11, 16, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v13
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v112
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v113, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v102
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v101, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v98, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v100
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v83, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v85
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v13, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v99
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v99
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v12
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v98, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v97, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v82
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v15
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v97
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v11, 16, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v87, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v96
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v87
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v86, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v85, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v96, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v86
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v12, 16, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v84, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v15, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v83, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v84
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v16
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v81
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v82
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v81
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v68
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v16, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v80, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v71, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, v69, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v67, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v65, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v18, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v18, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v71, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v69, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v67, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v66
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v65, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v70
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v68
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v66
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v20
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v64
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v55
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v18, v16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v21, v17
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v23, v19
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v24, v20
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v25, v22
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v70
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v20, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v64
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v22, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v55
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v19, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v21, v20
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v23, v22
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v15
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v17
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v18
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v12, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v19, v20
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v13, 16, v12
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v15, 16, v17
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v16, 16, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v19, 16, v21
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v20, 16, v18
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -41598,13 +41566,12 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u16_e32 v3, 3, v48
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v39
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX9-NEXT: v_add_u16_e32 v2, 3, v38
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v37
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -41612,8 +41579,8 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v35
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_add_u16_e32 v3, 3, v34
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v33
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -41621,8 +41588,8 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v31
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
-; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_add_u16_e32 v4, 3, v16
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v17
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -41630,8 +41597,8 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v19
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
-; GFX9-NEXT: v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_add_u16_e32 v5, 3, v20
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v21
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -41639,8 +41606,8 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v23
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
-; GFX9-NEXT: v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
@@ -41669,8 +41636,8 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v7, 3, v7
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -41683,48 +41650,48 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v8, 3, v8
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_add_u16_e32 v8, 3, v24
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v25
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 3, v47
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
-; GFX9-NEXT: v_add_u16_sdwa v9, v9, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_add_u16_e32 v9, 3, v26
; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v27
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v10, 3, v45
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
-; GFX9-NEXT: v_add_u16_sdwa v10, v10, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: v_add_u16_e32 v10, 3, v28
; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v29
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 3, v42
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
-; GFX9-NEXT: v_add_u16_sdwa v11, v11, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v11
+; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
+; GFX9-NEXT: v_lshl_or_b32 v10, v11, 16, v10
; GFX9-NEXT: v_add_u16_e32 v11, 3, v41
; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v40
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v12, 3, v55
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
-; GFX9-NEXT: v_add_u16_sdwa v12, v12, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: v_add_u16_e32 v12, 3, v62
; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v61
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v13, 3, v60
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
-; GFX9-NEXT: v_add_u16_sdwa v13, v13, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v12, v12, v13
+; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
+; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; GFX9-NEXT: v_add_u16_e32 v13, 3, v58
; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v57
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -41733,8 +41700,8 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v14, 3, v14
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v14, v14, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -41747,8 +41714,8 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v15, 3, v15
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v15, v15, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v14, v14, v15
+; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
+; GFX9-NEXT: v_lshl_or_b32 v14, v15, 16, v14
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -41759,8 +41726,8 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u16_e32 v16, 3, v56
; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
-; GFX9-NEXT: v_add_u16_sdwa v16, v16, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v15, v15, v16
+; GFX9-NEXT: v_add_u16_e32 v16, 0x300, v16
+; GFX9-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; GFX9-NEXT: .LBB70_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
@@ -42136,50 +42103,50 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v8i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v2 :: v_dual_mov_b32 v54, v0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v1 :: v_dual_mov_b32 v54, v0
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32 offset:128
; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:124
-; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:120
-; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:116
-; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:112
-; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:108
+; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:120
+; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:116
+; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:112
+; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:108
; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:104
; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:100
; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32 offset:96
; GFX11-FAKE16-NEXT: scratch_load_u16 v80, off, s32 offset:92
-; GFX11-FAKE16-NEXT: scratch_load_u16 v81, off, s32 offset:88
-; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:84
-; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:80
-; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:76
-; GFX11-FAKE16-NEXT: scratch_load_u16 v84, off, s32 offset:72
-; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:68
-; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:64
-; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:60
-; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:56
+; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:88
+; GFX11-FAKE16-NEXT: scratch_load_u16 v84, off, s32 offset:84
+; GFX11-FAKE16-NEXT: scratch_load_u16 v81, off, s32 offset:80
+; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:76
+; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:72
+; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:68
+; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:64
+; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:60
+; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:56
; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:52
; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:48
; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:44
-; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:40
-; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:36
-; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:28
+; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:40
+; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:36
+; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:32
+; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_u16 v112, off, s32 offset:24
; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:20
; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:132
; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:16
-; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:12
-; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:8
+; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:12
+; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:8
; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:4
-; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32
+; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32 offset:4
+; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v15 :: v_dual_mov_b32 v32, v14
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v13 :: v_dual_mov_b32 v34, v12
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v11 :: v_dual_mov_b32 v36, v10
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v9 :: v_dual_mov_b32 v38, v8
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v7 :: v_dual_mov_b32 v48, v6
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, v5 :: v_dual_mov_b32 v50, v4
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v3 :: v_dual_mov_b32 v52, v1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v3 :: v_dual_mov_b32 v52, v2
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
@@ -42195,8 +42162,8 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB70_3: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v54, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v53, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v54, v53, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v52, v51, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v50, v49, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v48, v39, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v38, v37, 0xc0c0004
@@ -42217,27 +42184,27 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v26, v27, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v28, v29, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v30, v119, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v118, v117, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v116, v115, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v30, v116, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v119, v118, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v117, v115, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v114, v112, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v113, v103, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v102, v100, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v103, v100, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v113, v102, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v101, v99, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v11, 16, v10
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v13, 16, v12
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v15, 16, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v98, v96, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v97, v87, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v86, v84, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v85, v82, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v83, v81, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v98, v97, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v96, v85, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v87, v86, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v83, v81, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v84, v82, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v70, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v71, v68, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v66, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v67, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v67, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v69, v66, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v65, v55, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v14, 16, v13
@@ -42245,8 +42212,8 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v18, 16, v17
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v20, 16, v19
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
@@ -42275,251 +42242,236 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB70_2
; GFX11-FAKE16-NEXT: .LBB70_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v54, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v53, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v52
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v53
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v52, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v51
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v50, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v48, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v49
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v36, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v39
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v38, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v48, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v38, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v37
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v37
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v36, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v39
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v34, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v35
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v8, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v34, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v35
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v33
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v32, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v32, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v31
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v16, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v18, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v19
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v33
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v16, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v20, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v22, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v8, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v17
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v20, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v2, 16, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v18, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v22, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v24, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v19
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v23
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v25
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v24, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v26, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v25
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v7, 16, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v26, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v8, 16, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v28, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v9
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v119, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v29
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v30, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v118
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v117, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v27
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v28, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v30, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v29
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v11, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v119
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v118, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v116
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v13, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v115
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v117
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v116, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v115
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v114, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v113, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v103
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v112
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v102, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v101, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v14, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v114, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v8, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v10, 16, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v103, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v11, 16, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v13
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v112
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v113, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v102
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v101, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v98, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v100
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v83, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v85
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v13, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v99
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v99
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v12
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v98, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v97, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v82
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v15
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v97
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v11, 16, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v87, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v96
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v87
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v86, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v85, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v96, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v86
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v12, 16, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v84, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v15, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v83, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v84
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v16
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v81
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v82
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v81
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v68
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v16, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v80, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v71, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, v69, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v67, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v65, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v18, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v18, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v71, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v69, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v67, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v66
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v65, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v70
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v68
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v66
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v20
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v64
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v55
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v18, v16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v21, v17
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v23, v19
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v24, v20
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v25, v22
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v70
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v20, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v64
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v22, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v55
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v19, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v21, v20
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v23, v22
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v15
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v17
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v18
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v12, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v19, v20
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v13, 16, v12
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v15, 16, v17
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v16, 16, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v19, 16, v21
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v20, 16, v18
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -54976,13 +54928,12 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u16_e32 v3, 3, v48
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v39
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX9-NEXT: v_add_u16_e32 v2, 3, v38
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v37
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -54990,8 +54941,8 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v35
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_add_u16_e32 v3, 3, v34
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v33
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -54999,8 +54950,8 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v31
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
-; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_add_u16_e32 v4, 3, v16
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v17
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -55008,8 +54959,8 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v19
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
-; GFX9-NEXT: v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_add_u16_e32 v5, 3, v20
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v21
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -55017,8 +54968,8 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v23
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
-; GFX9-NEXT: v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
@@ -55047,8 +54998,8 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v7, 3, v7
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -55061,48 +55012,48 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v8, 3, v8
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_add_u16_e32 v8, 3, v24
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v25
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 3, v47
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
-; GFX9-NEXT: v_add_u16_sdwa v9, v9, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_add_u16_e32 v9, 3, v26
; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v27
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v10, 3, v45
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
-; GFX9-NEXT: v_add_u16_sdwa v10, v10, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: v_add_u16_e32 v10, 3, v28
; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v29
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 3, v42
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
-; GFX9-NEXT: v_add_u16_sdwa v11, v11, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v11
+; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
+; GFX9-NEXT: v_lshl_or_b32 v10, v11, 16, v10
; GFX9-NEXT: v_add_u16_e32 v11, 3, v41
; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v40
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v12, 3, v55
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
-; GFX9-NEXT: v_add_u16_sdwa v12, v12, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: v_add_u16_e32 v12, 3, v62
; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v61
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v13, 3, v60
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
-; GFX9-NEXT: v_add_u16_sdwa v13, v13, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v12, v12, v13
+; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
+; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; GFX9-NEXT: v_add_u16_e32 v13, 3, v58
; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v57
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -55111,8 +55062,8 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v14, 3, v14
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v14, v14, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -55125,8 +55076,8 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v15, 3, v15
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_add_u16_sdwa v15, v15, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v14, v14, v15
+; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
+; GFX9-NEXT: v_lshl_or_b32 v14, v15, 16, v14
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -55137,8 +55088,8 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_add_u16_e32 v16, 3, v56
; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
-; GFX9-NEXT: v_add_u16_sdwa v16, v16, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v15, v15, v16
+; GFX9-NEXT: v_add_u16_e32 v16, 0x300, v16
+; GFX9-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; GFX9-NEXT: .LBB86_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
@@ -55514,50 +55465,50 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v8f64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v2 :: v_dual_mov_b32 v54, v0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v1 :: v_dual_mov_b32 v54, v0
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32 offset:128
; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:124
-; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:120
-; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:116
-; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:112
-; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:108
+; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:120
+; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:116
+; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:112
+; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:108
; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:104
; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:100
; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32 offset:96
; GFX11-FAKE16-NEXT: scratch_load_u16 v80, off, s32 offset:92
-; GFX11-FAKE16-NEXT: scratch_load_u16 v81, off, s32 offset:88
-; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:84
-; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:80
-; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:76
-; GFX11-FAKE16-NEXT: scratch_load_u16 v84, off, s32 offset:72
-; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:68
-; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:64
-; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:60
-; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:56
+; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:88
+; GFX11-FAKE16-NEXT: scratch_load_u16 v84, off, s32 offset:84
+; GFX11-FAKE16-NEXT: scratch_load_u16 v81, off, s32 offset:80
+; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:76
+; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:72
+; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:68
+; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:64
+; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:60
+; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:56
; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:52
; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:48
; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:44
-; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:40
-; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:36
-; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:32
-; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:28
+; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:40
+; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:36
+; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:32
+; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:28
; GFX11-FAKE16-NEXT: scratch_load_u16 v112, off, s32 offset:24
; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:20
; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:132
; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:16
-; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:12
-; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:8
+; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:12
+; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:8
; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:4
-; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32
+; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32 offset:4
+; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v15 :: v_dual_mov_b32 v32, v14
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v13 :: v_dual_mov_b32 v34, v12
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v11 :: v_dual_mov_b32 v36, v10
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v9 :: v_dual_mov_b32 v38, v8
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v7 :: v_dual_mov_b32 v48, v6
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, v5 :: v_dual_mov_b32 v50, v4
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v3 :: v_dual_mov_b32 v52, v1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v3 :: v_dual_mov_b32 v52, v2
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
@@ -55573,8 +55524,8 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB86_3: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v54, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v53, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, v54, v53, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v52, v51, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v50, v49, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v48, v39, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v38, v37, 0xc0c0004
@@ -55595,27 +55546,27 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v26, v27, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v28, v29, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v30, v119, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v118, v117, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v116, v115, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v30, v116, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v119, v118, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v117, v115, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v114, v112, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v113, v103, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v102, v100, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v103, v100, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v113, v102, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v101, v99, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v11, 16, v10
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v13, 16, v12
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v15, 16, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v98, v96, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v97, v87, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v86, v84, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v85, v82, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v83, v81, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v98, v97, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v96, v85, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v87, v86, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v83, v81, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v84, v82, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v70, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v71, v68, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v66, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v67, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v67, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v69, v66, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v65, v55, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v14, 16, v13
@@ -55623,8 +55574,8 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v18, 16, v17
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v20, 16, v19
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
@@ -55653,251 +55604,236 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
-; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
+; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB86_2
; GFX11-FAKE16-NEXT: .LBB86_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v54, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v53, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v52
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v53
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v52, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v51
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v50, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v48, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v49
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v36, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v39
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v38, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v48, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v38, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v37
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v37
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v36, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v39
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v34, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v35
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v8, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v34, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v35
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v33
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v32, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v32, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v31
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v16, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v18, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v19
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v33
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v16, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v20, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v22, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v8, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v17
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v20, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v2, 16, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v18, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v22, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v24, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v19
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v23
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v25
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v24, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v26, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v25
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v7, 16, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v26, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v8, 16, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v28, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v9
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v119, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v29
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v30, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v118
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v117, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v27
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v28, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v30, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v29
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v11, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v119
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v118, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v116
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v13, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v115
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v117
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v116, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v115
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v114, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v113, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v103
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v112
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v102, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v101, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v14, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v114, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v8, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v10, 16, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v103, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v11, 16, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v13
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v112
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v113, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v102
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v101, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v98, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v100
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v83, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v85
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v13, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v99
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v99
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v12
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v98, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v97, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v82
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v15
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v97
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v11, 16, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v87, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v96
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v87
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v86, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v85, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v96, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v86
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v12, 16, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v84, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v15, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v83, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v84
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v16
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v81
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v82
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v81
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v68
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v16, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v80, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v71, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, v69, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v67, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v65, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v18, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v18, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v71, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v69, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v67, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v66
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v65, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v70
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v68
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v66
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v20
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v64
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v55
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v18, v16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v21, v17
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v23, v19
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v24, v20
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v25, v22
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v70
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v20, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v64
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v22, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v55
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v19, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v21, v20
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v23, v22
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v15
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v17
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v18
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v12, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v19, v20
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v13, 16, v12
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v15, 16, v17
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v16, 16, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v19, 16, v21
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v20, 16, v18
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
index 77c047f492cac..e173dd870e46e 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
@@ -3124,11 +3124,10 @@ define i64 @bitcast_v8i8_to_i64(<8 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v3
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -3136,8 +3135,8 @@ define i64 @bitcast_v8i8_to_i64(<8 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v7
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -3238,36 +3237,33 @@ define i64 @bitcast_v8i8_to_i64(<8 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: .LBB26_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v9, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -6302,11 +6298,10 @@ define double @bitcast_v8i8_to_f64(<8 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v3
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -6314,8 +6309,8 @@ define double @bitcast_v8i8_to_f64(<8 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v7
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -6416,36 +6411,33 @@ define double @bitcast_v8i8_to_f64(<8 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: .LBB50_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v9, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -9159,11 +9151,10 @@ define <2 x i32> @bitcast_v8i8_to_v2i32(<8 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v3
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -9171,8 +9162,8 @@ define <2 x i32> @bitcast_v8i8_to_v2i32(<8 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v7
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -9273,36 +9264,33 @@ define <2 x i32> @bitcast_v8i8_to_v2i32(<8 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: .LBB70_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v9, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -11725,11 +11713,10 @@ define <2 x float> @bitcast_v8i8_to_v2f32(<8 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v3
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -11737,8 +11724,8 @@ define <2 x float> @bitcast_v8i8_to_v2f32(<8 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v7
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -11839,36 +11826,33 @@ define <2 x float> @bitcast_v8i8_to_v2f32(<8 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: .LBB86_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v9, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -13987,11 +13971,10 @@ define <4 x i16> @bitcast_v8i8_to_v4i16(<8 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v3
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -13999,8 +13982,8 @@ define <4 x i16> @bitcast_v8i8_to_v4i16(<8 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v7
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -14101,36 +14084,33 @@ define <4 x i16> @bitcast_v8i8_to_v4i16(<8 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: .LBB98_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v9, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -15856,11 +15836,10 @@ define <4 x half> @bitcast_v8i8_to_v4f16(<8 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v3
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -15868,8 +15847,8 @@ define <4 x half> @bitcast_v8i8_to_v4f16(<8 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v7
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -15970,36 +15949,33 @@ define <4 x half> @bitcast_v8i8_to_v4f16(<8 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: .LBB106_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v9, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -17217,11 +17193,10 @@ define <4 x bfloat> @bitcast_v8i8_to_v4bf16(<8 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v3
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -17229,8 +17204,8 @@ define <4 x bfloat> @bitcast_v8i8_to_v4bf16(<8 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v7
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -17331,36 +17306,33 @@ define <4 x bfloat> @bitcast_v8i8_to_v4bf16(<8 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: .LBB110_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v9, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v4, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
index a1c0db086bf3c..7cb5348f9bb5e 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
@@ -1081,11 +1081,10 @@ define <3 x i32> @bitcast_v12i8_to_v3i32(<12 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v15
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v3
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -1093,8 +1092,8 @@ define <3 x i32> @bitcast_v12i8_to_v3i32(<12 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v7
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_add_u16_e32 v2, 3, v8
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v9
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -1102,8 +1101,8 @@ define <3 x i32> @bitcast_v12i8_to_v3i32(<12 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v11
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -1227,44 +1226,41 @@ define <3 x i32> @bitcast_v12i8_to_v3i32(<12 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: .LBB6_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v14, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v15, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v8, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v15, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v10, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v6
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -4244,11 +4240,10 @@ define <3 x float> @bitcast_v12i8_to_v3f32(<12 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v15
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v3
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -4256,8 +4251,8 @@ define <3 x float> @bitcast_v12i8_to_v3f32(<12 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v7
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_add_u16_e32 v2, 3, v8
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v9
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -4265,8 +4260,8 @@ define <3 x float> @bitcast_v12i8_to_v3f32(<12 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v11
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -4390,44 +4385,41 @@ define <3 x float> @bitcast_v12i8_to_v3f32(<12 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: .LBB22_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v14, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v15, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v8, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v15, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v10, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v6
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -6930,11 +6922,10 @@ define <6 x bfloat> @bitcast_v12i8_to_v6bf16(<12 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v13
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v16
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -6942,8 +6933,8 @@ define <6 x bfloat> @bitcast_v12i8_to_v6bf16(<12 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v7
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_add_u16_e32 v2, 3, v8
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v9
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -6951,8 +6942,8 @@ define <6 x bfloat> @bitcast_v12i8_to_v6bf16(<12 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v11
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -7077,44 +7068,41 @@ define <6 x bfloat> @bitcast_v12i8_to_v6bf16(<12 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: .LBB36_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v15, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v13, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v8, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v13, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v10, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v16
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v6
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -8754,11 +8742,10 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v13
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v16
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -8766,8 +8753,8 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v7
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_add_u16_e32 v2, 3, v8
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v9
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -8775,8 +8762,8 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v11
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -8901,44 +8888,41 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: .LBB40_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v15, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v13, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v8, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v13, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v10, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v16
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v6
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -10117,11 +10101,10 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v13
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v16
-; GFX9-NEXT: s_movk_i32 s6, 0x300
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_add_u16_e32 v1, 3, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v5
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -10129,8 +10112,8 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v7
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
-; GFX9-NEXT: v_add_u16_sdwa v2, v2, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_add_u16_e32 v2, 3, v8
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v9
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
@@ -10138,8 +10121,8 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v11
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
-; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -10264,44 +10247,41 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: .LBB44_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v15, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v13, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v8, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v13, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v10, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v16
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v6
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
diff --git a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
index d9f64f01a4b4d..2beecd9a64afb 100644
--- a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
+++ b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
@@ -3741,100 +3741,98 @@ define amdgpu_cs void @amdgpu_cs_v32i1(<32 x i1> %arg0) {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 1, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 1, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 1, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 3, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 1, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 2, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 1, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 1, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 1, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 1, v26
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 1, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 1, v24
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 1, v22
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 1, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 1, v20
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 1, v18
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 1, v17
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 1, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 1, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 1, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 1, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 1, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 1, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 3, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 3, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 2, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 3, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 2, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v5
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 3, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 2, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 1, v30
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 1, v29
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 1, v28
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 3, v27
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 2, v26
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v24, v25
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 3, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 2, v22
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 3, v19
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 2, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v16, v17
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 3, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 2, v14
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v12, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 3, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 3, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 3, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 15, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 1, v29
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 1, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 1, v28
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 1, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 1, v24
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v12, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 3, v27
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 2, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 1, v22
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 1, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 1, v20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 1, v18
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 1, v17
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 1, v16
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 3, v31
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 2, v30
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v28, v29
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v27, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 3, v24
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v23, v22
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 3, v20
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v18
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 3, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v15, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 3, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 1, v30
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v8, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 3, v23
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 2, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 3, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 2, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 3, v31
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 2, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 3, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 3, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 3, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v11, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 3, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v7, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v31, v30
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 3, v28
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v24, v26
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v20, v21
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v16, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 15, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 4, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 15, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v27, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 15, v24
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 4, v20
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 15, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 4, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 15, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 12, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 12, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 12, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 12, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v22
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: global_store_b32 v[0:1], v0, off
; GFX11-FAKE16-NEXT: s_endpgm
;
@@ -3919,84 +3917,81 @@ define amdgpu_cs void @amdgpu_cs_v32i1(<32 x i1> %arg0) {
; GFX1250-FAKE16-LABEL: amdgpu_cs_v32i1:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-FAKE16-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v18, 1, v18
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v19, 3, v19
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v22, 1, v22
; GFX1250-FAKE16-NEXT: v_and_b32_e32 v6, 1, v6
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v3, 3, v3
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v17, 1, v17
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v18, 2, v18
; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v7, 3, v7
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v21, 1, v21
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v6, 2, v6
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v16, v16, v17, 1 bitop3:0xec
+; GFX1250-FAKE16-NEXT: v_or_b32_e32 v18, v19, v18
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v19, 2, v22
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v22, 1, v26
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v17, 3, v23
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v23, 1, v25
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v24, 1, v24
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v25, 3, v27
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v22, 2, v22
+; GFX1250-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v7, 1, v10
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v10, 1, v14
+; GFX1250-FAKE16-NEXT: v_or_b32_e32 v17, v17, v19
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v19, v20, v21, 1 bitop3:0xec
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v20, 1, v30
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v21, v24, 3, v23 bitop3:0xc8
+; GFX1250-FAKE16-NEXT: v_or_b32_e32 v22, v25, v22
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v2, 1, v2
; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v5, 1, v5
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v9, 1, v9
+; GFX1250-FAKE16-NEXT: v_and_b32_e32 v8, 1, v8
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v11, 3, v11
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v7, 2, v7
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v14, 3, v15
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v10, 2, v10
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v13, 1, v13
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v16, v16, v18, 3 bitop3:0xec
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v18, 3, v31
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v20, 2, v20
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v17, v19, v17, 3 bitop3:0xec
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v19, v21, 15, v22 bitop3:0xc8
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v21, 1, v29
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v3, 3, v3
; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v2, 2, v2
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v6, 2, v6
; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v1, 1, v1
-; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v4, v4, v5, 1 bitop3:0xec
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v5, v8, 3, v9 bitop3:0xc8
+; GFX1250-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
+; GFX1250-FAKE16-NEXT: v_or_b32_e32 v8, v14, v10
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v9, v12, v13, 1 bitop3:0xec
+; GFX1250-FAKE16-NEXT: v_or_b32_e32 v18, v18, v20
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v20, v28, v21, 1 bitop3:0xec
; GFX1250-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1250-FAKE16-NEXT: v_or_b32_e32 v3, v7, v6
-; GFX1250-FAKE16-NEXT: v_and_b32_e32 v6, 1, v10
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v5, 1, v9
-; GFX1250-FAKE16-NEXT: v_and_b32_e32 v7, 1, v8
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v8, 3, v11
-; GFX1250-FAKE16-NEXT: v_bitop3_b16 v3, v4, v3, 3 bitop3:0xec
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v6, 2, v6
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, 1 bitop3:0xec
-; GFX1250-FAKE16-NEXT: v_bitop3_b16 v4, v7, 3, v5 bitop3:0xc8
-; GFX1250-FAKE16-NEXT: v_and_b32_e32 v1, 1, v14
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v7, 3, v23
-; GFX1250-FAKE16-NEXT: v_or_b32_e32 v5, v8, v6
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v6, 3, v15
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v1, v4, v6, 3 bitop3:0xec
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v3, v5, 15, v7 bitop3:0xc8
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v4, v9, v8, 3 bitop3:0xec
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v5, v20, v18, 3 bitop3:0xec
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v2, 3 bitop3:0xec
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v1, 2, v1
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v2, 1, v13
-; GFX1250-FAKE16-NEXT: v_bitop3_b16 v4, v4, 15, v5 bitop3:0xc8
-; GFX1250-FAKE16-NEXT: v_and_b32_e32 v5, 1, v22
-; GFX1250-FAKE16-NEXT: v_and_b32_e32 v9, 1, v26
-; GFX1250-FAKE16-NEXT: v_and_b32_e32 v11, 1, v30
-; GFX1250-FAKE16-NEXT: v_or_b32_e32 v1, v6, v1
-; GFX1250-FAKE16-NEXT: v_bitop3_b16 v2, v12, v2, 1 bitop3:0xec
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v5, 2, v5
-; GFX1250-FAKE16-NEXT: v_and_b32_e32 v6, 1, v18
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v10, 1, v25
-; GFX1250-FAKE16-NEXT: v_and_b32_e32 v12, 1, v24
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v13, 3, v27
-; GFX1250-FAKE16-NEXT: v_or_b32_e32 v5, v7, v5
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v7, 1, v21
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v9, 2, v9
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v14, 3, v31
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v11, 2, v11
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v15, 1, v29
-; GFX1250-FAKE16-NEXT: v_bitop3_b16 v1, v2, v1, 3 bitop3:0xec
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v2, 3, v19
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v6, 2, v6
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v8, 1, v17
-; GFX1250-FAKE16-NEXT: v_bitop3_b16 v7, v20, v7, 1 bitop3:0xec
-; GFX1250-FAKE16-NEXT: v_bitop3_b16 v10, v12, 3, v10 bitop3:0xc8
-; GFX1250-FAKE16-NEXT: v_or_b32_e32 v9, v13, v9
-; GFX1250-FAKE16-NEXT: v_or_b32_e32 v11, v14, v11
-; GFX1250-FAKE16-NEXT: v_bitop3_b16 v12, v28, v15, 1 bitop3:0xec
-; GFX1250-FAKE16-NEXT: v_or_b32_e32 v2, v2, v6
-; GFX1250-FAKE16-NEXT: v_bitop3_b16 v6, v16, v8, 1 bitop3:0xec
-; GFX1250-FAKE16-NEXT: v_bitop3_b16 v5, v7, v5, 3 bitop3:0xec
-; GFX1250-FAKE16-NEXT: v_bitop3_b16 v7, v10, 15, v9 bitop3:0xc8
-; GFX1250-FAKE16-NEXT: v_bitop3_b16 v8, v12, v11, 3 bitop3:0xec
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v3, 4, v3
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v4
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v1, 12, v1
-; GFX1250-FAKE16-NEXT: v_bitop3_b16 v2, v6, v2, 3 bitop3:0xec
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v5, 4, v5
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v7
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v7, 12, v8
-; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v3, 15 bitop3:0xec
-; GFX1250-FAKE16-NEXT: v_or_b32_e32 v1, v1, v4
-; GFX1250-FAKE16-NEXT: v_bitop3_b16 v2, v2, v5, 15 bitop3:0xec
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v1, 4, v1
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v3
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v3, 12, v4
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v4, 4, v17
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v19
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v5, 12, v5
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, 15 bitop3:0xec
+; GFX1250-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
+; GFX1250-FAKE16-NEXT: v_bitop3_b16 v2, v16, v4, 15 bitop3:0xec
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-FAKE16-NEXT: v_or_b32_e32 v3, v7, v6
+; GFX1250-FAKE16-NEXT: v_or_b32_e32 v3, v5, v6
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, 0xff bitop3:0xec
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v1, v2, v3, 0xff bitop3:0xec
; GFX1250-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX1250-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX1250-FAKE16-NEXT: global_store_b32 v[0:1], v0, off
; GFX1250-FAKE16-NEXT: s_endpgm
store <32 x i1> %arg0, ptr addrspace(1) poison
diff --git a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
index bb9595d8592c0..f072b07761c91 100644
--- a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
+++ b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
@@ -1676,27 +1676,27 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(ptr addrspace(1) noalias %o
; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x34
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_load_dword v0, v0, s[0:1]
; GFX10-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffffff00, v0
-; GFX10-NEXT: v_add_nc_u16 v4, v0, 9
-; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff00, v1
-; GFX10-NEXT: v_add_nc_u16 v1, v1, 9
-; GFX10-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX10-NEXT: v_or_b32_sdwa v2, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX10-NEXT: v_mov_b32_e32 v4, 0
-; GFX10-NEXT: v_cvt_f32_ubyte3_e32 v3, v0
+; GFX10-NEXT: v_and_b32_e32 v1, 0xffffff00, v0
+; GFX10-NEXT: v_add_nc_u16 v2, v0, 9
+; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX10-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff00, v3
+; GFX10-NEXT: v_add_nc_u16 v3, v3, 9
; GFX10-NEXT: v_add_nc_u16 v1, 0x900, v1
-; GFX10-NEXT: v_add_nc_u16 v5, 0x900, v2
-; GFX10-NEXT: v_cvt_f32_ubyte2_e32 v2, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v1
+; GFX10-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX10-NEXT: v_cvt_f32_ubyte3_e32 v3, v0
+; GFX10-NEXT: v_and_b32_e32 v5, 0xffff, v1
; GFX10-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
+; GFX10-NEXT: v_add_nc_u16 v6, 0x900, v2
+; GFX10-NEXT: v_cvt_f32_ubyte2_e32 v2, v0
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
-; GFX10-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX10-NEXT: global_store_dword v4, v5, s[2:3]
@@ -1712,7 +1712,6 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(ptr addrspace(1) noalias %o
; GFX9-NEXT: global_load_dword v4, v0, s[0:1]
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-NEXT: s_movk_i32 s4, 0xff00
-; GFX9-NEXT: s_movk_i32 s5, 0x900
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cvt_f32_ubyte3_e32 v3, v4
; GFX9-NEXT: v_cvt_f32_ubyte2_e32 v2, v4
@@ -1728,8 +1727,8 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(ptr addrspace(1) noalias %o
; GFX9-NEXT: v_or_b32_sdwa v0, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_or_b32_sdwa v1, v9, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_u16_e32 v0, 0x900, v0
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e32 v1, 0x900, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: global_store_dword v5, v0, s[2:3]
; GFX9-NEXT: s_endpgm
;
@@ -1776,30 +1775,28 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(ptr addrspace(1) noalias %o
; GFX11-FAKE16-NEXT: global_load_b32 v0, v0, s[0:1]
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v0, 9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffffff00, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v1, 9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffffff00, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v0, 9
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffffff00, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v2
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, 0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v2, 9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffffff00, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x900, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v3, 0xff, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x900, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-FAKE16-NEXT: v_cvt_f32_ubyte3_e32 v3, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x900, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x900, v2
; GFX11-FAKE16-NEXT: v_cvt_f32_ubyte2_e32 v2, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1
; GFX11-FAKE16-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
; GFX11-FAKE16-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: global_store_b128 v4, v[0:3], s[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp.ll b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp.ll
index 767849bed5bac..ca2dedbdd51fa 100644
--- a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp.ll
+++ b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp.ll
@@ -825,13 +825,13 @@ define <4 x i8> @to_f8e4m3fn_v4f32(<4 x float> %x) {
; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v2, v2
; CHECK-NEXT: v_lshlrev_b16_e32 v3, 8, v3
; CHECK-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc
-; CHECK-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; CHECK-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; CHECK-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; CHECK-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; CHECK-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; CHECK-NEXT: v_or_b32_e32 v1, v1, v3
-; CHECK-NEXT: v_lshrrev_b32_e32 v3, 24, v3
+; CHECK-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; CHECK-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; CHECK-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; CHECK-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; CHECK-NEXT: s_setpc_b64 s[30:31]
%r = call <4 x i8> @llvm.convert.to.arbitrary.fp.v4i8.v4f32(<4 x float> %x, metadata !"Float8E4M3FN", metadata !"round.tonearest", i1 false)
ret <4 x i8> %r
@@ -1046,13 +1046,13 @@ define <4 x i8> @to_f8e5m2_v4f32(<4 x float> %x) {
; CHECK-NEXT: v_cmp_o_f32_e32 vcc, v2, v2
; CHECK-NEXT: v_lshlrev_b16_e32 v3, 8, v3
; CHECK-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
-; CHECK-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; CHECK-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; CHECK-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; CHECK-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; CHECK-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; CHECK-NEXT: v_or_b32_e32 v1, v1, v3
-; CHECK-NEXT: v_lshrrev_b32_e32 v3, 24, v3
+; CHECK-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; CHECK-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; CHECK-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; CHECK-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; CHECK-NEXT: s_setpc_b64 s[30:31]
%r = call <4 x i8> @llvm.convert.to.arbitrary.fp.v4i8.v4f32(<4 x float> %x, metadata !"Float8E5M2", metadata !"round.tonearest", i1 false)
ret <4 x i8> %r
diff --git a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
index ff08c1ac4d30e..afd9ec131865c 100644
--- a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
@@ -2702,10 +2702,10 @@ define <4 x i8> @test_signed_v4f16_v4i8(<4 x half> %f) {
; GFX9-NEXT: v_med3_i16 v2, v2, s4, v3
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX9-NEXT: v_or_b32_sdwa v2, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v1
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v1
-; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v4
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v4
+; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_signed_v4f16_v4i8:
@@ -2730,7 +2730,7 @@ define <4 x i8> @test_signed_v4f16_v4i8(<4 x half> %f) {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -2787,7 +2787,7 @@ define <4 x i8> @test_signed_v4f16_v4i8(<4 x half> %f) {
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
; GFX12-FAKE16-NEXT: v_or_b32_e32 v0, v0, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v1, v1, v4
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v4
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -4378,20 +4378,22 @@ define <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) {
; GFX9-LABEL: test_signed_v8f16_v8i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_i16_f16_e32 v4, v2
+; GFX9-NEXT: v_cvt_i16_f16_e32 v4, v3
; GFX9-NEXT: s_movk_i32 s4, 0xff80
; GFX9-NEXT: v_mov_b32_e32 v7, 0x7f
-; GFX9-NEXT: v_cvt_i16_f16_sdwa v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_med3_i16 v2, v2, s4, v7
-; GFX9-NEXT: v_med3_i16 v4, v4, s4, v7
-; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v2
-; GFX9-NEXT: v_or_b32_sdwa v8, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_cvt_i16_f16_e32 v2, v3
; GFX9-NEXT: v_cvt_i16_f16_sdwa v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-NEXT: v_med3_i16 v3, v3, s4, v7
-; GFX9-NEXT: v_med3_i16 v2, v2, s4, v7
+; GFX9-NEXT: v_med3_i16 v4, v4, s4, v7
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3
-; GFX9-NEXT: v_or_b32_sdwa v6, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v6, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_cvt_i16_f16_e32 v3, v2
+; GFX9-NEXT: v_cvt_i16_f16_sdwa v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_med3_i16 v2, v2, s4, v7
+; GFX9-NEXT: v_med3_i16 v3, v3, s4, v7
+; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v2
+; GFX9-NEXT: v_or_b32_sdwa v8, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v8
+; GFX9-NEXT: v_lshl_or_b32 v4, v6, 16, v2
; GFX9-NEXT: v_cvt_i16_f16_e32 v2, v1
; GFX9-NEXT: v_cvt_i16_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-NEXT: v_med3_i16 v1, v1, s4, v7
@@ -4400,67 +4402,66 @@ define <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) {
; GFX9-NEXT: v_or_b32_sdwa v2, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_cvt_i16_f16_e32 v1, v0
; GFX9-NEXT: v_cvt_i16_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v6
; GFX9-NEXT: v_med3_i16 v0, v0, s4, v7
-; GFX9-NEXT: v_or_b32_sdwa v4, v8, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX9-NEXT: v_med3_i16 v1, v1, s4, v7
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v4
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v7, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v6
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v7
; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[3:4]
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v9
; GFX9-NEXT: v_mov_b32_e32 v4, v8
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_signed_v8f16_v8i8:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v2, v2
-; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v5, v3
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v4, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v2, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v4, v4
-; GFX11-FAKE16-NEXT: s_movk_i32 s0, 0xff80
-; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v1, v1
+; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v5, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
+; GFX11-FAKE16-NEXT: s_movk_i32 s0, 0xff80
+; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v3, v3
; GFX11-FAKE16-NEXT: v_med3_i16 v2, v2, s0, 0x7f
+; GFX11-FAKE16-NEXT: v_med3_i16 v5, v5, s0, 0x7f
+; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v1, v1
; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v6, v6
+; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v7, v7
; GFX11-FAKE16-NEXT: v_med3_i16 v4, v4, s0, 0x7f
-; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v3, v3
-; GFX11-FAKE16-NEXT: v_med3_i16 v1, v1, s0, 0x7f
+; GFX11-FAKE16-NEXT: v_med3_i16 v3, v3, s0, 0x7f
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT: v_med3_i16 v1, v1, s0, 0x7f
; GFX11-FAKE16-NEXT: v_med3_i16 v6, v6, s0, 0x7f
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v4
-; GFX11-FAKE16-NEXT: v_med3_i16 v5, v5, s0, 0x7f
-; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v7, v7
-; GFX11-FAKE16-NEXT: v_med3_i16 v3, v3, s0, 0x7f
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v2, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX11-FAKE16-NEXT: v_med3_i16 v7, v7, s0, 0x7f
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v2, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v6
; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v1, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v5, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v4, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v1, v2
; GFX11-FAKE16-NEXT: v_med3_i16 v0, v0, s0, 0x7f
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v6, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v3, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 24, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[4:5]
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v7
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 24, v9
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, v8
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -4516,50 +4517,50 @@ define <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v2, v2
-; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v5, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v4, v3
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v2, v2
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v4, v4
-; GFX12-FAKE16-NEXT: s_movk_i32 s0, 0xff80
-; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v1, v1
+; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v5, v5
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
+; GFX12-FAKE16-NEXT: s_movk_i32 s0, 0xff80
+; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v3, v3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_med3_i16 v2, v2, s0, 0x7f
+; GFX12-FAKE16-NEXT: v_med3_i16 v5, v5, s0, 0x7f
+; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v1, v1
; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v6, v6
+; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v7, v7
; GFX12-FAKE16-NEXT: v_med3_i16 v4, v4, s0, 0x7f
-; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v3, v3
-; GFX12-FAKE16-NEXT: v_med3_i16 v1, v1, s0, 0x7f
+; GFX12-FAKE16-NEXT: v_med3_i16 v3, v3, s0, 0x7f
; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
+; GFX12-FAKE16-NEXT: v_med3_i16 v1, v1, s0, 0x7f
; GFX12-FAKE16-NEXT: v_med3_i16 v6, v6, s0, 0x7f
-; GFX12-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v4
-; GFX12-FAKE16-NEXT: v_med3_i16 v5, v5, s0, 0x7f
-; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v7, v7
-; GFX12-FAKE16-NEXT: v_med3_i16 v3, v3, s0, 0x7f
-; GFX12-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v6
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, v2, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX12-FAKE16-NEXT: v_med3_i16 v7, v7, s0, 0x7f
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX12-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, v2, v5
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v6
; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v0, v0
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v2, v1, v6
-; GFX12-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v7
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v6, v5, v3
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v6, v4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v8
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v2, v1, v2
; GFX12-FAKE16-NEXT: v_med3_i16 v0, v0, s0, 0x7f
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v1
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v7
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v5, v6, 16, v3
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, v5, v4
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v5, v3, v7
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 24, v7
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v9
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX12-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[4:5]
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v0, v0, v7
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 24, v9
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v8
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6912,23 +6913,23 @@ define <4 x i8> @test_signed_v4f32_v4i8(<4 x float> %f) {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v3
-; GFX9-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX9-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX9-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX9-NEXT: s_movk_i32 s4, 0xff80
; GFX9-NEXT: v_mov_b32_e32 v4, 0x7f
-; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX9-NEXT: v_med3_i32 v3, v3, s4, v4
+; GFX9-NEXT: v_med3_i32 v1, v1, s4, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3
; GFX9-NEXT: v_med3_i32 v2, v2, s4, v4
-; GFX9-NEXT: v_med3_i32 v1, v1, s4, v4
-; GFX9-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX9-NEXT: v_med3_i32 v0, v0, s4, v4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX9-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_signed_v4f32_v4i8:
@@ -6936,8 +6937,8 @@ define <4 x i8> @test_signed_v4f32_v4i8(<4 x float> %f) {
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_cvt_i32_f32_e32 v3, v3
; GFX11-FAKE16-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX11-FAKE16-NEXT: s_movk_i32 s0, 0xff80
; GFX11-FAKE16-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT: s_movk_i32 s0, 0xff80
; GFX11-FAKE16-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX11-FAKE16-NEXT: v_med3_i32 v3, v3, s0, 0x7f
; GFX11-FAKE16-NEXT: v_med3_i32 v2, v2, s0, 0x7f
@@ -6951,7 +6952,7 @@ define <4 x i8> @test_signed_v4f32_v4i8(<4 x float> %f) {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v2, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v4
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -6990,8 +6991,8 @@ define <4 x i8> @test_signed_v4f32_v4i8(<4 x float> %f) {
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: v_cvt_i32_f32_e32 v3, v3
; GFX12-FAKE16-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX12-FAKE16-NEXT: s_movk_i32 s0, 0xff80
; GFX12-FAKE16-NEXT: v_cvt_i32_f32_e32 v1, v1
+; GFX12-FAKE16-NEXT: s_movk_i32 s0, 0xff80
; GFX12-FAKE16-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_med3_i32 v3, v3, s0, 0x7f
@@ -7006,7 +7007,7 @@ define <4 x i8> @test_signed_v4f32_v4i8(<4 x float> %f) {
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v3, v2, 16, v3
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v4
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
index f8a5331960b0b..12da957613996 100644
--- a/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
@@ -2493,10 +2493,10 @@ define <4 x i8> @test_unsigned_v4f16_v4i8(<4 x half> %f) {
; GFX9-NEXT: v_min_u16_e32 v2, 0xff, v2
; GFX9-NEXT: v_min_u16_sdwa v1, v1, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v2, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v4, v3, v1
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v1
-; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v4
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v3
+; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_unsigned_v4f16_v4i8:
@@ -2518,7 +2518,7 @@ define <4 x i8> @test_unsigned_v4f16_v4i8(<4 x half> %f) {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -2568,7 +2568,7 @@ define <4 x i8> @test_unsigned_v4f16_v4i8(<4 x half> %f) {
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
; GFX12-FAKE16-NEXT: v_or_b32_e32 v0, v0, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v1, v1, v4
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v4
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -4066,80 +4066,81 @@ define <8 x i8> @test_unsigned_v8f16_v8i8(<8 x half> %f) {
; GFX9-LABEL: test_unsigned_v8f16_v8i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_u16_f16_e32 v4, v2
+; GFX9-NEXT: v_cvt_u16_f16_e32 v4, v3
; GFX9-NEXT: s_movk_i32 s4, 0xff
-; GFX9-NEXT: v_cvt_u16_f16_sdwa v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_min_u16_e32 v4, 0xff, v4
-; GFX9-NEXT: v_min_u16_sdwa v2, v2, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v8, v4, v2
-; GFX9-NEXT: v_cvt_u16_f16_e32 v2, v3
; GFX9-NEXT: v_cvt_u16_f16_sdwa v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_min_u16_e32 v2, 0xff, v2
+; GFX9-NEXT: v_min_u16_e32 v4, 0xff, v4
; GFX9-NEXT: v_min_u16_sdwa v3, v3, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v6, v2, v3
+; GFX9-NEXT: v_or_b32_e32 v6, v4, v3
+; GFX9-NEXT: v_cvt_u16_f16_e32 v3, v2
+; GFX9-NEXT: v_cvt_u16_f16_sdwa v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_min_u16_e32 v3, 0xff, v3
+; GFX9-NEXT: v_min_u16_sdwa v2, v2, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_e32 v8, v3, v2
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v8
+; GFX9-NEXT: v_lshl_or_b32 v4, v6, 16, v2
; GFX9-NEXT: v_cvt_u16_f16_e32 v2, v1
; GFX9-NEXT: v_cvt_u16_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-NEXT: v_min_u16_e32 v2, 0xff, v2
; GFX9-NEXT: v_min_u16_sdwa v1, v1, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v6
; GFX9-NEXT: v_or_b32_e32 v2, v2, v1
; GFX9-NEXT: v_cvt_u16_f16_e32 v1, v0
; GFX9-NEXT: v_cvt_u16_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_or_b32_sdwa v4, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX9-NEXT: v_min_u16_e32 v1, 0xff, v1
-; GFX9-NEXT: v_min_u16_sdwa v9, v0, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_min_u16_sdwa v7, v0, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; GFX9-NEXT: v_or_b32_e32 v0, v1, v9
-; GFX9-NEXT: v_or_b32_e32 v1, v9, v3
+; GFX9-NEXT: v_or_b32_e32 v0, v1, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v6
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v7
; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[3:4]
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v9
; GFX9-NEXT: v_mov_b32_e32 v4, v8
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_unsigned_v8f16_v8i8:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v4, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v4, v3
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v3, v3
; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v2, v2
; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v5, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
+; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v3, v3
; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v6, v6
; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v7, v7
-; GFX11-FAKE16-NEXT: v_min_u16 v2, 0xff, v2
; GFX11-FAKE16-NEXT: v_min_u16 v5, 0xff, v5
-; GFX11-FAKE16-NEXT: v_min_u16 v6, 0xff, v6
-; GFX11-FAKE16-NEXT: v_min_u16 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_min_u16 v2, 0xff, v2
; GFX11-FAKE16-NEXT: v_min_u16 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v2
+; GFX11-FAKE16-NEXT: v_min_u16 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v7, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_min_u16 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v6
+; GFX11-FAKE16-NEXT: v_min_u16 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v2, v5
; GFX11-FAKE16-NEXT: v_min_u16 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v4, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v3, v5
; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v1, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v1, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v4, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_min_u16 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v3, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 24, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v6, 16, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v7
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 24, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[4:5]
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: test_unsigned_v8f16_v8i8:
@@ -4189,45 +4190,45 @@ define <8 x i8> @test_unsigned_v8f16_v8i8(<8 x half> %f) {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v4, v2
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v4, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v3, v3
; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v2, v2
; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v5, v5
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
+; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v3, v3
; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v6, v6
; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v1, v1
-; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v7, v7
-; GFX12-FAKE16-NEXT: v_min_u16 v2, 0xff, v2
; GFX12-FAKE16-NEXT: v_min_u16 v5, 0xff, v5
-; GFX12-FAKE16-NEXT: v_min_u16 v6, 0xff, v6
-; GFX12-FAKE16-NEXT: v_min_u16 v4, 0xff, v4
+; GFX12-FAKE16-NEXT: v_min_u16 v2, 0xff, v2
; GFX12-FAKE16-NEXT: v_min_u16 v3, 0xff, v3
-; GFX12-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v2
+; GFX12-FAKE16-NEXT: v_min_u16 v6, 0xff, v6
+; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v7, v7
; GFX12-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX12-FAKE16-NEXT: v_min_u16 v1, 0xff, v1
-; GFX12-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v6
+; GFX12-FAKE16-NEXT: v_min_u16 v4, 0xff, v4
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v6
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, v2, v5
; GFX12-FAKE16-NEXT: v_min_u16 v7, 0xff, v7
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, v4, v2
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v6, v3, v5
; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v0, v0
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v2, v1, v9
-; GFX12-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v7
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v2, v1, v6
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v6, v4, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v8
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX12-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX12-FAKE16-NEXT: v_min_u16 v0, 0xff, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v1
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v5, v3, v7
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 24, v7
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, v9, v4
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v5, v6, 16, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v7
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v0, v0, v7
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 24, v9
; GFX12-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[4:5]
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v8
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v9
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_unsigned_v8f16_v8i8:
@@ -6411,14 +6412,14 @@ define <4 x i8> @test_unsigned_v4f32_v4i8(<4 x float> %f) {
; GFX9-NEXT: s_movk_i32 s4, 0xff
; GFX9-NEXT: v_min_u32_sdwa v3, v3, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_min_u32_e32 v2, 0xff, v2
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_min_u32_sdwa v1, v1, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_min_u32_e32 v0, 0xff, v0
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_unsigned_v4f32_v4i8:
@@ -6438,7 +6439,7 @@ define <4 x i8> @test_unsigned_v4f32_v4i8(<4 x float> %f) {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v2, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v4
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
@@ -6486,7 +6487,7 @@ define <4 x i8> @test_unsigned_v4f32_v4i8(<4 x float> %f) {
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v1
; GFX12-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v3, v2, 16, v3
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v4
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll b/llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
index a090a1b804677..258e51239c491 100644
--- a/llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
@@ -23,9 +23,7 @@ define void @test_i8load_v4i8store(ptr addrspace(1) %ptr_a, ptr addrspace(1) %pt
; GCN-SDAG-FAKE16-NEXT: v_perm_b32 v1, v10, v7, 0xc0c0004
; GCN-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GCN-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v6, v0
-; GCN-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GCN-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GCN-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
+; GCN-SDAG-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GCN-SDAG-FAKE16-NEXT: global_store_b32 v[8:9], v0, off
; GCN-SDAG-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
@@ -61,9 +59,7 @@ define void @test_i8load_v4i8store(ptr addrspace(1) %ptr_a, ptr addrspace(1) %pt
; GCN-SDAG-REAL16-NEXT: v_perm_b32 v1, v10, v7, 0xc0c0004
; GCN-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GCN-SDAG-REAL16-NEXT: v_or_b16 v0.l, v6.l, v0.l
-; GCN-SDAG-REAL16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GCN-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GCN-SDAG-REAL16-NEXT: v_or_b32_e32 v0, v1, v0
+; GCN-SDAG-REAL16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GCN-SDAG-REAL16-NEXT: global_store_b32 v[8:9], v0, off
; GCN-SDAG-REAL16-NEXT: s_set_pc_i64 s[30:31]
%a = load i8, ptr addrspace(1) %ptr_a
diff --git a/llvm/test/CodeGen/AMDGPU/idot4u.ll b/llvm/test/CodeGen/AMDGPU/idot4u.ll
index 1735e5c8c4ca2..a92fba0c8b24b 100644
--- a/llvm/test/CodeGen/AMDGPU/idot4u.ll
+++ b/llvm/test/CodeGen/AMDGPU/idot4u.ll
@@ -2607,16 +2607,17 @@ define amdgpu_kernel void @udot4_acc8_vecMul(ptr addrspace(1) %src1,
; GFX9-NODL-NEXT: s_waitcnt vmcnt(1)
; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX9-NODL-NEXT: v_mul_lo_u16_sdwa v6, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
-; GFX9-NODL-NEXT: v_mul_lo_u16_e32 v7, v4, v5
-; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v8, 8, v6
-; GFX9-NODL-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NODL-NEXT: v_mul_lo_u16_sdwa v6, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PRESERVE src0_sel:BYTE_1 src1_sel:BYTE_1
+; GFX9-NODL-NEXT: v_mul_lo_u16_e32 v8, v4, v5
+; GFX9-NODL-NEXT: v_mul_lo_u16_sdwa v7, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
+; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v9, 8, v6
+; GFX9-NODL-NEXT: v_or_b32_sdwa v6, v8, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NODL-NEXT: v_lshl_or_b32 v6, v6, 16, v7
; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v6, 8, v6
; GFX9-NODL-NEXT: s_waitcnt vmcnt(0)
; GFX9-NODL-NEXT: v_mad_legacy_u16 v1, v1, v2, v3
; GFX9-NODL-NEXT: v_add_u16_e32 v1, v1, v6
; GFX9-NODL-NEXT: v_mad_legacy_u16 v1, v4, v5, v1
-; GFX9-NODL-NEXT: v_add_u16_e32 v1, v1, v8
+; GFX9-NODL-NEXT: v_add_u16_e32 v1, v1, v9
; GFX9-NODL-NEXT: global_store_byte v0, v1, s[6:7]
; GFX9-NODL-NEXT: s_endpgm
;
@@ -2635,16 +2636,17 @@ define amdgpu_kernel void @udot4_acc8_vecMul(ptr addrspace(1) %src1,
; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
; GFX9-DL-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v6, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
-; GFX9-DL-NEXT: v_mul_lo_u16_e32 v7, v4, v5
-; GFX9-DL-NEXT: v_lshrrev_b32_e32 v8, 8, v6
-; GFX9-DL-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v6, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PRESERVE src0_sel:BYTE_1 src1_sel:BYTE_1
+; GFX9-DL-NEXT: v_mul_lo_u16_e32 v8, v4, v5
+; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v7, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v9, 8, v6
+; GFX9-DL-NEXT: v_or_b32_sdwa v6, v8, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-DL-NEXT: v_lshl_or_b32 v6, v6, 16, v7
; GFX9-DL-NEXT: v_lshrrev_b32_e32 v6, 8, v6
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v1, v2, v3
; GFX9-DL-NEXT: v_add_u16_e32 v1, v1, v6
; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v4, v5, v1
-; GFX9-DL-NEXT: v_add_u16_e32 v1, v1, v8
+; GFX9-DL-NEXT: v_add_u16_e32 v1, v1, v9
; GFX9-DL-NEXT: global_store_byte v0, v1, s[6:7]
; GFX9-DL-NEXT: s_endpgm
;
@@ -2661,26 +2663,27 @@ define amdgpu_kernel void @udot4_acc8_vecMul(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0
; GFX10-DL-NEXT: global_load_ubyte v3, v0, s[6:7]
; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
-; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 24, v1
+; GFX10-DL-NEXT: v_lshrrev_b16 v4, 8, v1
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 24, v1
; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 24, v2
-; GFX10-DL-NEXT: v_lshrrev_b16 v6, 8, v1
-; GFX10-DL-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX10-DL-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX10-DL-NEXT: v_lshrrev_b16 v9, 8, v2
-; GFX10-DL-NEXT: v_mul_lo_u16 v4, v4, v5
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v6, 24, v2
+; GFX10-DL-NEXT: v_lshrrev_b16 v7, 8, v2
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v9, 16, v2
+; GFX10-DL-NEXT: v_mul_lo_u16 v5, v5, v6
+; GFX10-DL-NEXT: v_mul_lo_u16 v4, v4, v7
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_u16 v1, v1, v2, v3
-; GFX10-DL-NEXT: v_mul_lo_u16 v5, v7, v8
-; GFX10-DL-NEXT: v_mul_lo_u16 v6, v6, v9
+; GFX10-DL-NEXT: v_mul_lo_u16 v6, v8, v9
+; GFX10-DL-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX10-DL-NEXT: v_lshlrev_b16 v4, 8, v4
-; GFX10-DL-NEXT: v_lshlrev_b16 v6, 8, v6
-; GFX10-DL-NEXT: v_or_b32_sdwa v5, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 8, v4
-; GFX10-DL-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX10-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v5
-; GFX10-DL-NEXT: v_add_nc_u16 v1, v1, v5
-; GFX10-DL-NEXT: v_mad_u16 v1, v7, v8, v1
+; GFX10-DL-NEXT: v_or_b32_sdwa v6, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-DL-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v2, 8, v5
+; GFX10-DL-NEXT: v_lshl_or_b32 v4, v6, 16, v4
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v4, 8, v4
+; GFX10-DL-NEXT: v_add_nc_u16 v1, v1, v4
+; GFX10-DL-NEXT: v_mad_u16 v1, v8, v9, v1
; GFX10-DL-NEXT: v_add_nc_u16 v1, v1, v2
; GFX10-DL-NEXT: global_store_byte v0, v1, s[6:7]
; GFX10-DL-NEXT: s_endpgm
@@ -2739,35 +2742,34 @@ define amdgpu_kernel void @udot4_acc8_vecMul(ptr addrspace(1) %src1,
; GFX11-DL-FAKE16-NEXT: global_load_b32 v0, v0, s[2:3]
; GFX11-DL-FAKE16-NEXT: global_load_u8 v3, v2, s[4:5]
; GFX11-DL-FAKE16-NEXT: s_waitcnt vmcnt(2)
-; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 24, v1
+; GFX11-DL-FAKE16-NEXT: v_lshrrev_b16 v4, 8, v1
+; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 24, v1
; GFX11-DL-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 24, v0
-; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX11-DL-FAKE16-NEXT: v_lshrrev_b16 v8, 8, v1
+; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 24, v0
+; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v0
; GFX11-DL-FAKE16-NEXT: v_lshrrev_b16 v9, 8, v0
; GFX11-DL-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-DL-FAKE16-NEXT: v_mad_u16 v0, v1, v0, v3
-; GFX11-DL-FAKE16-NEXT: v_mul_lo_u16 v5, v5, v6
-; GFX11-DL-FAKE16-NEXT: v_mul_lo_u16 v6, v4, v7
-; GFX11-DL-FAKE16-NEXT: v_mul_lo_u16 v8, v8, v9
+; GFX11-DL-FAKE16-NEXT: v_mul_lo_u16 v6, v6, v7
+; GFX11-DL-FAKE16-NEXT: v_mul_lo_u16 v7, v5, v8
+; GFX11-DL-FAKE16-NEXT: v_mul_lo_u16 v4, v4, v9
; GFX11-DL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-DL-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
-; GFX11-DL-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-DL-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v6
+; GFX11-DL-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
; GFX11-DL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-DL-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v8
-; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v5
+; GFX11-DL-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v4
+; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v6
; GFX11-DL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-DL-FAKE16-NEXT: v_or_b32_e32 v6, v6, v5
-; GFX11-DL-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-DL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-DL-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-DL-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
+; GFX11-DL-FAKE16-NEXT: v_or_b32_e32 v7, v7, v6
+; GFX11-DL-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-DL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 8, v6
-; GFX11-DL-FAKE16-NEXT: v_add_nc_u16 v0, v0, v6
+; GFX11-DL-FAKE16-NEXT: v_lshl_or_b32 v4, v7, 16, v4
+; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 8, v4
; GFX11-DL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-DL-FAKE16-NEXT: v_mad_u16 v0, v4, v7, v0
+; GFX11-DL-FAKE16-NEXT: v_add_nc_u16 v0, v0, v4
+; GFX11-DL-FAKE16-NEXT: v_mad_u16 v0, v5, v8, v0
+; GFX11-DL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-DL-FAKE16-NEXT: v_add_nc_u16 v0, v0, v1
; GFX11-DL-FAKE16-NEXT: global_store_b8 v2, v0, s[4:5]
; GFX11-DL-FAKE16-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/idot8s.ll b/llvm/test/CodeGen/AMDGPU/idot8s.ll
index 330f187ac42de..51de68f60cd17 100644
--- a/llvm/test/CodeGen/AMDGPU/idot8s.ll
+++ b/llvm/test/CodeGen/AMDGPU/idot8s.ll
@@ -2710,76 +2710,77 @@ define amdgpu_kernel void @idot8_acc8_vecMul(ptr addrspace(1) %src1,
; GFX9-NEXT: global_load_ubyte v3, v0, s[0:1]
; GFX9-NEXT: s_addc_u32 s13, s13, 0
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_lshrrev_b32_e32 v5, 20, v1
-; GFX9-NEXT: v_lshrrev_b32_e32 v6, 28, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v5, 28, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v6, 20, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 12, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v8, 8, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 4, v1
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_lshrrev_b32_e32 v10, 20, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v11, 28, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v10, 28, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 20, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v12, 12, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 8, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 4, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v15, 12, v1
-; GFX9-NEXT: v_lshlrev_b16_sdwa v16, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-; GFX9-NEXT: v_lshlrev_b16_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_lshlrev_b16_sdwa v16, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_lshlrev_b16_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
; GFX9-NEXT: v_lshlrev_b16_e32 v17, 12, v2
-; GFX9-NEXT: v_lshlrev_b16_sdwa v18, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-; GFX9-NEXT: v_lshlrev_b16_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_lshlrev_b16_sdwa v18, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_lshlrev_b16_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 12, v9
; GFX9-NEXT: v_ashrrev_i16_e32 v9, 12, v15
-; GFX9-NEXT: v_lshlrev_b16_e32 v8, 12, v8
-; GFX9-NEXT: v_lshlrev_b16_e32 v7, 12, v7
; GFX9-NEXT: v_ashrrev_i16_e32 v15, 12, v16
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 12, v6
; GFX9-NEXT: v_ashrrev_i16_e32 v16, 12, v1
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 12, v5
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 12, v14
; GFX9-NEXT: v_ashrrev_i16_e32 v14, 12, v17
-; GFX9-NEXT: v_lshlrev_b16_e32 v13, 12, v13
-; GFX9-NEXT: v_lshlrev_b16_e32 v12, 12, v12
; GFX9-NEXT: v_ashrrev_i16_e32 v17, 12, v18
; GFX9-NEXT: v_lshlrev_b16_e32 v11, 12, v11
; GFX9-NEXT: v_ashrrev_i16_e32 v18, 12, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 12, v10
-; GFX9-NEXT: v_ashrrev_i16_e32 v8, 12, v8
-; GFX9-NEXT: v_ashrrev_i16_e32 v7, 12, v7
+; GFX9-NEXT: v_lshlrev_b16_e32 v8, 12, v8
+; GFX9-NEXT: v_lshlrev_b16_e32 v7, 12, v7
+; GFX9-NEXT: v_lshlrev_b16_e32 v13, 12, v13
+; GFX9-NEXT: v_lshlrev_b16_e32 v12, 12, v12
; GFX9-NEXT: v_ashrrev_i16_e32 v6, 12, v6
; GFX9-NEXT: v_ashrrev_i16_e32 v1, 12, v1
-; GFX9-NEXT: v_ashrrev_i16_e32 v10, 12, v13
-; GFX9-NEXT: v_ashrrev_i16_e32 v12, 12, v12
; GFX9-NEXT: v_ashrrev_i16_e32 v11, 12, v11
; GFX9-NEXT: v_ashrrev_i16_e32 v2, 12, v2
-; GFX9-NEXT: v_ashrrev_i16_e32 v4, 12, v4
-; GFX9-NEXT: v_ashrrev_i16_e32 v5, 12, v5
-; GFX9-NEXT: v_mul_lo_u16_e32 v13, v16, v18
+; GFX9-NEXT: v_ashrrev_i16_e32 v8, 12, v8
+; GFX9-NEXT: v_ashrrev_i16_e32 v7, 12, v7
+; GFX9-NEXT: v_ashrrev_i16_e32 v10, 12, v13
+; GFX9-NEXT: v_ashrrev_i16_e32 v12, 12, v12
; GFX9-NEXT: v_mul_lo_u16_e32 v19, v15, v17
; GFX9-NEXT: v_mul_lo_u16_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_mul_lo_u16_sdwa v2, v6, v11 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_ashrrev_i16_e32 v4, 12, v4
+; GFX9-NEXT: v_ashrrev_i16_e32 v5, 12, v5
+; GFX9-NEXT: v_mul_lo_u16_e32 v13, v16, v18
; GFX9-NEXT: v_mul_lo_u16_sdwa v6, v7, v12 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_mul_lo_u16_e32 v7, v8, v10
+; GFX9-NEXT: v_or_b32_sdwa v2, v19, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_mul_lo_u16_e32 v9, v9, v14
; GFX9-NEXT: v_mul_lo_u16_sdwa v4, v4, v5 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v1, v13, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v5, v19, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v5, v13, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_mul_lo_u16_e32 v9, v9, v14
-; GFX9-NEXT: v_lshrrev_b32_e32 v8, 8, v2
-; GFX9-NEXT: v_or_b32_sdwa v2, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX9-NEXT: v_or_b32_sdwa v7, v9, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v2
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v1
-; GFX9-NEXT: v_lshrrev_b64 v[1:2], 24, v[1:2]
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 8, v4
+; GFX9-NEXT: v_lshrrev_b32_e32 v8, 8, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; GFX9-NEXT: v_lshl_or_b32 v4, v6, 16, v4
+; GFX9-NEXT: v_lshl_or_b32 v2, v5, 16, v2
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v3, v7, v3
-; GFX9-NEXT: v_add_u16_e32 v2, v3, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v4, 8, v4
+; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v2
+; GFX9-NEXT: v_lshrrev_b64 v[1:2], 24, v[1:2]
+; GFX9-NEXT: v_add_u16_e32 v2, v3, v4
; GFX9-NEXT: v_add_u16_e32 v2, v2, v6
; GFX9-NEXT: v_add_u16_e32 v1, v2, v1
-; GFX9-NEXT: v_mad_legacy_u16 v1, v16, v18, v1
-; GFX9-NEXT: v_add_u16_e32 v1, v1, v5
; GFX9-NEXT: v_mad_legacy_u16 v1, v15, v17, v1
+; GFX9-NEXT: v_add_u16_e32 v1, v1, v5
+; GFX9-NEXT: v_mad_legacy_u16 v1, v16, v18, v1
; GFX9-NEXT: v_add_u16_e32 v1, v1, v8
; GFX9-NEXT: global_store_byte v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
@@ -2802,76 +2803,77 @@ define amdgpu_kernel void @idot8_acc8_vecMul(ptr addrspace(1) %src1,
; GFX9-DL-NEXT: global_load_ubyte v3, v0, s[0:1]
; GFX9-DL-NEXT: s_addc_u32 s13, s13, 0
; GFX9-DL-NEXT: s_waitcnt vmcnt(2)
-; GFX9-DL-NEXT: v_lshrrev_b32_e32 v5, 20, v1
-; GFX9-DL-NEXT: v_lshrrev_b32_e32 v6, 28, v1
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v5, 28, v1
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v6, 20, v1
; GFX9-DL-NEXT: v_lshrrev_b32_e32 v7, 12, v1
; GFX9-DL-NEXT: v_lshrrev_b32_e32 v8, 8, v1
; GFX9-DL-NEXT: v_lshrrev_b32_e32 v9, 4, v1
; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX9-DL-NEXT: v_lshrrev_b32_e32 v10, 20, v2
-; GFX9-DL-NEXT: v_lshrrev_b32_e32 v11, 28, v2
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v10, 28, v2
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v11, 20, v2
; GFX9-DL-NEXT: v_lshrrev_b32_e32 v12, 12, v2
; GFX9-DL-NEXT: v_lshrrev_b32_e32 v13, 8, v2
; GFX9-DL-NEXT: v_lshrrev_b32_e32 v14, 4, v2
; GFX9-DL-NEXT: v_lshlrev_b16_e32 v15, 12, v1
-; GFX9-DL-NEXT: v_lshlrev_b16_sdwa v16, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-; GFX9-DL-NEXT: v_lshlrev_b16_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-DL-NEXT: v_lshlrev_b16_sdwa v16, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-DL-NEXT: v_lshlrev_b16_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
; GFX9-DL-NEXT: v_lshlrev_b16_e32 v17, 12, v2
-; GFX9-DL-NEXT: v_lshlrev_b16_sdwa v18, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-; GFX9-DL-NEXT: v_lshlrev_b16_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-DL-NEXT: v_lshlrev_b16_sdwa v18, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-DL-NEXT: v_lshlrev_b16_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
; GFX9-DL-NEXT: v_lshlrev_b16_e32 v4, 12, v9
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v9, 12, v15
-; GFX9-DL-NEXT: v_lshlrev_b16_e32 v8, 12, v8
-; GFX9-DL-NEXT: v_lshlrev_b16_e32 v7, 12, v7
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v15, 12, v16
; GFX9-DL-NEXT: v_lshlrev_b16_e32 v6, 12, v6
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v16, 12, v1
; GFX9-DL-NEXT: v_lshlrev_b16_e32 v1, 12, v5
; GFX9-DL-NEXT: v_lshlrev_b16_e32 v5, 12, v14
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v14, 12, v17
-; GFX9-DL-NEXT: v_lshlrev_b16_e32 v13, 12, v13
-; GFX9-DL-NEXT: v_lshlrev_b16_e32 v12, 12, v12
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v17, 12, v18
; GFX9-DL-NEXT: v_lshlrev_b16_e32 v11, 12, v11
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v18, 12, v2
; GFX9-DL-NEXT: v_lshlrev_b16_e32 v2, 12, v10
-; GFX9-DL-NEXT: v_ashrrev_i16_e32 v8, 12, v8
-; GFX9-DL-NEXT: v_ashrrev_i16_e32 v7, 12, v7
+; GFX9-DL-NEXT: v_lshlrev_b16_e32 v8, 12, v8
+; GFX9-DL-NEXT: v_lshlrev_b16_e32 v7, 12, v7
+; GFX9-DL-NEXT: v_lshlrev_b16_e32 v13, 12, v13
+; GFX9-DL-NEXT: v_lshlrev_b16_e32 v12, 12, v12
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v6, 12, v6
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v1, 12, v1
-; GFX9-DL-NEXT: v_ashrrev_i16_e32 v10, 12, v13
-; GFX9-DL-NEXT: v_ashrrev_i16_e32 v12, 12, v12
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v11, 12, v11
; GFX9-DL-NEXT: v_ashrrev_i16_e32 v2, 12, v2
-; GFX9-DL-NEXT: v_ashrrev_i16_e32 v4, 12, v4
-; GFX9-DL-NEXT: v_ashrrev_i16_e32 v5, 12, v5
-; GFX9-DL-NEXT: v_mul_lo_u16_e32 v13, v16, v18
+; GFX9-DL-NEXT: v_ashrrev_i16_e32 v8, 12, v8
+; GFX9-DL-NEXT: v_ashrrev_i16_e32 v7, 12, v7
+; GFX9-DL-NEXT: v_ashrrev_i16_e32 v10, 12, v13
+; GFX9-DL-NEXT: v_ashrrev_i16_e32 v12, 12, v12
; GFX9-DL-NEXT: v_mul_lo_u16_e32 v19, v15, v17
; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v2, v6, v11 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-DL-NEXT: v_ashrrev_i16_e32 v4, 12, v4
+; GFX9-DL-NEXT: v_ashrrev_i16_e32 v5, 12, v5
+; GFX9-DL-NEXT: v_mul_lo_u16_e32 v13, v16, v18
; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v6, v7, v12 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-DL-NEXT: v_mul_lo_u16_e32 v7, v8, v10
+; GFX9-DL-NEXT: v_or_b32_sdwa v2, v19, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-DL-NEXT: v_mul_lo_u16_e32 v9, v9, v14
; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v4, v4, v5 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-DL-NEXT: v_or_b32_sdwa v1, v13, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-DL-NEXT: v_or_b32_sdwa v5, v19, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-DL-NEXT: v_or_b32_sdwa v5, v13, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-DL-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-DL-NEXT: v_mul_lo_u16_e32 v9, v9, v14
-; GFX9-DL-NEXT: v_lshrrev_b32_e32 v8, 8, v2
-; GFX9-DL-NEXT: v_or_b32_sdwa v2, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-DL-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; GFX9-DL-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX9-DL-NEXT: v_or_b32_sdwa v7, v9, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v2
-; GFX9-DL-NEXT: v_or_b32_e32 v4, v4, v1
-; GFX9-DL-NEXT: v_lshrrev_b64 v[1:2], 24, v[1:2]
-; GFX9-DL-NEXT: v_lshrrev_b32_e32 v2, 8, v4
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v8, 8, v1
+; GFX9-DL-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; GFX9-DL-NEXT: v_lshl_or_b32 v4, v6, 16, v4
+; GFX9-DL-NEXT: v_lshl_or_b32 v2, v5, 16, v2
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
; GFX9-DL-NEXT: v_add_u16_e32 v3, v7, v3
-; GFX9-DL-NEXT: v_add_u16_e32 v2, v3, v2
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v4, 8, v4
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v2
+; GFX9-DL-NEXT: v_lshrrev_b64 v[1:2], 24, v[1:2]
+; GFX9-DL-NEXT: v_add_u16_e32 v2, v3, v4
; GFX9-DL-NEXT: v_add_u16_e32 v2, v2, v6
; GFX9-DL-NEXT: v_add_u16_e32 v1, v2, v1
-; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v16, v18, v1
-; GFX9-DL-NEXT: v_add_u16_e32 v1, v1, v5
; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v15, v17, v1
+; GFX9-DL-NEXT: v_add_u16_e32 v1, v1, v5
+; GFX9-DL-NEXT: v_mad_legacy_u16 v1, v16, v18, v1
; GFX9-DL-NEXT: v_add_u16_e32 v1, v1, v8
; GFX9-DL-NEXT: global_store_byte v0, v1, s[0:1]
; GFX9-DL-NEXT: s_endpgm
@@ -2893,87 +2895,89 @@ define amdgpu_kernel void @idot8_acc8_vecMul(ptr addrspace(1) %src1,
; GFX10-DL-XNACK-NEXT: s_clause 0x1
; GFX10-DL-XNACK-NEXT: global_load_dword v1, v0, s[8:9]
; GFX10-DL-XNACK-NEXT: global_load_dword v2, v0, s[10:11]
-; GFX10-DL-XNACK-NEXT: global_load_ubyte v3, v4, s[0:1]
+; GFX10-DL-XNACK-NEXT: global_load_ubyte v0, v4, s[0:1]
; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v8, 12, v1
+; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v10, 4, v1
; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v15, 12, v2
+; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v17, 4, v2
+; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v6, 20, v1
+; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v13, 20, v2
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v9, 8, v1
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v16, 8, v2
-; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v10, 4, v1
+; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v10, 12, v10
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v8, 12, v8
+; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v17, 12, v17
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v15, 12, v15
-; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v17, 4, v2
+; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v3, 28, v1
+; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v11, 28, v2
+; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v14, 16, v2
+; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v6, 12, v6
+; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v13, 12, v13
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v9, 12, v9
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v16, 12, v16
+; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v10, 12, v10
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v8, 12, v8
+; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v17, 12, v17
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v15, 12, v15
-; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v0, 20, v1
-; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v6, 28, v1
-; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v11, 20, v2
-; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v13, 28, v2
-; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v10, 12, v10
-; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v17, 12, v17
+; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v5, 24, v1
+; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v12, 24, v2
+; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v7, 12, v7
+; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v3, 12, v3
+; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v14, 12, v14
+; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v11, 12, v11
+; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v6, 12, v6
+; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v13, 12, v13
+; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v1, 12, v1
+; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v2, 12, v2
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v9, 12, v9
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v16, 12, v16
; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v8, v8, v15
-; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v7, 24, v1
-; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v12, 16, v2
-; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v14, 24, v2
-; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v1, 12, v1
-; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v2, 12, v2
-; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v6, 12, v6
-; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v0, 12, v0
-; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v13, 12, v13
-; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v11, 12, v11
-; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v10, 12, v10
-; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v15, 12, v17
-; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v9, v9, v16
-; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v8, 8, v8
-; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v1, 12, v1
-; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v7, 12, v7
+; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v10, v10, v17
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v5, 12, v5
-; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v2, 12, v2
-; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v14, 12, v14
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v12, 12, v12
-; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v6, 12, v6
-; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v0, 12, v0
-; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v13, 12, v13
-; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v11, 12, v11
-; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v10, v10, v15
-; GFX10-DL-XNACK-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v7, 12, v7
-; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v5, 12, v5
+; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v3, 12, v3
; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v14, 12, v14
-; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v12, 12, v12
-; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v1, v1, v2
-; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v2, v0, v11
+; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v11, 12, v11
; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v6, v6, v13
-; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v9, 8, v10
-; GFX10-DL-XNACK-NEXT: v_lshlrev_b32_e32 v0, 16, v8
-; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v10, v5, v12
+; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v1, 12, v1
+; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v2, 12, v2
+; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v9, v9, v16
+; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v8, 8, v8
+; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v10, 8, v10
+; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v5, 12, v5
+; GFX10-DL-XNACK-NEXT: v_ashrrev_i16 v12, 12, v12
+; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v3, v3, v11
; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v11, v7, v14
-; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v2, 8, v2
; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v6, 8, v6
-; GFX10-DL-XNACK-NEXT: v_or_b32_sdwa v13, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX10-DL-XNACK-NEXT: v_or_b32_sdwa v1, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-DL-XNACK-NEXT: v_or_b32_sdwa v2, v10, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-DL-XNACK-NEXT: v_or_b32_sdwa v9, v11, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v10, 8, v13
+; GFX10-DL-XNACK-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-DL-XNACK-NEXT: v_and_b32_e32 v9, 0xffff, v10
+; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v1, v1, v2
+; GFX10-DL-XNACK-NEXT: v_mul_lo_u16 v2, v5, v12
+; GFX10-DL-XNACK-NEXT: v_lshlrev_b16 v13, 8, v3
+; GFX10-DL-XNACK-NEXT: v_or_b32_sdwa v3, v11, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-DL-XNACK-NEXT: v_lshl_or_b32 v6, v8, 16, v9
+; GFX10-DL-XNACK-NEXT: v_or_b32_sdwa v1, v1, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-DL-XNACK-NEXT: v_or_b32_sdwa v2, v2, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-DL-XNACK-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v6, 8, v6
; GFX10-DL-XNACK-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v3, v1, v3
-; GFX10-DL-XNACK-NEXT: v_or_b32_sdwa v1, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v9, v3, v10
+; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v9, v1, v0
+; GFX10-DL-XNACK-NEXT: v_lshlrev_b32_e32 v0, 16, v8
+; GFX10-DL-XNACK-NEXT: v_lshl_or_b32 v1, v2, 16, v3
+; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v6, v9, v6
; GFX10-DL-XNACK-NEXT: v_lshrrev_b64 v[2:3], 24, v[0:1]
; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v1, 8, v1
-; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v0, v9, v8
+; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v0, v6, v8
; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v0, v0, v2
-; GFX10-DL-XNACK-NEXT: v_mad_u16 v0, v5, v12, v0
-; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v0, v0, v1
-; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v1, 8, v6
; GFX10-DL-XNACK-NEXT: v_mad_u16 v0, v7, v14, v0
; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v0, v0, v1
+; GFX10-DL-XNACK-NEXT: v_lshrrev_b32_e32 v1, 8, v13
+; GFX10-DL-XNACK-NEXT: v_mad_u16 v0, v5, v12, v0
+; GFX10-DL-XNACK-NEXT: v_add_nc_u16 v0, v0, v1
; GFX10-DL-XNACK-NEXT: global_store_byte v4, v0, s[0:1]
; GFX10-DL-XNACK-NEXT: s_endpgm
;
@@ -2997,84 +3001,86 @@ define amdgpu_kernel void @idot8_acc8_vecMul(ptr addrspace(1) %src1,
; GFX10-DL-NOXNACK-NEXT: global_load_ubyte v2, v4, s[0:1]
; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(2)
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v8, 12, v1
+; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v10, 4, v1
; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(1)
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v15, 12, v0
+; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v17, 4, v0
+; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v6, 20, v1
+; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v13, 20, v0
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v9, 8, v1
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v16, 8, v0
-; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v10, 4, v1
+; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v10, 12, v10
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v8, 12, v8
+; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v17, 12, v17
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v15, 12, v15
-; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v17, 4, v0
+; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v3, 28, v1
+; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v11, 28, v0
+; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v14, 16, v0
+; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v6, 12, v6
+; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v13, 12, v13
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v9, 12, v9
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v16, 12, v16
+; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v10, 12, v10
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v8, 12, v8
+; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v17, 12, v17
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v15, 12, v15
-; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v3, 20, v1
-; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v6, 28, v1
-; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v11, 20, v0
-; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v13, 28, v0
-; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v10, 12, v10
-; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v17, 12, v17
-; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v9, 12, v9
-; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v16, 12, v16
-; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v8, v8, v15
-; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v7, 24, v1
-; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v12, 16, v0
-; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v14, 24, v0
-; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v6, 12, v6
+; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v5, 24, v1
+; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v12, 24, v0
+; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v7, 12, v7
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v3, 12, v3
-; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v13, 12, v13
+; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v14, 12, v14
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v11, 12, v11
+; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v6, 12, v6
+; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v13, 12, v13
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v1, 12, v1
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v0, 12, v0
-; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v10, 12, v10
-; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v15, 12, v17
-; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v9, v9, v16
-; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v8, 8, v8
-; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v7, 12, v7
+; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v9, 12, v9
+; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v16, 12, v16
+; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v8, v8, v15
+; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v10, v10, v17
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v5, 12, v5
-; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v14, 12, v14
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v12, 12, v12
-; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v6, 12, v6
+; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v7, 12, v7
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v3, 12, v3
-; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v13, 12, v13
+; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v14, 12, v14
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v11, 12, v11
+; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v6, v6, v13
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v1, 12, v1
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v0, 12, v0
-; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v10, v10, v15
-; GFX10-DL-NOXNACK-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v7, 12, v7
+; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v9, v9, v16
+; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v8, 8, v8
+; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v10, 8, v10
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v5, 12, v5
-; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v14, 12, v14
; GFX10-DL-NOXNACK-NEXT: v_ashrrev_i16 v12, 12, v12
; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v3, v3, v11
-; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v6, v6, v13
-; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v1, v1, v0
-; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v9, 8, v10
-; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b32_e32 v0, 16, v8
-; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v10, v5, v12
; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v11, v7, v14
-; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v6, 8, v6
-; GFX10-DL-NOXNACK-NEXT: v_or_b32_sdwa v13, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX10-DL-NOXNACK-NEXT: v_or_b32_sdwa v1, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-DL-NOXNACK-NEXT: v_or_b32_sdwa v3, v10, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-DL-NOXNACK-NEXT: v_or_b32_sdwa v9, v11, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v10, 8, v13
+; GFX10-DL-NOXNACK-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-DL-NOXNACK-NEXT: v_and_b32_e32 v9, 0xffff, v10
+; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v0, v1, v0
+; GFX10-DL-NOXNACK-NEXT: v_mul_lo_u16 v1, v5, v12
+; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b16 v13, 8, v3
+; GFX10-DL-NOXNACK-NEXT: v_or_b32_sdwa v3, v11, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-DL-NOXNACK-NEXT: v_lshl_or_b32 v6, v8, 16, v9
+; GFX10-DL-NOXNACK-NEXT: v_or_b32_sdwa v0, v0, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-DL-NOXNACK-NEXT: v_or_b32_sdwa v1, v1, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-DL-NOXNACK-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v6, 8, v6
; GFX10-DL-NOXNACK-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v2, v1, v2
-; GFX10-DL-NOXNACK-NEXT: v_or_b32_sdwa v1, v3, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v9, v2, v10
+; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v2, v0, v2
+; GFX10-DL-NOXNACK-NEXT: v_lshlrev_b32_e32 v0, 16, v8
+; GFX10-DL-NOXNACK-NEXT: v_lshl_or_b32 v1, v1, 16, v3
+; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v6, v2, v6
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b64 v[2:3], 24, v[0:1]
; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v1, 8, v1
-; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v0, v9, v8
+; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v0, v6, v8
; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v0, v0, v2
-; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v5, v12, v0
-; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v0, v0, v1
-; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v1, 8, v6
; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v7, v14, v0
; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v0, v0, v1
+; GFX10-DL-NOXNACK-NEXT: v_lshrrev_b32_e32 v1, 8, v13
+; GFX10-DL-NOXNACK-NEXT: v_mad_u16 v0, v5, v12, v0
+; GFX10-DL-NOXNACK-NEXT: v_add_nc_u16 v0, v0, v1
; GFX10-DL-NOXNACK-NEXT: global_store_byte v4, v0, s[0:1]
; GFX10-DL-NOXNACK-NEXT: s_endpgm
ptr addrspace(1) %src2,
diff --git a/llvm/test/CodeGen/AMDGPU/idot8u.ll b/llvm/test/CodeGen/AMDGPU/idot8u.ll
index 231520d148884..5c9494662111b 100644
--- a/llvm/test/CodeGen/AMDGPU/idot8u.ll
+++ b/llvm/test/CodeGen/AMDGPU/idot8u.ll
@@ -2538,132 +2538,134 @@ define amdgpu_kernel void @udot8_acc8_vecMul(ptr addrspace(1) %src1,
;
; GFX9-LABEL: udot8_acc8_vecMul:
; GFX9: ; %bb.0: ; %entry
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-NEXT: v_mov_b32_e32 v3, 0
; GFX9-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: global_load_dword v1, v0, s[0:1]
-; GFX9-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX9-NEXT: global_load_ubyte v4, v3, s[6:7]
; GFX9-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
; GFX9-NEXT: s_mov_b32 s14, -1
; GFX9-NEXT: s_mov_b32 s15, 0xe00000
; GFX9-NEXT: s_add_u32 s12, s12, s11
+; GFX9-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x34
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX9-NEXT: v_mov_b32_e32 v3, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: global_load_dword v1, v0, s[8:9]
+; GFX9-NEXT: global_load_dword v2, v0, s[10:11]
+; GFX9-NEXT: global_load_ubyte v4, v3, s[0:1]
; GFX9-NEXT: s_addc_u32 s13, s13, 0
; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: v_bfe_u32 v8, v1, 20, 4
+; GFX9-NEXT: v_bfe_u32 v9, v1, 16, 4
+; GFX9-NEXT: v_lshrrev_b32_e32 v10, 28, v1
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_bfe_u32 v15, v2, 20, 4
+; GFX9-NEXT: v_bfe_u32 v16, v2, 16, 4
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 28, v2
; GFX9-NEXT: v_bfe_u32 v0, v1, 4, 4
; GFX9-NEXT: v_and_b32_e32 v5, 15, v1
; GFX9-NEXT: v_bfe_u32 v6, v1, 12, 4
; GFX9-NEXT: v_bfe_u32 v7, v1, 8, 4
-; GFX9-NEXT: v_lshrrev_b32_e32 v8, 28, v1
-; GFX9-NEXT: v_bfe_u32 v9, v1, 24, 4
-; GFX9-NEXT: v_bfe_u32 v10, v1, 20, 4
-; GFX9-NEXT: v_bfe_u32 v11, v1, 16, 4
-; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_bfe_u32 v11, v1, 24, 4
; GFX9-NEXT: v_bfe_u32 v1, v2, 4, 4
; GFX9-NEXT: v_and_b32_e32 v12, 15, v2
; GFX9-NEXT: v_bfe_u32 v13, v2, 12, 4
; GFX9-NEXT: v_bfe_u32 v14, v2, 8, 4
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 28, v2
-; GFX9-NEXT: v_bfe_u32 v16, v2, 24, 4
-; GFX9-NEXT: v_bfe_u32 v17, v2, 20, 4
-; GFX9-NEXT: v_bfe_u32 v2, v2, 16, 4
-; GFX9-NEXT: v_mul_lo_u16_e32 v18, v11, v2
+; GFX9-NEXT: v_bfe_u32 v2, v2, 24, 4
; GFX9-NEXT: v_mul_lo_u16_sdwa v10, v10, v17 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_mul_lo_u16_e32 v17, v9, v16
; GFX9-NEXT: v_mul_lo_u16_sdwa v8, v8, v15 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_mul_lo_u16_e32 v18, v11, v2
; GFX9-NEXT: v_mul_lo_u16_e32 v7, v7, v14
; GFX9-NEXT: v_mul_lo_u16_sdwa v6, v6, v13 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_mul_lo_u16_sdwa v1, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_e32 v0, v17, v8
; GFX9-NEXT: v_mul_lo_u16_e32 v5, v5, v12
-; GFX9-NEXT: v_mul_lo_u16_sdwa v12, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v18, v10
-; GFX9-NEXT: v_or_b32_sdwa v1, v17, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_e32 v12, v18, v10
; GFX9-NEXT: v_or_b32_e32 v6, v7, v6
-; GFX9-NEXT: v_or_b32_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v8, 0xffff, v0
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v7, 8, v10
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v12
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 8, v8
-; GFX9-NEXT: v_lshrrev_b32_e32 v8, 8, v1
-; GFX9-NEXT: v_or_b32_e32 v10, v12, v0
-; GFX9-NEXT: v_lshrrev_b64 v[0:1], 24, v[0:1]
-; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v10
+; GFX9-NEXT: v_lshl_or_b32 v10, v6, 16, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v12, 16, v8
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v4, v5, v4
-; GFX9-NEXT: v_add_u16_e32 v1, v4, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v10
+; GFX9-NEXT: v_lshrrev_b32_e32 v8, 8, v1
+; GFX9-NEXT: v_lshrrev_b64 v[0:1], 24, v[0:1]
+; GFX9-NEXT: v_add_u16_e32 v1, v4, v5
; GFX9-NEXT: v_add_u16_e32 v1, v1, v6
; GFX9-NEXT: v_add_u16_e32 v0, v1, v0
-; GFX9-NEXT: v_mad_legacy_u16 v0, v11, v2, v0
-; GFX9-NEXT: v_add_u16_e32 v0, v0, v8
; GFX9-NEXT: v_mad_legacy_u16 v0, v9, v16, v0
+; GFX9-NEXT: v_add_u16_e32 v0, v0, v8
+; GFX9-NEXT: v_mad_legacy_u16 v0, v11, v2, v0
; GFX9-NEXT: v_add_u16_e32 v0, v0, v7
-; GFX9-NEXT: global_store_byte v3, v0, s[6:7]
+; GFX9-NEXT: global_store_byte v3, v0, s[0:1]
; GFX9-NEXT: s_endpgm
;
; GFX9-DL-LABEL: udot8_acc8_vecMul:
; GFX9-DL: ; %bb.0: ; %entry
-; GFX9-DL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-DL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GFX9-DL-NEXT: v_mov_b32_e32 v3, 0
; GFX9-DL-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
-; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-DL-NEXT: global_load_dword v1, v0, s[0:1]
-; GFX9-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX9-DL-NEXT: global_load_ubyte v4, v3, s[6:7]
; GFX9-DL-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
; GFX9-DL-NEXT: s_mov_b32 s14, -1
; GFX9-DL-NEXT: s_mov_b32 s15, 0xe00000
; GFX9-DL-NEXT: s_add_u32 s12, s12, s11
+; GFX9-DL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24
+; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x34
+; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX9-DL-NEXT: v_mov_b32_e32 v3, 0
+; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-DL-NEXT: global_load_dword v1, v0, s[8:9]
+; GFX9-DL-NEXT: global_load_dword v2, v0, s[10:11]
+; GFX9-DL-NEXT: global_load_ubyte v4, v3, s[0:1]
; GFX9-DL-NEXT: s_addc_u32 s13, s13, 0
; GFX9-DL-NEXT: s_waitcnt vmcnt(2)
+; GFX9-DL-NEXT: v_bfe_u32 v8, v1, 20, 4
+; GFX9-DL-NEXT: v_bfe_u32 v9, v1, 16, 4
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v10, 28, v1
+; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
+; GFX9-DL-NEXT: v_bfe_u32 v15, v2, 20, 4
+; GFX9-DL-NEXT: v_bfe_u32 v16, v2, 16, 4
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v17, 28, v2
; GFX9-DL-NEXT: v_bfe_u32 v0, v1, 4, 4
; GFX9-DL-NEXT: v_and_b32_e32 v5, 15, v1
; GFX9-DL-NEXT: v_bfe_u32 v6, v1, 12, 4
; GFX9-DL-NEXT: v_bfe_u32 v7, v1, 8, 4
-; GFX9-DL-NEXT: v_lshrrev_b32_e32 v8, 28, v1
-; GFX9-DL-NEXT: v_bfe_u32 v9, v1, 24, 4
-; GFX9-DL-NEXT: v_bfe_u32 v10, v1, 20, 4
-; GFX9-DL-NEXT: v_bfe_u32 v11, v1, 16, 4
-; GFX9-DL-NEXT: s_waitcnt vmcnt(1)
+; GFX9-DL-NEXT: v_bfe_u32 v11, v1, 24, 4
; GFX9-DL-NEXT: v_bfe_u32 v1, v2, 4, 4
; GFX9-DL-NEXT: v_and_b32_e32 v12, 15, v2
; GFX9-DL-NEXT: v_bfe_u32 v13, v2, 12, 4
; GFX9-DL-NEXT: v_bfe_u32 v14, v2, 8, 4
-; GFX9-DL-NEXT: v_lshrrev_b32_e32 v15, 28, v2
-; GFX9-DL-NEXT: v_bfe_u32 v16, v2, 24, 4
-; GFX9-DL-NEXT: v_bfe_u32 v17, v2, 20, 4
-; GFX9-DL-NEXT: v_bfe_u32 v2, v2, 16, 4
-; GFX9-DL-NEXT: v_mul_lo_u16_e32 v18, v11, v2
+; GFX9-DL-NEXT: v_bfe_u32 v2, v2, 24, 4
; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v10, v10, v17 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-DL-NEXT: v_mul_lo_u16_e32 v17, v9, v16
; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v8, v8, v15 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-DL-NEXT: v_mul_lo_u16_e32 v18, v11, v2
; GFX9-DL-NEXT: v_mul_lo_u16_e32 v7, v7, v14
; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v6, v6, v13 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v1, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-DL-NEXT: v_or_b32_e32 v0, v17, v8
; GFX9-DL-NEXT: v_mul_lo_u16_e32 v5, v5, v12
-; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v12, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-DL-NEXT: v_or_b32_e32 v0, v18, v10
-; GFX9-DL-NEXT: v_or_b32_sdwa v1, v17, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-DL-NEXT: v_or_b32_e32 v12, v18, v10
; GFX9-DL-NEXT: v_or_b32_e32 v6, v7, v6
-; GFX9-DL-NEXT: v_or_b32_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-DL-NEXT: v_and_b32_e32 v8, 0xffff, v0
+; GFX9-DL-NEXT: v_or_b32_e32 v5, v5, v1
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v7, 8, v10
; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 16, v6
-; GFX9-DL-NEXT: v_or_b32_e32 v5, v5, v12
-; GFX9-DL-NEXT: v_lshrrev_b32_e32 v7, 8, v8
-; GFX9-DL-NEXT: v_lshrrev_b32_e32 v8, 8, v1
-; GFX9-DL-NEXT: v_or_b32_e32 v10, v12, v0
-; GFX9-DL-NEXT: v_lshrrev_b64 v[0:1], 24, v[0:1]
-; GFX9-DL-NEXT: v_lshrrev_b32_e32 v1, 8, v10
+; GFX9-DL-NEXT: v_lshl_or_b32 v10, v6, 16, v1
+; GFX9-DL-NEXT: v_lshl_or_b32 v1, v12, 16, v8
; GFX9-DL-NEXT: s_waitcnt vmcnt(0)
; GFX9-DL-NEXT: v_add_u16_e32 v4, v5, v4
-; GFX9-DL-NEXT: v_add_u16_e32 v1, v4, v1
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v10
+; GFX9-DL-NEXT: v_lshrrev_b32_e32 v8, 8, v1
+; GFX9-DL-NEXT: v_lshrrev_b64 v[0:1], 24, v[0:1]
+; GFX9-DL-NEXT: v_add_u16_e32 v1, v4, v5
; GFX9-DL-NEXT: v_add_u16_e32 v1, v1, v6
; GFX9-DL-NEXT: v_add_u16_e32 v0, v1, v0
-; GFX9-DL-NEXT: v_mad_legacy_u16 v0, v11, v2, v0
-; GFX9-DL-NEXT: v_add_u16_e32 v0, v0, v8
; GFX9-DL-NEXT: v_mad_legacy_u16 v0, v9, v16, v0
+; GFX9-DL-NEXT: v_add_u16_e32 v0, v0, v8
+; GFX9-DL-NEXT: v_mad_legacy_u16 v0, v11, v2, v0
; GFX9-DL-NEXT: v_add_u16_e32 v0, v0, v7
-; GFX9-DL-NEXT: global_store_byte v3, v0, s[6:7]
+; GFX9-DL-NEXT: global_store_byte v3, v0, s[0:1]
; GFX9-DL-NEXT: s_endpgm
;
; GFX10-DL-LABEL: udot8_acc8_vecMul:
@@ -2683,56 +2685,58 @@ define amdgpu_kernel void @udot8_acc8_vecMul(ptr addrspace(1) %src1,
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-DL-NEXT: global_load_dword v2, v0, s[2:3]
-; GFX10-DL-NEXT: global_load_ubyte v3, v4, s[6:7]
+; GFX10-DL-NEXT: global_load_ubyte v0, v4, s[6:7]
; GFX10-DL-NEXT: s_waitcnt vmcnt(2)
-; GFX10-DL-NEXT: v_bfe_u32 v6, v1, 12, 4
-; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT: v_bfe_u32 v9, v2, 12, 4
-; GFX10-DL-NEXT: v_bfe_u32 v0, v1, 4, 4
+; GFX10-DL-NEXT: v_bfe_u32 v3, v1, 4, 4
; GFX10-DL-NEXT: v_and_b32_e32 v5, 15, v1
+; GFX10-DL-NEXT: v_bfe_u32 v6, v1, 12, 4
; GFX10-DL-NEXT: v_bfe_u32 v7, v1, 8, 4
-; GFX10-DL-NEXT: v_lshrrev_b32_e32 v8, 28, v1
-; GFX10-DL-NEXT: v_bfe_u32 v10, v1, 24, 4
-; GFX10-DL-NEXT: v_bfe_u32 v11, v1, 20, 4
-; GFX10-DL-NEXT: v_bfe_u32 v12, v1, 16, 4
-; GFX10-DL-NEXT: v_bfe_u32 v1, v2, 8, 4
-; GFX10-DL-NEXT: v_mul_lo_u16 v6, v6, v9
-; GFX10-DL-NEXT: v_bfe_u32 v9, v2, 4, 4
-; GFX10-DL-NEXT: v_lshrrev_b32_e32 v14, 28, v2
+; GFX10-DL-NEXT: v_bfe_u32 v8, v1, 20, 4
+; GFX10-DL-NEXT: v_bfe_u32 v9, v1, 16, 4
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v10, 28, v1
+; GFX10-DL-NEXT: v_bfe_u32 v11, v1, 24, 4
+; GFX10-DL-NEXT: s_waitcnt vmcnt(1)
+; GFX10-DL-NEXT: v_bfe_u32 v1, v2, 4, 4
+; GFX10-DL-NEXT: v_bfe_u32 v13, v2, 12, 4
; GFX10-DL-NEXT: v_bfe_u32 v15, v2, 20, 4
-; GFX10-DL-NEXT: v_mul_lo_u16 v1, v7, v1
+; GFX10-DL-NEXT: v_bfe_u32 v14, v2, 8, 4
+; GFX10-DL-NEXT: v_and_b32_e32 v12, 15, v2
+; GFX10-DL-NEXT: v_mul_lo_u16 v1, v3, v1
+; GFX10-DL-NEXT: v_mul_lo_u16 v6, v6, v13
+; GFX10-DL-NEXT: v_bfe_u32 v16, v2, 16, 4
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v17, 28, v2
+; GFX10-DL-NEXT: v_bfe_u32 v13, v2, 24, 4
+; GFX10-DL-NEXT: v_mul_lo_u16 v2, v8, v15
+; GFX10-DL-NEXT: v_mul_lo_u16 v3, v7, v14
; GFX10-DL-NEXT: v_lshlrev_b16 v6, 8, v6
-; GFX10-DL-NEXT: v_and_b32_e32 v13, 15, v2
-; GFX10-DL-NEXT: v_mul_lo_u16 v0, v0, v9
-; GFX10-DL-NEXT: v_bfe_u32 v7, v2, 16, 4
-; GFX10-DL-NEXT: v_bfe_u32 v16, v2, 24, 4
-; GFX10-DL-NEXT: v_or_b32_e32 v6, v1, v6
-; GFX10-DL-NEXT: v_mul_lo_u16 v2, v11, v15
-; GFX10-DL-NEXT: v_mul_lo_u16 v8, v8, v14
-; GFX10-DL-NEXT: v_lshlrev_b16 v9, 8, v0
-; GFX10-DL-NEXT: v_mul_lo_u16 v5, v5, v13
-; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 16, v6
-; GFX10-DL-NEXT: v_mul_lo_u16 v1, v12, v7
-; GFX10-DL-NEXT: v_mul_lo_u16 v11, v10, v16
+; GFX10-DL-NEXT: v_lshlrev_b16 v1, 8, v1
+; GFX10-DL-NEXT: v_mul_lo_u16 v7, v10, v17
+; GFX10-DL-NEXT: v_mul_lo_u16 v8, v9, v16
; GFX10-DL-NEXT: v_lshlrev_b16 v2, 8, v2
-; GFX10-DL-NEXT: v_lshlrev_b16 v8, 8, v8
-; GFX10-DL-NEXT: v_or_b32_sdwa v13, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX10-DL-NEXT: v_or_b32_e32 v5, v5, v9
-; GFX10-DL-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX10-DL-NEXT: v_or_b32_sdwa v2, v11, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-DL-NEXT: v_lshrrev_b32_e32 v9, 8, v13
+; GFX10-DL-NEXT: v_or_b32_e32 v6, v3, v6
+; GFX10-DL-NEXT: v_and_b32_e32 v3, 0xffff, v1
+; GFX10-DL-NEXT: v_mul_lo_u16 v5, v5, v12
+; GFX10-DL-NEXT: v_mul_lo_u16 v10, v11, v13
+; GFX10-DL-NEXT: v_lshlrev_b16 v7, 8, v7
+; GFX10-DL-NEXT: v_or_b32_e32 v2, v8, v2
+; GFX10-DL-NEXT: v_lshl_or_b32 v3, v6, 16, v3
+; GFX10-DL-NEXT: v_or_b32_e32 v1, v5, v1
+; GFX10-DL-NEXT: v_or_b32_e32 v5, v10, v7
+; GFX10-DL-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v3, 8, v3
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT: v_add_nc_u16 v3, v5, v3
-; GFX10-DL-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX10-DL-NEXT: v_add_nc_u16 v5, v3, v9
+; GFX10-DL-NEXT: v_add_nc_u16 v8, v1, v0
+; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 16, v6
+; GFX10-DL-NEXT: v_lshl_or_b32 v1, v5, 16, v2
+; GFX10-DL-NEXT: v_add_nc_u16 v5, v8, v3
; GFX10-DL-NEXT: v_lshrrev_b64 v[2:3], 24, v[0:1]
; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX10-DL-NEXT: v_add_nc_u16 v0, v5, v6
; GFX10-DL-NEXT: v_add_nc_u16 v0, v0, v2
-; GFX10-DL-NEXT: v_mad_u16 v0, v12, v7, v0
+; GFX10-DL-NEXT: v_mad_u16 v0, v9, v16, v0
; GFX10-DL-NEXT: v_add_nc_u16 v0, v0, v1
-; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 8, v8
-; GFX10-DL-NEXT: v_mad_u16 v0, v10, v16, v0
+; GFX10-DL-NEXT: v_lshrrev_b32_e32 v1, 8, v7
+; GFX10-DL-NEXT: v_mad_u16 v0, v11, v13, v0
; GFX10-DL-NEXT: v_add_nc_u16 v0, v0, v1
; GFX10-DL-NEXT: global_store_byte v4, v0, s[6:7]
; GFX10-DL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
index daa0df045f72e..8cbc0728f3e2c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
@@ -386,11 +386,11 @@ define amdgpu_ps float @general_case_load_with_waterfall(ptr %p, i16 %stride, i6
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, killed [[DEF]], %subreg.sub1
- ; CHECK-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 16, [[COPY2]], implicit $exec
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
- ; CHECK-NEXT: [[V_AND_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_OR_B32_e64 [[COPY3]], killed [[S_MOV_B32_]], killed [[V_LSHLREV_B32_e64_]], implicit $exec
+ ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY3]], killed [[S_MOV_B32_]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHL_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHL_OR_B32_e64 [[COPY2]], 16, killed [[V_AND_B32_e64_]], implicit $exec
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0
- ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, killed [[V_AND_OR_B32_e64_]], %subreg.sub1, killed [[COPY5]], %subreg.sub2, [[COPY]], %subreg.sub3
+ ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, killed [[V_LSHL_OR_B32_e64_]], %subreg.sub1, killed [[COPY5]], %subreg.sub2, [[COPY]], %subreg.sub3
; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_128 = COPY [[REG_SEQUENCE1]]
diff --git a/llvm/test/CodeGen/AMDGPU/pack-half-to-lshl-or.ll b/llvm/test/CodeGen/AMDGPU/pack-half-to-lshl-or.ll
new file mode 100644
index 0000000000000..9c03aeed6ceba
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/pack-half-to-lshl-or.ll
@@ -0,0 +1,109 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn -mcpu=gfx803 < %s | FileCheck -check-prefixes=GFX8 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12-TRUE16 %s
+
+define i32 @pack_high_half(i16 %hi, i32 %lo) {
+; GFX8-LABEL: pack_high_half:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: pack_high_half:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: pack_high_half:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: pack_high_half:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: pack_high_half:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: pack_high_half:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+ %ext = zext i16 %hi to i32
+ %shl = shl i32 %ext, 16
+ %or = or i32 %shl, %lo
+ ret i32 %or
+}
+
+define i32 @pack_high_half_commuted(i16 %hi, i32 %lo) {
+; GFX8-LABEL: pack_high_half_commuted:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: pack_high_half_commuted:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-FAKE16-LABEL: pack_high_half_commuted:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-TRUE16-LABEL: pack_high_half_commuted:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: pack_high_half_commuted:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-TRUE16-LABEL: pack_high_half_commuted:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+ %ext = zext i16 %hi to i32
+ %shl = shl i32 %ext, 16
+ %or = or i32 %lo, %shl
+ ret i32 %or
+}
diff --git a/llvm/test/CodeGen/AMDGPU/permute_i8.ll b/llvm/test/CodeGen/AMDGPU/permute_i8.ll
index b54d80a03abd0..ecdae6ab20d3e 100644
--- a/llvm/test/CodeGen/AMDGPU/permute_i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/permute_i8.ll
@@ -567,16 +567,17 @@ define hidden void @addUsesOr(ptr addrspace(1) %in0, ptr addrspace(1) %in1, i8 %
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 24, v4
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 24, v7
-; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v4
-; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v7
+; GFX10-NEXT: v_lshrrev_b16 v2, 8, v7
+; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v4
+; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; GFX10-NEXT: v_add_nc_u16 v0, v0, v1
-; GFX10-NEXT: v_lshrrev_b16 v1, 8, v7
-; GFX10-NEXT: v_add_nc_u16 v2, v2, v3
+; GFX10-NEXT: v_add_nc_u16 v1, v4, v2
+; GFX10-NEXT: v_add_nc_u16 v2, v3, v7
; GFX10-NEXT: v_lshlrev_b16 v0, 8, v0
-; GFX10-NEXT: v_add_nc_u16 v1, v4, v1
-; GFX10-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_lshlrev_b16 v1, 8, v1
-; GFX10-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX10-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX10-NEXT: global_store_dword v[5:6], v0, off
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -588,8 +589,9 @@ define hidden void @addUsesOr(ptr addrspace(1) %in0, ptr addrspace(1) %in1, i8 %
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_sdwa v0, v4, v7 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
; GFX9-NEXT: v_add_u16_sdwa v1, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u16_sdwa v0, v4, v7 dst_sel:BYTE_1 dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:BYTE_1
+; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_add_u16_sdwa v1, v4, v7 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX9-NEXT: global_store_dword v[5:6], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -698,24 +700,27 @@ define hidden void @add(ptr addrspace(1) %in0, ptr addrspace(1) %in1, i8 %elt, p
; GFX10-NEXT: v_lshlrev_b16 v0, 8, v0
; GFX10-NEXT: v_lshlrev_b16 v2, 8, v2
; GFX10-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX10-NEXT: global_store_dword v[5:6], v0, off
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: add:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: global_load_dword v4, v[0:1], off
-; GFX9-NEXT: global_load_dword v7, v[2:3], off
+; GFX9-NEXT: global_load_dword v4, v[2:3], off
+; GFX9-NEXT: global_load_dword v7, v[0:1], off
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_add_u16_sdwa v0, v4, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX9-NEXT: v_add_u16_sdwa v1, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:WORD_1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_add_u16_sdwa v0, v4, v7 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_1
-; GFX9-NEXT: v_add_u16_sdwa v1, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX9-NEXT: v_add_u16_sdwa v2, v7, v7 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-; GFX9-NEXT: v_add_u16_sdwa v3, v7, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:WORD_1
+; GFX9-NEXT: v_add_u16_sdwa v2, v7, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_1
+; GFX9-NEXT: v_add_u16_sdwa v3, v7, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v1, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v1, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX9-NEXT: global_store_dword v[5:6], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -931,8 +936,9 @@ define hidden void @add_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX10-NEXT: v_lshlrev_b16 v0, 8, v0
; GFX10-NEXT: v_lshlrev_b16 v2, 8, v2
; GFX10-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX10-NEXT: v_perm_b32 v1, v4, v9, 0x10705
; GFX10-NEXT: global_store_dword v[5:6], v0, off
; GFX10-NEXT: global_store_dword v[7:8], v1, off
@@ -952,13 +958,14 @@ define hidden void @add_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX9-NEXT: s_mov_b32 s4, 0x10705
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v4, v9, s4
-; GFX9-NEXT: v_add_u16_sdwa v1, v4, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_1
-; GFX9-NEXT: v_add_u16_sdwa v2, v4, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX9-NEXT: v_add_u16_sdwa v3, v9, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-; GFX9-NEXT: v_add_u16_sdwa v4, v9, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:WORD_1
+; GFX9-NEXT: v_add_u16_sdwa v1, v9, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX9-NEXT: v_add_u16_sdwa v2, v9, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:WORD_1
+; GFX9-NEXT: v_add_u16_sdwa v3, v4, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_1
+; GFX9-NEXT: v_add_u16_sdwa v4, v4, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v2, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v2, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX9-NEXT: global_store_dword v[5:6], v1, off
; GFX9-NEXT: global_store_dword v[7:8], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -996,8 +1003,9 @@ define hidden void @and_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX10-NEXT: v_and_b32_e32 v3, 0x100, v9
; GFX10-NEXT: v_and_b32_sdwa v0, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
; GFX10-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX10-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_e32 v0, v0, v3
+; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX10-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX10-NEXT: v_perm_b32 v1, v9, v4, 0x5070006
; GFX10-NEXT: global_store_dword v[5:6], v0, off
; GFX10-NEXT: global_store_dword v[7:8], v1, off
@@ -1014,19 +1022,20 @@ define hidden void @and_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: global_load_dword v4, v[0:1], off
; GFX9-NEXT: global_load_dword v9, v[2:3], off
-; GFX9-NEXT: s_mov_b32 s4, 0x5070006
; GFX9-NEXT: v_mov_b32_e32 v0, 2
; GFX9-NEXT: v_mov_b32_e32 v1, 1
+; GFX9-NEXT: s_mov_b32 s4, 0x5070006
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_and_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_sdwa v10, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_and_b32_sdwa v0, v9, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v3, 0x100, v4
+; GFX9-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX9-NEXT: v_or_b32_e32 v3, v10, v3
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX9-NEXT: v_lshl_or_b32 v0, v3, 16, v0
; GFX9-NEXT: v_perm_b32 v2, v4, v9, s4
-; GFX9-NEXT: v_and_b32_sdwa v3, v9, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_and_b32_e32 v9, 0x100, v4
-; GFX9-NEXT: v_and_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_or_b32_sdwa v0, v0, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: global_store_dword v[5:6], v0, off
; GFX9-NEXT: global_store_dword v[7:8], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -1054,20 +1063,21 @@ define hidden void @ashr_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX10-NEXT: global_load_dword v9, v[0:1], off
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v2, v4
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v3, vcc_lo
-; GFX10-NEXT: v_mov_b32_e32 v2, 26
; GFX10-NEXT: global_load_dword v0, v[0:1], off
+; GFX10-NEXT: v_mov_b32_e32 v1, 26
; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_bfe_i32 v1, v9, 0, 8
-; GFX10-NEXT: v_ashrrev_i32_sdwa v2, v2, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_bfe_i32 v2, v9, 0, 8
+; GFX10-NEXT: v_ashrrev_i32_sdwa v1, v1, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_ashrrev_i32_e32 v3, 25, v9
-; GFX10-NEXT: v_lshlrev_b16 v1, 7, v1
-; GFX10-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_lshlrev_b16 v2, 7, v2
+; GFX10-NEXT: v_or_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_ashrrev_i16 v4, 10, v0
; GFX10-NEXT: v_perm_b32 v0, v9, v0, 0x4010707
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffffff00, v1
-; GFX10-NEXT: v_or_b32_sdwa v1, v4, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff00, v2
+; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX10-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX10-NEXT: global_store_dword v[5:6], v1, off
; GFX10-NEXT: global_store_dword v[7:8], v0, off
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -1083,20 +1093,21 @@ define hidden void @ashr_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: global_load_dword v4, v[0:1], off
; GFX9-NEXT: global_load_dword v9, v[2:3], off
+; GFX9-NEXT: v_mov_b32_e32 v0, 26
; GFX9-NEXT: v_mov_b32_e32 v1, 7
; GFX9-NEXT: s_mov_b32 s4, 0x4010707
-; GFX9-NEXT: v_mov_b32_e32 v0, 26
; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_ashrrev_i32_sdwa v0, v0, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_ashrrev_i32_e32 v3, 25, v4
; GFX9-NEXT: v_lshlrev_b16_sdwa v1, v1, sext(v4) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v4, v9, s4
-; GFX9-NEXT: v_ashrrev_i32_sdwa v0, v0, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_ashrrev_i32_e32 v3, 25, v4
; GFX9-NEXT: v_ashrrev_i16_e32 v9, 10, v9
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffffff00, v1
; GFX9-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v1, v9, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffffff00, v1
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX9-NEXT: v_or_b32_sdwa v1, v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: global_store_dword v[5:6], v0, off
; GFX9-NEXT: global_store_dword v[7:8], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -1232,8 +1243,8 @@ define hidden void @ive_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX10-NEXT: v_lshrrev_b32_sdwa v0, v0, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_perm_b32 v1, v10, v4, 0xc0c0006
-; GFX10-NEXT: v_or_b32_sdwa v0, v9, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX10-NEXT: v_or_b32_sdwa v0, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX10-NEXT: v_perm_b32 v1, v10, v9, 0x2000706
; GFX10-NEXT: global_store_dword v[5:6], v0, off
; GFX10-NEXT: global_store_dword v[7:8], v1, off
@@ -1257,8 +1268,8 @@ define hidden void @ive_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v10, v4, s5
-; GFX9-NEXT: v_or_b32_sdwa v0, v9, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX9-NEXT: v_or_b32_sdwa v0, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v2
; GFX9-NEXT: v_perm_b32 v1, v10, v9, s4
; GFX9-NEXT: global_store_dword v[5:6], v0, off
; GFX9-NEXT: global_store_dword v[7:8], v1, off
@@ -1298,8 +1309,9 @@ define hidden void @lhsr_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX10-NEXT: v_lshrrev_b32_e32 v3, 26, v4
; GFX10-NEXT: v_and_b32_e32 v1, 0x7f00, v1
; GFX10-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX10-NEXT: v_or_b32_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX10-NEXT: v_perm_b32 v1, v9, v4, 0x1030707
; GFX10-NEXT: global_store_dword v[5:6], v0, off
; GFX10-NEXT: global_store_dword v[7:8], v1, off
@@ -1316,19 +1328,20 @@ define hidden void @lhsr_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: global_load_dword v4, v[0:1], off
; GFX9-NEXT: global_load_dword v9, v[2:3], off
-; GFX9-NEXT: v_mov_b32_e32 v0, 26
; GFX9-NEXT: s_mov_b32 s4, 0x1030707
+; GFX9-NEXT: v_mov_b32_e32 v0, 26
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_lshrrev_b16_e32 v3, 1, v4
+; GFX9-NEXT: v_lshrrev_b16_e32 v2, 1, v4
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshrrev_b32_sdwa v0, v0, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 25, v9
; GFX9-NEXT: v_perm_b32 v1, v9, v4, s4
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 26, v4
-; GFX9-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX9-NEXT: v_and_b32_e32 v2, 0x7f00, v3
-; GFX9-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshrrev_b32_e32 v3, 26, v4
+; GFX9-NEXT: v_lshrrev_b32_sdwa v0, v0, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_lshrrev_b32_e32 v4, 25, v9
+; GFX9-NEXT: v_and_b32_e32 v2, 0x7f00, v2
+; GFX9-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX9-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-NEXT: global_store_dword v[5:6], v0, off
; GFX9-NEXT: global_store_dword v[7:8], v1, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -1361,18 +1374,19 @@ define hidden void @mul_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_lshrrev_b16 v0, 8, v4
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_lshrrev_b32_e32 v1, 24, v9
-; GFX10-NEXT: v_lshrrev_b16 v2, 8, v9
+; GFX10-NEXT: v_lshrrev_b16 v1, 8, v9
+; GFX10-NEXT: v_lshrrev_b32_e32 v2, 24, v9
; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v9
-; GFX10-NEXT: v_mul_lo_u16 v0, v0, v2
-; GFX10-NEXT: v_mul_lo_u16 v1, v3, v1
-; GFX10-NEXT: v_mul_lo_u16 v2, v4, v9
+; GFX10-NEXT: v_mul_lo_u16 v0, v0, v1
+; GFX10-NEXT: v_mul_lo_u16 v1, v4, v9
+; GFX10-NEXT: v_mul_lo_u16 v2, v3, v2
; GFX10-NEXT: v_mul_lo_u16 v3, v9, v3
; GFX10-NEXT: v_lshlrev_b16 v0, 8, v0
-; GFX10-NEXT: v_lshlrev_b16 v1, 8, v1
-; GFX10-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_lshlrev_b16 v2, 8, v2
+; GFX10-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v1, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX10-NEXT: v_perm_b32 v1, v4, v9, 0x2000504
; GFX10-NEXT: global_store_dword v[5:6], v0, off
; GFX10-NEXT: global_store_dword v[7:8], v1, off
@@ -1392,13 +1406,14 @@ define hidden void @mul_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX9-NEXT: s_mov_b32 s4, 0x2000504
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v4, v9, s4
-; GFX9-NEXT: v_mul_lo_u16_e32 v1, v4, v9
-; GFX9-NEXT: v_mul_lo_u16_sdwa v2, v4, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
-; GFX9-NEXT: v_mul_lo_u16_sdwa v3, v9, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_3
-; GFX9-NEXT: v_mul_lo_u16_sdwa v4, v9, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v2, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_mul_lo_u16_sdwa v1, v9, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_3
+; GFX9-NEXT: v_mul_lo_u16_sdwa v2, v9, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_mul_lo_u16_e32 v3, v4, v9
+; GFX9-NEXT: v_mul_lo_u16_sdwa v4, v4, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
+; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v2, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX9-NEXT: global_store_dword v[5:6], v1, off
; GFX9-NEXT: global_store_dword v[7:8], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -1429,7 +1444,6 @@ define hidden void @or_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1, i
; GFX10-NEXT: global_load_dword v4, v[2:3], off
; GFX10-NEXT: global_load_dword v9, v[0:1], off
; GFX10-NEXT: v_mov_b32_e32 v0, 16
-; GFX10-NEXT: v_bfrev_b32_e32 v2, 4.0
; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_lshlrev_b16 v1, 8, v4
; GFX10-NEXT: v_lshrrev_b32_sdwa v0, v0, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
@@ -1437,8 +1451,9 @@ define hidden void @or_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1, i
; GFX10-NEXT: v_or_b32_sdwa v1, v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX10-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX10-NEXT: v_or_b32_e32 v1, 0x201, v1
-; GFX10-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_e32 v0, 0x102, v0
+; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX10-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX10-NEXT: v_perm_b32 v1, v9, v4, 0x2010005
; GFX10-NEXT: global_store_dword v[5:6], v0, off
; GFX10-NEXT: global_store_dword v[7:8], v1, off
@@ -1451,23 +1466,23 @@ define hidden void @or_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1, i
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 2, v4
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
-; GFX9-NEXT: global_load_dword v2, v[2:3], off
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v4
+; GFX9-NEXT: global_load_dword v2, v[2:3], off
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: global_load_dword v0, v[0:1], off
; GFX9-NEXT: s_mov_b32 s4, 0x2010005
-; GFX9-NEXT: s_movk_i32 s5, 0x102
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v1, v1, s5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v4, v0, v2, s4
; GFX9-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, 0x201, v0
-; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX9-NEXT: v_or_b32_e32 v1, 0x102, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: global_store_dword v[5:6], v0, off
; GFX9-NEXT: global_store_dword v[7:8], v4, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -1548,9 +1563,10 @@ define hidden void @sdiv_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_add_nc_u32_e32 v2, v17, v2
; GFX10-NEXT: v_cndmask_b32_e32 v3, 0, v13, vcc_lo
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX10-NEXT: v_add_nc_u32_sdwa v3, v18, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v1, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX10-NEXT: v_perm_b32 v1, v9, v4, 0x60706
; GFX10-NEXT: global_store_dword v[5:6], v0, off
; GFX10-NEXT: global_store_dword v[7:8], v1, off
@@ -1597,12 +1613,12 @@ define hidden void @sdiv_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX9-NEXT: v_or_b32_e32 v1, 1, v1
; GFX9-NEXT: v_trunc_f32_e32 v17, v17
; GFX9-NEXT: v_trunc_f32_e32 v18, v18
+; GFX9-NEXT: v_cvt_i32_f32_e32 v15, v15
; GFX9-NEXT: v_mad_f32 v11, -v16, v12, v11
+; GFX9-NEXT: v_cvt_i32_f32_e32 v16, v16
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v19|, |v2|
; GFX9-NEXT: v_ashrrev_i32_e32 v9, 30, v9
; GFX9-NEXT: v_or_b32_e32 v10, 1, v10
-; GFX9-NEXT: v_cvt_i32_f32_e32 v15, v15
-; GFX9-NEXT: v_cvt_i32_f32_e32 v16, v16
; GFX9-NEXT: v_mad_f32 v3, -v17, v13, v3
; GFX9-NEXT: v_cvt_i32_f32_e32 v17, v17
; GFX9-NEXT: v_mad_f32 v2, -v18, v4, v2
@@ -1622,8 +1638,9 @@ define hidden void @sdiv_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX9-NEXT: v_add_u32_e32 v3, v17, v3
; GFX9-NEXT: v_add_u32_sdwa v2, v18, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: global_store_dword v[5:6], v1, off
; GFX9-NEXT: global_store_dword v[7:8], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -1726,9 +1743,10 @@ define hidden void @shl_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX10-NEXT: v_and_b32_e32 v1, 0xfffffe00, v1
; GFX10-NEXT: v_and_b32_e32 v0, 0xfc, v0
; GFX10-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; GFX10-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX10-NEXT: v_perm_b32 v1, v9, v4, 0x5000104
-; GFX10-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX10-NEXT: global_store_dword v[5:6], v0, off
; GFX10-NEXT: global_store_dword v[7:8], v1, off
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -1746,17 +1764,18 @@ define hidden void @shl_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX9-NEXT: global_load_dword v9, v[2:3], off
; GFX9-NEXT: s_mov_b32 s4, 0x5000104
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_lshlrev_b16_e32 v1, 2, v4
+; GFX9-NEXT: v_lshlrev_b16_e32 v2, 2, v4
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshlrev_b16_e32 v2, 1, v9
+; GFX9-NEXT: v_lshlrev_b16_e32 v1, 1, v9
; GFX9-NEXT: v_perm_b32 v0, v9, v4, s4
-; GFX9-NEXT: v_and_b32_e32 v3, 0xfffffc00, v1
-; GFX9-NEXT: v_and_b32_e32 v4, 0xfe, v2
-; GFX9-NEXT: v_and_b32_e32 v2, 0xfffffe00, v2
-; GFX9-NEXT: v_and_b32_e32 v1, 0xfc, v1
+; GFX9-NEXT: v_and_b32_e32 v3, 0xfffffe00, v1
+; GFX9-NEXT: v_and_b32_e32 v4, 0xfc, v2
+; GFX9-NEXT: v_and_b32_e32 v2, 0xfffffc00, v2
+; GFX9-NEXT: v_and_b32_e32 v1, 0xfe, v1
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: v_or_b32_e32 v3, v4, v3
-; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: global_store_dword v[5:6], v1, off
; GFX9-NEXT: global_store_dword v[7:8], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -1890,21 +1909,21 @@ define hidden void @srem_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX10-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v12|, |v13|
; GFX10-NEXT: v_or_b32_e32 v16, 1, v16
; GFX10-NEXT: v_cvt_i32_f32_e32 v18, v18
+; GFX10-NEXT: v_lshrrev_b32_e32 v10, 8, v4
; GFX10-NEXT: v_cvt_i32_f32_e32 v19, v19
-; GFX10-NEXT: v_cvt_i32_f32_e32 v20, v20
; GFX10-NEXT: v_cndmask_b32_e32 v2, 0, v11, vcc_lo
; GFX10-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v23|, |v3|
-; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; GFX10-NEXT: v_lshrrev_b32_e32 v10, 8, v4
-; GFX10-NEXT: v_lshrrev_b32_e32 v12, 24, v4
+; GFX10-NEXT: v_cvt_i32_f32_e32 v20, v20
; GFX10-NEXT: v_add_nc_u32_e32 v1, v17, v1
+; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v4
+; GFX10-NEXT: v_add_nc_u32_e32 v2, v18, v2
; GFX10-NEXT: v_cndmask_b32_e32 v3, 0, v14, vcc_lo
; GFX10-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v21|, |v15|
-; GFX10-NEXT: v_add_nc_u32_e32 v2, v18, v2
+; GFX10-NEXT: v_lshrrev_b32_e32 v12, 24, v4
; GFX10-NEXT: v_mul_lo_u32 v1, v1, v4
+; GFX10-NEXT: v_mul_lo_u32 v2, v2, v10
; GFX10-NEXT: v_add_nc_u32_e32 v3, v19, v3
; GFX10-NEXT: v_cndmask_b32_e32 v11, 0, v16, vcc_lo
-; GFX10-NEXT: v_mul_lo_u32 v2, v2, v10
; GFX10-NEXT: v_mul_lo_u32 v3, v3, v0
; GFX10-NEXT: v_add_nc_u32_e32 v11, v20, v11
; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v1
@@ -1913,8 +1932,9 @@ define hidden void @srem_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX10-NEXT: v_sub_nc_u32_e32 v2, v12, v3
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_sub_nc_u32_sdwa v3, v9, v10 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v1, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-NEXT: v_or_b32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX10-NEXT: v_perm_b32 v1, v4, v9, 0x2070306
; GFX10-NEXT: global_store_dword v[5:6], v0, off
; GFX10-NEXT: global_store_dword v[7:8], v1, off
@@ -1961,31 +1981,31 @@ define hidden void @srem_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX9-NEXT: v_cvt_f32_i32_sdwa v13, sext(v9) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
; GFX9-NEXT: v_cmp_ge_f32_e64 s[6:7], |v19|, |v10|
; GFX9-NEXT: v_rcp_f32_e32 v10, v16
-; GFX9-NEXT: v_ashrrev_i32_e32 v2, 30, v2
-; GFX9-NEXT: v_xor_b32_sdwa v19, sext(v9), sext(v4) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_3
; GFX9-NEXT: v_cvt_i32_f32_e32 v17, v17
+; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX9-NEXT: v_ashrrev_i32_e32 v2, 30, v2
; GFX9-NEXT: v_mul_f32_e32 v10, v13, v10
; GFX9-NEXT: v_trunc_f32_e32 v10, v10
-; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX9-NEXT: v_ashrrev_i32_e32 v12, 30, v12
+; GFX9-NEXT: v_xor_b32_sdwa v19, sext(v9), sext(v4) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_3
; GFX9-NEXT: v_cvt_i32_f32_e32 v15, v15
; GFX9-NEXT: v_mad_f32 v13, -v10, v16, v13
; GFX9-NEXT: v_cvt_i32_f32_e32 v10, v10
; GFX9-NEXT: v_or_b32_e32 v2, 1, v2
-; GFX9-NEXT: v_ashrrev_i32_e32 v12, 30, v12
-; GFX9-NEXT: v_ashrrev_i32_e32 v19, 30, v19
; GFX9-NEXT: v_or_b32_e32 v12, 1, v12
+; GFX9-NEXT: v_ashrrev_i32_e32 v19, 30, v19
; GFX9-NEXT: v_or_b32_e32 v14, 1, v14
; GFX9-NEXT: v_or_b32_e32 v19, 1, v19
; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v13|, |v16|
; GFX9-NEXT: v_cndmask_b32_e64 v12, 0, v12, s[4:5]
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v13|, |v16|
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 8, v4
; GFX9-NEXT: v_cndmask_b32_e64 v14, 0, v14, s[6:7]
; GFX9-NEXT: v_cndmask_b32_e32 v13, 0, v19, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; GFX9-NEXT: v_lshrrev_b32_e32 v11, 8, v4
-; GFX9-NEXT: v_lshrrev_b32_e32 v18, 24, v4
; GFX9-NEXT: v_add_u32_e32 v2, v17, v2
; GFX9-NEXT: v_add_u32_e32 v3, v3, v12
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v4
+; GFX9-NEXT: v_lshrrev_b32_e32 v18, 24, v4
; GFX9-NEXT: v_add_u32_e32 v12, v15, v14
; GFX9-NEXT: v_add_u32_e32 v10, v10, v13
; GFX9-NEXT: v_mul_lo_u32 v2, v2, v4
@@ -1997,8 +2017,9 @@ define hidden void @srem_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX9-NEXT: v_sub_u32_e32 v3, v18, v4
; GFX9-NEXT: v_sub_u32_sdwa v4, v9, v10 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v2, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX9-NEXT: v_lshl_or_b32 v0, v3, 16, v0
; GFX9-NEXT: global_store_dword v[5:6], v0, off
; GFX9-NEXT: global_store_dword v[7:8], v1, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -2026,25 +2047,26 @@ define hidden void @sub_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
-; GFX10-NEXT: global_load_dword v2, v[2:3], off
-; GFX10-NEXT: global_load_dword v0, v[0:1], off
+; GFX10-NEXT: global_load_dword v4, v[2:3], off
+; GFX10-NEXT: global_load_dword v9, v[0:1], off
; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v2
-; GFX10-NEXT: v_lshrrev_b16 v3, 8, v2
-; GFX10-NEXT: v_lshrrev_b32_e32 v4, 24, v2
-; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_sub_nc_u16 v3, v0, v3
-; GFX10-NEXT: v_sub_nc_u16 v9, v1, v4
-; GFX10-NEXT: v_sub_nc_u16 v10, v4, v2
-; GFX10-NEXT: v_sub_nc_u16 v1, v4, v1
-; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x6070007
-; GFX10-NEXT: v_lshlrev_b16 v3, 8, v3
-; GFX10-NEXT: v_lshlrev_b16 v4, 8, v9
-; GFX10-NEXT: v_or_b32_sdwa v3, v10, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX10-NEXT: global_store_dword v[5:6], v1, off
-; GFX10-NEXT: global_store_dword v[7:8], v0, off
+; GFX10-NEXT: v_lshrrev_b16 v0, 8, v4
+; GFX10-NEXT: v_lshrrev_b32_e32 v1, 24, v4
+; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v4
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: v_sub_nc_u16 v0, v9, v0
+; GFX10-NEXT: v_sub_nc_u16 v10, v1, v4
+; GFX10-NEXT: v_sub_nc_u16 v3, v2, v1
+; GFX10-NEXT: v_sub_nc_u16 v1, v1, v2
+; GFX10-NEXT: v_lshlrev_b16 v0, 8, v0
+; GFX10-NEXT: v_lshlrev_b16 v2, 8, v3
+; GFX10-NEXT: v_or_b32_sdwa v0, v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX10-NEXT: v_perm_b32 v1, v4, v9, 0x6070007
+; GFX10-NEXT: global_store_dword v[5:6], v0, off
+; GFX10-NEXT: global_store_dword v[7:8], v1, off
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: sub_store_div:
@@ -2061,13 +2083,14 @@ define hidden void @sub_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX9-NEXT: s_mov_b32 s4, 0x6070007
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v9, v4, s4
-; GFX9-NEXT: v_sub_u16_sdwa v1, v4, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-; GFX9-NEXT: v_sub_u16_sdwa v2, v9, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-; GFX9-NEXT: v_sub_u16_sdwa v3, v9, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_3
-; GFX9-NEXT: v_sub_u16_sdwa v4, v9, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:WORD_1
+; GFX9-NEXT: v_sub_u16_sdwa v1, v9, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_3
+; GFX9-NEXT: v_sub_u16_sdwa v2, v9, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:WORD_1
+; GFX9-NEXT: v_sub_u16_sdwa v3, v4, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX9-NEXT: v_sub_u16_sdwa v4, v9, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v2, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v2, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX9-NEXT: global_store_dword v[5:6], v1, off
; GFX9-NEXT: global_store_dword v[7:8], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -2215,47 +2238,48 @@ define hidden void @udiv(ptr addrspace(1) %in0, ptr addrspace(1) %in1, i8 %elt,
; GFX10-NEXT: global_load_dword v2, v[2:3], off
; GFX10-NEXT: global_load_dword v0, v[0:1], off
; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v1, v2
; GFX10-NEXT: v_cvt_f32_ubyte1_e32 v3, v2
+; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v1, v2
+; GFX10-NEXT: v_cvt_f32_ubyte2_e32 v4, v2
; GFX10-NEXT: v_cvt_f32_ubyte3_e32 v9, v2
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cvt_f32_ubyte3_e32 v14, v0
-; GFX10-NEXT: v_cvt_f32_ubyte2_e32 v4, v2
-; GFX10-NEXT: v_rcp_f32_e32 v10, v1
; GFX10-NEXT: v_rcp_f32_e32 v11, v3
+; GFX10-NEXT: v_rcp_f32_e32 v10, v1
+; GFX10-NEXT: v_rcp_f32_e32 v12, v4
; GFX10-NEXT: v_rcp_f32_e32 v13, v9
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v15, v0
-; GFX10-NEXT: v_rcp_f32_e32 v12, v4
; GFX10-NEXT: v_perm_b32 v0, v0, v2, 0x40207
-; GFX10-NEXT: v_mul_f32_e32 v10, v14, v10
; GFX10-NEXT: v_mul_f32_e32 v11, v4, v11
-; GFX10-NEXT: v_mul_f32_e32 v13, v1, v13
+; GFX10-NEXT: v_mul_f32_e32 v10, v14, v10
; GFX10-NEXT: v_mul_f32_e32 v12, v15, v12
-; GFX10-NEXT: v_trunc_f32_e32 v10, v10
+; GFX10-NEXT: v_mul_f32_e32 v13, v1, v13
; GFX10-NEXT: v_trunc_f32_e32 v11, v11
-; GFX10-NEXT: v_trunc_f32_e32 v13, v13
+; GFX10-NEXT: v_trunc_f32_e32 v10, v10
; GFX10-NEXT: v_trunc_f32_e32 v12, v12
+; GFX10-NEXT: v_trunc_f32_e32 v13, v13
+; GFX10-NEXT: v_mad_f32 v16, -v11, v3, v4
+; GFX10-NEXT: v_cvt_u32_f32_e32 v11, v11
; GFX10-NEXT: v_mad_f32 v14, -v10, v1, v14
; GFX10-NEXT: v_cvt_u32_f32_e32 v10, v10
-; GFX10-NEXT: v_mad_f32 v16, -v11, v3, v4
; GFX10-NEXT: v_mad_f32 v17, -v13, v9, v1
-; GFX10-NEXT: v_cvt_u32_f32_e32 v11, v11
-; GFX10-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v14|, v1
+; GFX10-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v16|, v3
; GFX10-NEXT: v_cvt_u32_f32_e32 v13, v13
; GFX10-NEXT: v_mad_f32 v15, -v12, v4, v15
; GFX10-NEXT: v_cvt_u32_f32_e32 v12, v12
-; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v10, vcc_lo
-; GFX10-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v16|, v3
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v11, vcc_lo
-; GFX10-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v17|, v9
+; GFX10-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v14|, v1
; GFX10-NEXT: v_lshlrev_b16 v3, 8, v3
+; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v10, vcc_lo
+; GFX10-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v17|, v9
+; GFX10-NEXT: v_or_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0, v13, vcc_lo
; GFX10-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v15|, v4
-; GFX10-NEXT: v_or_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX10-NEXT: v_lshlrev_b16 v9, 8, v9
; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, 0, v12, vcc_lo
-; GFX10-NEXT: v_or_b32_sdwa v3, v4, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v3, v4, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX10-NEXT: global_store_dword v[5:6], v1, off
; GFX10-NEXT: global_store_dword v[7:8], v0, off
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -2312,8 +2336,9 @@ define hidden void @udiv(ptr addrspace(1) %in0, ptr addrspace(1) %in1, i8 %elt,
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4
; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v2, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: global_store_dword v[5:6], v1, off
; GFX9-NEXT: global_store_dword v[7:8], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -2413,8 +2438,8 @@ define hidden void @urem_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX10-NEXT: v_rcp_f32_e32 v11, v3
; GFX10-NEXT: v_rcp_f32_e32 v12, v4
; GFX10-NEXT: v_rcp_f32_e32 v13, v9
-; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v16, 8, v2
+; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v17, 24, v2
; GFX10-NEXT: v_mul_f32_e32 v10, v3, v10
; GFX10-NEXT: v_mul_f32_e32 v11, v3, v11
@@ -2448,10 +2473,11 @@ define hidden void @urem_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX10-NEXT: v_or_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_mul_lo_u32 v9, v9, v17
; GFX10-NEXT: v_sub_nc_u32_e32 v4, v16, v4
+; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX10-NEXT: v_sub_nc_u32_sdwa v9, v0, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x2050505
-; GFX10-NEXT: v_or_b32_sdwa v3, v4, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v3, v4, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX10-NEXT: global_store_dword v[5:6], v1, off
; GFX10-NEXT: global_store_dword v[7:8], v0, off
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -2501,12 +2527,12 @@ define hidden void @urem_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v16, vcc
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v19|, v11
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v17, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v10, 8, v4
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v13|, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v4
-; GFX9-NEXT: v_lshrrev_b32_e32 v10, 8, v4
+; GFX9-NEXT: v_perm_b32 v1, v4, v9, s4
; GFX9-NEXT: v_lshrrev_b32_e32 v12, 24, v4
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v18, vcc
-; GFX9-NEXT: v_perm_b32 v1, v4, v9, s4
; GFX9-NEXT: v_mul_lo_u32 v4, v15, v4
; GFX9-NEXT: v_mul_lo_u32 v2, v2, v10
; GFX9-NEXT: v_mul_lo_u32 v0, v3, v0
@@ -2516,8 +2542,9 @@ define hidden void @urem_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX9-NEXT: v_sub_u32_e32 v0, v10, v0
; GFX9-NEXT: v_sub_u32_sdwa v3, v9, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v2
; GFX9-NEXT: global_store_dword v[5:6], v0, off
; GFX9-NEXT: global_store_dword v[7:8], v1, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -2559,8 +2586,9 @@ define hidden void @xor_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX10-NEXT: v_xor_b32_e32 v0, 0x200, v0
; GFX10-NEXT: v_xor_b32_e32 v3, 0x100, v3
; GFX10-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX10-NEXT: v_or_b32_sdwa v1, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX10-NEXT: v_perm_b32 v1, v9, v4, 0x5060307
; GFX10-NEXT: global_store_dword v[5:6], v0, off
; GFX10-NEXT: global_store_dword v[7:8], v1, off
@@ -2578,20 +2606,21 @@ define hidden void @xor_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1,
; GFX9-NEXT: global_load_dword v4, v[0:1], off
; GFX9-NEXT: global_load_dword v9, v[2:3], off
; GFX9-NEXT: s_movk_i32 s4, 0xff00
-; GFX9-NEXT: v_mov_b32_e32 v0, 1
-; GFX9-NEXT: v_mov_b32_e32 v1, 2
+; GFX9-NEXT: v_mov_b32_e32 v1, 1
+; GFX9-NEXT: v_mov_b32_e32 v0, 2
; GFX9-NEXT: s_mov_b32 s5, 0x5060307
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_and_b32_sdwa v2, v4, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_and_b32_e32 v3, 0xffffff00, v9
-; GFX9-NEXT: v_xor_b32_sdwa v0, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-; GFX9-NEXT: v_xor_b32_sdwa v1, v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-NEXT: v_xor_b32_sdwa v1, v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
; GFX9-NEXT: v_xor_b32_e32 v2, 0x200, v2
+; GFX9-NEXT: v_xor_b32_sdwa v0, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_xor_b32_e32 v3, 0x100, v3
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX9-NEXT: v_or_b32_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX9-NEXT: v_perm_b32 v4, v9, v4, s5
; GFX9-NEXT: global_store_dword v[5:6], v0, off
; GFX9-NEXT: global_store_dword v[7:8], v4, off
diff --git a/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll b/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
index 40634bb5ad2e9..8b66d1a50fb94 100644
--- a/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
@@ -444,15 +444,26 @@ define i64 @bitcast_combine_scalar_to_vector_v4i16(i16 %arg) {
; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX89-LABEL: bitcast_combine_scalar_to_vector_v4i16:
-; GFX89: ; %bb.0:
-; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX89-NEXT: v_and_b32_e32 v1, 0xffffff00, v0
-; GFX89-NEXT: v_or_b32_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX89-NEXT: v_lshlrev_b32_e32 v2, 16, v1
-; GFX89-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX89-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX89-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: bitcast_combine_scalar_to_vector_v4i16:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_and_b32_e32 v1, 0xffffff00, v0
+; VI-NEXT: v_or_b32_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: bitcast_combine_scalar_to_vector_v4i16:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffffff00, v0
+; GFX9-NEXT: v_or_b32_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_combine_scalar_to_vector_v4i16:
; GFX11: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll b/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
index fa705fb455ba8..31ea6efb6907f 100644
--- a/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
@@ -1217,13 +1217,14 @@ define amdgpu_kernel void @mul_v4i8(ptr addrspace(1) %out, ptr addrspace(1) %ina
; GFX9-NEXT: global_load_dword v2, v0, s[6:7]
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_mul_lo_u16_e32 v3, v1, v2
-; GFX9-NEXT: v_mul_lo_u16_sdwa v4, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
-; GFX9-NEXT: v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
-; GFX9-NEXT: v_mul_lo_u16_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NEXT: v_or_b32_sdwa v2, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v1, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_mul_lo_u16_sdwa v3, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
+; GFX9-NEXT: v_mul_lo_u16_sdwa v4, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-NEXT: v_mul_lo_u16_e32 v5, v1, v2
+; GFX9-NEXT: v_mul_lo_u16_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
+; GFX9-NEXT: v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v2, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
;
@@ -1238,23 +1239,24 @@ define amdgpu_kernel void @mul_v4i8(ptr addrspace(1) %out, ptr addrspace(1) %ina
; GFX10-NEXT: global_load_dword v1, v0, s[2:3]
; GFX10-NEXT: global_load_dword v2, v0, s[6:7]
; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_lshrrev_b32_e32 v0, 24, v1
-; GFX10-NEXT: v_lshrrev_b16 v3, 8, v1
+; GFX10-NEXT: v_lshrrev_b16 v0, 8, v1
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_lshrrev_b16 v4, 8, v2
+; GFX10-NEXT: v_lshrrev_b16 v3, 8, v2
+; GFX10-NEXT: v_lshrrev_b32_e32 v4, 24, v1
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 24, v2
-; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v2
+; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v2
+; GFX10-NEXT: v_mul_lo_u16 v0, v0, v3
+; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX10-NEXT: v_mul_lo_u16 v4, v4, v5
; GFX10-NEXT: v_mul_lo_u16 v1, v1, v2
-; GFX10-NEXT: v_mul_lo_u16 v3, v3, v4
-; GFX10-NEXT: v_mul_lo_u16 v0, v0, v5
-; GFX10-NEXT: v_mul_lo_u16 v2, v6, v7
-; GFX10-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX10-NEXT: v_lshlrev_b16 v0, 8, v0
-; GFX10-NEXT: v_or_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_mul_lo_u16 v3, v3, v6
+; GFX10-NEXT: v_lshlrev_b16 v2, 8, v4
+; GFX10-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v1, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: v_mov_b32_e32 v2, 0
-; GFX10-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX10-NEXT: global_store_dword v2, v0, s[0:1]
; GFX10-NEXT: s_endpgm
entry:
@@ -1372,20 +1374,22 @@ define amdgpu_kernel void @mul_v8i8(ptr addrspace(1) %out, ptr addrspace(1) %ina
; GFX9-NEXT: global_load_dwordx2 v[2:3], v4, s[6:7]
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_mul_lo_u16_e32 v5, v1, v3
-; GFX9-NEXT: v_mul_lo_u16_sdwa v6, v1, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
-; GFX9-NEXT: v_mul_lo_u16_sdwa v7, v1, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
-; GFX9-NEXT: v_mul_lo_u16_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NEXT: v_mul_lo_u16_e32 v3, v0, v2
-; GFX9-NEXT: v_mul_lo_u16_sdwa v8, v0, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
-; GFX9-NEXT: v_mul_lo_u16_sdwa v9, v0, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
+; GFX9-NEXT: v_mul_lo_u16_e32 v5, v0, v2
+; GFX9-NEXT: v_mul_lo_u16_sdwa v6, v0, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
+; GFX9-NEXT: v_mul_lo_u16_sdwa v7, v0, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
; GFX9-NEXT: v_mul_lo_u16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NEXT: v_or_b32_sdwa v2, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v1, v1, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v3, v3, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v0, v0, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_mul_lo_u16_sdwa v2, v1, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
+; GFX9-NEXT: v_mul_lo_u16_sdwa v8, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-NEXT: v_mul_lo_u16_e32 v9, v1, v3
+; GFX9-NEXT: v_mul_lo_u16_sdwa v1, v1, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
+; GFX9-NEXT: v_or_b32_sdwa v3, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v1, v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v0, v0, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_sdwa v2, v8, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX9-NEXT: s_endpgm
;
@@ -1400,38 +1404,40 @@ define amdgpu_kernel void @mul_v8i8(ptr addrspace(1) %out, ptr addrspace(1) %ina
; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[2:3]
; GFX10-NEXT: global_load_dwordx2 v[2:3], v4, s[6:7]
; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_lshrrev_b32_e32 v5, 24, v0
-; GFX10-NEXT: v_lshrrev_b16 v6, 8, v0
-; GFX10-NEXT: v_lshrrev_b32_e32 v8, 24, v1
-; GFX10-NEXT: v_lshrrev_b16 v9, 8, v1
+; GFX10-NEXT: v_lshrrev_b16 v4, 8, v1
+; GFX10-NEXT: v_lshrrev_b16 v9, 8, v0
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_lshrrev_b32_e32 v11, 24, v2
-; GFX10-NEXT: v_lshrrev_b16 v12, 8, v2
-; GFX10-NEXT: v_lshrrev_b16 v13, 8, v3
-; GFX10-NEXT: v_lshrrev_b32_e32 v14, 24, v3
-; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX10-NEXT: v_lshrrev_b32_e32 v15, 16, v3
-; GFX10-NEXT: v_mul_lo_u16 v1, v1, v3
+; GFX10-NEXT: v_lshrrev_b16 v10, 8, v3
+; GFX10-NEXT: v_lshrrev_b16 v13, 8, v2
+; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX10-NEXT: v_lshrrev_b32_e32 v6, 24, v1
+; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v0
+; GFX10-NEXT: v_lshrrev_b32_e32 v8, 24, v0
+; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v3
+; GFX10-NEXT: v_lshrrev_b32_e32 v12, 24, v3
+; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v2
+; GFX10-NEXT: v_lshrrev_b32_e32 v15, 24, v2
; GFX10-NEXT: v_mul_lo_u16 v0, v0, v2
+; GFX10-NEXT: v_mul_lo_u16 v1, v1, v3
; GFX10-NEXT: v_mul_lo_u16 v2, v9, v13
-; GFX10-NEXT: v_mul_lo_u16 v3, v8, v14
+; GFX10-NEXT: v_mul_lo_u16 v3, v4, v10
+; GFX10-NEXT: v_mul_lo_u16 v4, v8, v15
; GFX10-NEXT: v_mul_lo_u16 v6, v6, v12
-; GFX10-NEXT: v_mul_lo_u16 v5, v5, v11
-; GFX10-NEXT: v_mul_lo_u16 v7, v7, v15
-; GFX10-NEXT: v_mul_lo_u16 v4, v4, v10
+; GFX10-NEXT: v_mul_lo_u16 v7, v7, v14
; GFX10-NEXT: v_lshlrev_b16 v2, 8, v2
; GFX10-NEXT: v_lshlrev_b16 v3, 8, v3
+; GFX10-NEXT: v_mul_lo_u16 v5, v5, v11
+; GFX10-NEXT: v_lshlrev_b16 v4, 8, v4
; GFX10-NEXT: v_lshlrev_b16 v6, 8, v6
-; GFX10-NEXT: v_lshlrev_b16 v5, 8, v5
-; GFX10-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v2, v7, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v0, v0, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v3, v4, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v2, v7, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_sdwa v3, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX10-NEXT: v_mov_b32_e32 v4, 0
-; GFX10-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX10-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX10-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX10-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX10-NEXT: s_endpgm
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll b/llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
index 20789232b1f25..722c553861656 100644
--- a/llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
+++ b/llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
@@ -733,71 +733,74 @@ define amdgpu_kernel void @v8i8_multiuse_multiblock(ptr addrspace(1) %src1, ptr
; GFX942-NEXT: s_cbranch_execz .LBB13_2
; GFX942-NEXT: ; %bb.1: ; %bb.1
; GFX942-NEXT: s_movk_i32 s6, 0xff00
-; GFX942-NEXT: v_mov_b32_e32 v5, 8
-; GFX942-NEXT: v_and_b32_sdwa v6, v0, s6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX942-NEXT: v_mov_b32_e32 v6, 8
+; GFX942-NEXT: v_and_b32_sdwa v5, v0, s6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX942-NEXT: v_lshlrev_b16_sdwa v6, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX942-NEXT: s_mov_b32 s6, 0x6070504
; GFX942-NEXT: v_cmp_gt_u32_e32 vcc, 7, v2
; GFX942-NEXT: v_and_b32_e32 v4, 0xffffff00, v0
-; GFX942-NEXT: v_lshlrev_b16_sdwa v5, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX942-NEXT: v_or_b32_sdwa v6, v0, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX942-NEXT: v_perm_b32 v7, v0, v0, s6
; GFX942-NEXT: s_andn2_b64 s[2:3], s[2:3], exec
; GFX942-NEXT: s_and_b64 s[6:7], vcc, exec
; GFX942-NEXT: v_mov_b32_e32 v3, 0
-; GFX942-NEXT: v_or_b32_sdwa v4, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-; GFX942-NEXT: v_or_b32_sdwa v5, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX942-NEXT: v_or_b32_sdwa v6, v0, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX942-NEXT: v_or_b32_sdwa v4, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX942-NEXT: v_or_b32_sdwa v5, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX942-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX942-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
-; GFX942-NEXT: v_or_b32_sdwa v6, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX942-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX942-NEXT: v_lshl_or_b32 v5, v5, 16, v6
+; GFX942-NEXT: v_lshl_or_b32 v4, v4, 16, v6
; GFX942-NEXT: global_store_dword v3, v0, s[12:13]
; GFX942-NEXT: global_store_dword v3, v7, s[12:13] offset:8
-; GFX942-NEXT: global_store_dword v3, v6, s[12:13] offset:16
+; GFX942-NEXT: global_store_dword v3, v5, s[12:13] offset:16
; GFX942-NEXT: global_store_dword v3, v4, s[12:13] offset:24
; GFX942-NEXT: .LBB13_2: ; %Flow
; GFX942-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX942-NEXT: s_and_saveexec_b64 s[4:5], s[2:3]
; GFX942-NEXT: s_cbranch_execz .LBB13_4
; GFX942-NEXT: ; %bb.3: ; %bb.2
-; GFX942-NEXT: v_lshlrev_b16_e32 v3, 8, v1
; GFX942-NEXT: v_and_b32_e32 v4, 0xffffff00, v1
+; GFX942-NEXT: v_lshlrev_b16_e32 v3, 8, v1
+; GFX942-NEXT: v_or_b32_sdwa v4, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX942-NEXT: v_or_b32_sdwa v3, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX942-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX942-NEXT: v_and_b32_e32 v5, 0xffffff00, v0
; GFX942-NEXT: s_mov_b32 s2, 0xc0c0001
-; GFX942-NEXT: v_or_b32_sdwa v3, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX942-NEXT: v_or_b32_sdwa v4, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX942-NEXT: v_or_b32_sdwa v5, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX942-NEXT: v_perm_b32 v1, 0, v1, s2
; GFX942-NEXT: v_mov_b32_e32 v2, 0
-; GFX942-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX942-NEXT: v_lshl_or_b32 v3, v3, 16, v4
+; GFX942-NEXT: v_or_b32_sdwa v5, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX942-NEXT: v_perm_b32 v6, 0, v0, s2
; GFX942-NEXT: s_mov_b32 s3, 0xffff0000
-; GFX942-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX942-NEXT: v_perm_b32 v1, 0, v1, s2
; GFX942-NEXT: v_and_or_b32 v7, v0, s3, v6
-; GFX942-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX942-NEXT: v_or_b32_e32 v1, v6, v1
+; GFX942-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX942-NEXT: v_lshl_or_b32 v1, v1, 16, v6
; GFX942-NEXT: global_store_dword v2, v3, s[14:15]
; GFX942-NEXT: global_store_dword v2, v4, s[14:15] offset:8
; GFX942-NEXT: global_store_dword v2, v7, s[14:15] offset:16
; GFX942-NEXT: global_store_dword v2, v1, s[14:15] offset:24
; GFX942-NEXT: .LBB13_4: ; %bb.3
; GFX942-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX942-NEXT: s_movk_i32 s3, 0xff00
; GFX942-NEXT: v_mov_b32_e32 v4, 8
+; GFX942-NEXT: s_movk_i32 s3, 0xff00
+; GFX942-NEXT: v_lshlrev_b16_sdwa v4, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX942-NEXT: s_movk_i32 s2, 0xff
; GFX942-NEXT: v_and_b32_sdwa v2, v0, s3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX942-NEXT: v_lshlrev_b16_sdwa v4, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX942-NEXT: v_or_b32_sdwa v3, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX942-NEXT: v_or_b32_sdwa v5, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX942-NEXT: v_or_b32_sdwa v3, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX942-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX942-NEXT: v_lshlrev_b16_e32 v6, 8, v0
; GFX942-NEXT: v_and_b32_sdwa v7, v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX942-NEXT: v_mov_b32_e32 v1, 0
-; GFX942-NEXT: v_or_b32_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX942-NEXT: v_or_b32_sdwa v7, v7, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX942-NEXT: v_or_b32_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX942-NEXT: v_or_b32_sdwa v4, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX942-NEXT: v_or_b32_sdwa v0, v0, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-; GFX942-NEXT: v_or_b32_sdwa v4, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX942-NEXT: v_or_b32_sdwa v0, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX942-NEXT: v_or_b32_sdwa v2, v2, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX942-NEXT: v_mov_b32_e32 v1, 0
+; GFX942-NEXT: v_lshl_or_b32 v3, v3, 16, v5
+; GFX942-NEXT: v_or_b32_e32 v7, v7, v6
+; GFX942-NEXT: v_or_b32_sdwa v4, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX942-NEXT: v_or_b32_sdwa v0, v0, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX942-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX942-NEXT: v_lshl_or_b32 v0, v0, 16, v5
+; GFX942-NEXT: v_lshl_or_b32 v4, v4, 16, v2
+; GFX942-NEXT: v_lshl_or_b32 v2, v7, 16, v2
; GFX942-NEXT: global_store_dword v1, v3, s[0:1]
; GFX942-NEXT: global_store_dword v1, v0, s[0:1] offset:8
; GFX942-NEXT: global_store_dword v1, v4, s[0:1] offset:16
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