[llvm] [AMDGPU] Select the high-half 16-bit packing idiom to v_lshl_or_b32 (PR #206058)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 26 07:59:56 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Barbara Mitic (barbara-amd)
<details>
<summary>Changes</summary>
The (hi << 16) | z high-half packing idiom is not fused into v_lshl_or_b32 by the existing (or (shl x, y), z) selection. By the time it reaches ISel the DAG combiner has rewritten (ext i16) << 16 into bitcast(build_vector (i16 0), hi), so there is no shl node left to match and the build_vector and or are selected separately.
Add ISel patterns that match the build_vector form directly and fold it into v_lshl_or_b32. Both operand orders of the or are handled. On the non-real-true16 path the high-half source is already a VGPR_32; on the real-true16 path it is widened from a VGPR_16 with a REG_SEQUENCE. Only the divergent case is matched; gated on GFX9+, where v_lshl_or_b32 is available.
---
Patch is 1.05 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/206058.diff
24 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SIInstructions.td (+38)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll (+2360-2496)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll (+350-392)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll (+344-380)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll (+532-576)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll (+60-78)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll (+944-1008)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll (+98-126)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll (+130-150)
- (modified) llvm/test/CodeGen/AMDGPU/calling-conventions.ll (+125-130)
- (modified) llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll (+30-33)
- (modified) llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll (+85-84)
- (modified) llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll (+73-72)
- (modified) llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll (+2-6)
- (modified) llvm/test/CodeGen/AMDGPU/idot4u.ll (+48-46)
- (modified) llvm/test/CodeGen/AMDGPU/idot8s.ll (+170-164)
- (modified) llvm/test/CodeGen/AMDGPU/idot8u.ll (+106-102)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll (+3-3)
- (added) llvm/test/CodeGen/AMDGPU/pack-half-to-lshl-or.ll (+109)
- (modified) llvm/test/CodeGen/AMDGPU/permute_i8.ll (+213-184)
- (modified) llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll (+20-9)
- (modified) llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll (+62-56)
- (modified) llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll (+32-29)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 750cb1973e21f..9dda188bf9417 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -4024,6 +4024,44 @@ def : GCNPat <
(v2i16 (V_LSHL_OR_B32_e64 $src1, (i32 16), (i32 (V_AND_B32_e64 (i32 (V_MOV_B32_e32 (i32 0xffff))), $src0))))
>;
+// Fold the (hi << 16) | z high-half packing idiom into v_lshl_or_b32.
+// DAGCombine canonicalizes a 16-bit value shifted into the high half to
+// bitcast(build_vector (i16 0), hi), leaving no shl for the
+// (or (shl x, y), z) selection to match, so match the build_vector directly.
+let True16Predicate = NotUseRealTrue16Insts in {
+def : GCNPat <
+ (i32 (DivergentBinFrag<or>
+ (i32 (bitconvert (v2i16 (build_vector (i16 0), (i16 VGPR_32:$src_hi))))),
+ i32:$src2)),
+ (V_LSHL_OR_B32_e64 VGPR_32:$src_hi, (i32 16), VSrc_b32:$src2)
+>;
+def : GCNPat <
+ (i32 (DivergentBinFrag<or>
+ i32:$src2,
+ (i32 (bitconvert (v2i16 (build_vector (i16 0), (i16 VGPR_32:$src_hi))))))),
+ (V_LSHL_OR_B32_e64 VGPR_32:$src_hi, (i32 16), VSrc_b32:$src2)
+>;
+}
+
+let True16Predicate = UseRealTrue16Insts in {
+def : GCNPat <
+ (i32 (DivergentBinFrag<or>
+ (i32 (bitconvert (v2i16 (build_vector (i16 0), (i16 VGPR_16:$src_hi))))),
+ i32:$src2)),
+ (V_LSHL_OR_B32_e64
+ (i32 (REG_SEQUENCE VGPR_32, VGPR_16:$src_hi, lo16, (i16 (IMPLICIT_DEF)), hi16)),
+ (i32 16), VSrc_b32:$src2)
+>;
+def : GCNPat <
+ (i32 (DivergentBinFrag<or>
+ i32:$src2,
+ (i32 (bitconvert (v2i16 (build_vector (i16 0), (i16 VGPR_16:$src_hi))))))),
+ (V_LSHL_OR_B32_e64
+ (i32 (REG_SEQUENCE VGPR_32, VGPR_16:$src_hi, lo16, (i16 (IMPLICIT_DEF)), hi16)),
+ (i32 16), VSrc_b32:$src2)
+>;
+}
+
// With multiple uses of the shift, this will duplicate the shift and
// increase register pressure.
def : GCNPat <
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
index 2d5fc5cf22425..7672755c6b386 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
@@ -14503,14 +14503,14 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:388
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32
@@ -14527,16 +14527,16 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:84
; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:80
; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:76
-; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:72
-; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:68
+; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:72
+; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:68
; GFX9-NEXT: buffer_load_ushort v38, off, s[0:3], s32 offset:64
; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:60
-; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:56
-; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:52
+; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:56
+; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:52
; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:48
; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:44
-; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:40
-; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:36
+; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:40
+; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:36
; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:32
; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:28
; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:24
@@ -14644,31 +14644,31 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:364
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:188
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:360
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:184
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:356
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:180
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:352
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:176
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:348
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:172
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
@@ -14680,13 +14680,13 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:340
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:164
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:336
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:160
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
@@ -14748,8 +14748,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB14_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0xc0c0004
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v10, v55, v32, s6
@@ -14772,19 +14772,19 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s6
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_perm_b32 v16, v43, v16, s6
; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v1, v2, v1, s6
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s6
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
@@ -14847,11 +14847,11 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_perm_b32 v9, v39, v40, s6
; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; GFX9-NEXT: v_perm_b32 v10, v62, v63, s6
+; GFX9-NEXT: v_perm_b32 v10, v63, v62, s6
; GFX9-NEXT: v_lshl_or_b32 v10, v11, 16, v10
-; GFX9-NEXT: v_perm_b32 v11, v59, v54, s6
+; GFX9-NEXT: v_perm_b32 v11, v54, v59, s6
; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
-; GFX9-NEXT: v_perm_b32 v12, v58, v37, s6
+; GFX9-NEXT: v_perm_b32 v12, v37, v58, s6
; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; GFX9-NEXT: v_perm_b32 v13, v47, v52, s6
; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
@@ -14867,12 +14867,12 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr40
-; GFX9-NEXT: ; implicit-def: $vgpr62
; GFX9-NEXT: ; implicit-def: $vgpr63
-; GFX9-NEXT: ; implicit-def: $vgpr59
+; GFX9-NEXT: ; implicit-def: $vgpr62
; GFX9-NEXT: ; implicit-def: $vgpr54
-; GFX9-NEXT: ; implicit-def: $vgpr58
+; GFX9-NEXT: ; implicit-def: $vgpr59
; GFX9-NEXT: ; implicit-def: $vgpr37
+; GFX9-NEXT: ; implicit-def: $vgpr58
; GFX9-NEXT: ; implicit-def: $vgpr47
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr33
@@ -14895,21 +14895,21 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v18, v19, v18, s6
; GFX9-NEXT: v_lshl_or_b32 v17, v18, 16, v17
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v18, v19, v18, s6
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v19, v20, v19, s6
; GFX9-NEXT: v_lshl_or_b32 v18, v19, 16, v18
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v19, v20, v19, s6
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v20, v21, v20, s6
; GFX9-NEXT: v_lshl_or_b32 v19, v20, 16, v19
@@ -15218,23 +15218,22 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB14_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; GFX9-NEXT: s_movk_i32 s6, 0x300
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
@@ -15257,19 +15256,16 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(24)
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
-; GFX9-NEXT: s_waitcnt vmcnt(22)
-; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v8
; GFX9-NEXT: s_waitcnt vmcnt(21)
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v2
; GFX9-NEXT: s_waitcnt vmcnt(20)
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v3
-; GFX9-NEXT: s_waitcnt vmcnt(19)
-; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4
+; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v8
; GFX9-NEXT: v_lshlrev_b16_e32 v18, 8, v18
-; GFX9-NEXT: s_waitcnt vmcnt(18)
-; GFX9-NEXT: v_lshlrev_b16_e32 v21, 8, v21
+; GFX9-NEXT: s_waitcnt vmcnt(17)
+; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v4
; GFX9-NEXT: s_waitcnt vmcnt(16)
; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v17
; GFX9-NEXT: s_waitcnt vmcnt(15)
@@ -15282,10 +15278,10 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v6
; GFX9-NEXT: s_waitcnt vmcnt(11)
; GFX9-NEXT: v_lshlrev_b16_e32 v20, 8, v20
-; GFX9-NEXT: s_waitcnt vmcnt(10)
-; GFX9-NEXT: v_lshlrev_b16_e32 v22, 8, v22
+; GFX9-NEXT: v_lshlrev_b16_e32 v21, 8, v21
; GFX9-NEXT: s_waitcnt vmcnt(9)
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v7
+; GFX9-NEXT: v_lshlrev_b16_e32 v22, 8, v22
; GFX9-NEXT: s_waitcnt vmcnt(8)
; GFX9-NEXT: v_lshlrev_b16_e32 v23, 8, v23
; GFX9-NEXT: v_lshlrev_b16_e32 v24, 8, v24
@@ -15307,19 +15303,19 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v1, 3, v1
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
-; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u16_e32 v2, 3, v2
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/206058
More information about the llvm-commits
mailing list