[llvm] [RISCV][XCV] Add LLVM intrinsics and patterns for XCVsimd (PR #204880)

[Luke Lau via llvm-commits]

================
@@ -304,9 +304,64 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
     }
   }
 
+  // XCVsimd packs 2 x i16 / 4 x i8 into a GPR (RV32 only); make those types
+  // legal so element-wise IR ops select the cv.*.h / cv.*.b SIMD instructions.
+  if (Subtarget.hasVendorXCVsimd() && !Subtarget.hasStdExtP()) {
+    addRegisterClass(MVT::v2i16, &RISCV::GPRRegClass);
+    addRegisterClass(MVT::v4i8, &RISCV::GPRRegClass);
+  }
+
   // Compute derived properties from the register classes.
   computeRegisterProperties(STI.getRegisterInfo());
 
+  if (Subtarget.hasVendorXCVsimd() && !Subtarget.hasStdExtP()) {
+    for (MVT VT : {MVT::v2i16, MVT::v4i8}) {
+      setOperationAction({ISD::ADD, ISD::SUB, ISD::AND, ISD::OR, ISD::XOR,
+                          ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX, ISD::ABS},
+                         VT, Legal);
+      setOperationAction({ISD::LOAD, ISD::STORE}, VT, Legal);
----------------
lukel97 wrote:

I think the standard codegen patterns seem reasonable enough to support independent of the builtins and RFC. If you split those off they could be landed separately.

You could probably start with loads and stores for now, and follow up with bitcasts + arithmetic later

https://github.com/llvm/llvm-project/pull/204880