[llvm] 0b6faee - [LoopInterchange] Reject inner-latch lcssa PHI feeding the exit condition (#202863)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 14 23:46:18 PDT 2026
Author: Madhur Amilkanthwar
Date: 2026-06-15T06:46:13Z
New Revision: 0b6faeeaadc5791797e3708c4084f2be74212ca4
URL: https://github.com/llvm/llvm-project/commit/0b6faeeaadc5791797e3708c4084f2be74212ca4
DIFF: https://github.com/llvm/llvm-project/commit/0b6faeeaadc5791797e3708c4084f2be74212ca4.diff
LOG: [LoopInterchange] Reject inner-latch lcssa PHI feeding the exit condition (#202863)
In a multi-level nest, an lcssa PHI in the inner loop latch that feeds
the latch's exit condition can be left with a stale incoming block after
a subsequent interchange rewires the CFG, producing invalid IR. This
happened even when the outer latch had a single predecessor, where the
legality check returned early. Instead, reject the interchange when such
a PHI feeds the exit condition.
Fixes #202027
Added:
llvm/test/Transforms/LoopInterchange/inner-latch-lcssa-feeds-exit-condition.ll
Modified:
llvm/lib/Transforms/Scalar/LoopInterchange.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/Scalar/LoopInterchange.cpp b/llvm/lib/Transforms/Scalar/LoopInterchange.cpp
index 0268da69956bd..ca278ee565a20 100644
--- a/llvm/lib/Transforms/Scalar/LoopInterchange.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopInterchange.cpp
@@ -1451,36 +1451,46 @@ static bool areOuterLoopExitPHIsSupported(Loop *OuterLoop, Loop *InnerLoop) {
return true;
}
-// In case of multi-level nested loops, it may occur that lcssa phis exist in
-// the latch of InnerLoop, i.e., when defs of the incoming values are further
-// inside the loopnest. Sometimes those incoming values are not available
-// after interchange, since the original inner latch will become the new outer
-// latch which may have predecessor paths that do not include those incoming
-// values.
-// TODO: Handle transformation of lcssa phis in the InnerLoop latch in case of
-// multi-level loop nests.
-static bool areInnerLoopLatchPHIsSupported(Loop *OuterLoop, Loop *InnerLoop) {
+/// The transform clones the inner latch's exit condition into the new latch
+/// (see MoveInstructions in LoopInterchangeTransform::transform), but it does
+/// not relocate PHI nodes. So if a PHI in the inner latch feeds that condition,
+/// a later interchange can leave the cloned PHI with a stale incoming block,
+/// producing invalid IR. Reject that case here.
+///
+/// For example, %p is a PHI in the inner latch and the inner loop's exit test
+/// reads %p, so %p feeds the condition that would be cloned:
+///
+/// inner.latch:
+/// %p = phi i64 [ %v, %subloop.latch ]
+/// %ec = icmp eq i64 %iv, %p ; inner exit test reads %p
+/// br i1 %ec, label %exit, label %inner.header
+///
+/// TODO: Handle transformation of lcssa phis in the InnerLoop latch in case of
+/// multi-level loop nests.
+static bool areInnerLoopLatchPHIsSupported(Loop *InnerLoop) {
if (InnerLoop->getSubLoops().empty())
return true;
- // If the original outer latch has only one predecessor, then values defined
- // further inside the looploop, e.g., in the innermost loop, will be available
- // at the new outer latch after interchange.
- if (OuterLoop->getLoopLatch()->getUniquePredecessor() != nullptr)
- return true;
- // The outer latch has more than one predecessors, i.e., the inner
- // exit and the inner header.
- // PHI nodes in the inner latch are lcssa phis where the incoming values
- // are defined further inside the loopnest. Check if those phis are used
- // in the original inner latch. If that is the case then bail out since
- // those incoming values may not be available at the new outer latch.
BasicBlock *InnerLoopLatch = InnerLoop->getLoopLatch();
- for (PHINode &PHI : InnerLoopLatch->phis()) {
- for (auto *U : PHI.users()) {
- Instruction *UI = cast<Instruction>(U);
- if (InnerLoopLatch == UI->getParent())
- return false;
- }
+ auto *LatchBI = dyn_cast<CondBrInst>(InnerLoopLatch->getTerminator());
+ if (!LatchBI)
+ return true;
+ auto *CondI = dyn_cast<Instruction>(LatchBI->getCondition());
+ if (!CondI)
+ return true;
+
+ // Bail if a phi in the inner latch feeds the exit condition, walking operands
+ // within the inner loop.
+ SmallSetVector<Instruction *, 8> Worklist;
+ Worklist.insert(CondI);
+ for (unsigned I = 0; I < Worklist.size(); ++I) {
+ Instruction *Cur = Worklist[I];
+ if (isa<PHINode>(Cur) && Cur->getParent() == InnerLoopLatch)
+ return false;
+ for (Value *Op : Cur->operands())
+ if (auto *OpI = dyn_cast<Instruction>(Op))
+ if (InnerLoop->contains(OpI))
+ Worklist.insert(OpI);
}
return true;
}
@@ -1531,7 +1541,7 @@ bool LoopInterchangeLegality::canInterchangeLoops(unsigned InnerLoopId,
return false;
}
- if (!areInnerLoopLatchPHIsSupported(OuterLoop, InnerLoop)) {
+ if (!areInnerLoopLatchPHIsSupported(InnerLoop)) {
LLVM_DEBUG(dbgs() << "Found unsupported PHI nodes in inner loop latch.\n");
ORE->emit([&]() {
return OptimizationRemarkMissed(DEBUG_TYPE, "UnsupportedInnerLatchPHI",
@@ -2103,6 +2113,10 @@ bool LoopInterchangeTransform::transform(
unsigned i = 0;
auto MoveInstructions = [&i, &WorkList, this, &InductionPHIs, NewLatch]() {
for (; i < WorkList.size(); i++) {
+ // PHI nodes cannot be cloned and moved here; the legality check
+ // (areInnerLoopLatchPHIsSupported) ensures none reach the worklist.
+ assert(!isa<PHINode>(WorkList[i]) &&
+ "MoveInstructions does not support PHI nodes");
// Duplicate instruction and move it to the new latch. Update uses that
// have been moved.
Instruction *NewI = WorkList[i]->clone();
diff --git a/llvm/test/Transforms/LoopInterchange/inner-latch-lcssa-feeds-exit-condition.ll b/llvm/test/Transforms/LoopInterchange/inner-latch-lcssa-feeds-exit-condition.ll
new file mode 100644
index 0000000000000..e5c503c33367e
--- /dev/null
+++ b/llvm/test/Transforms/LoopInterchange/inner-latch-lcssa-feeds-exit-condition.ll
@@ -0,0 +1,81 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt < %s -passes=loop-interchange -loop-interchange-profitabilities=ignore \
+; RUN: -verify-dom-info -verify-loop-info -verify-loop-lcssa -S | FileCheck %s
+
+; After interchanging the innermost and the middle loop, an lcssa phi in the new
+; inner latch feeds the latch's exit condition. Interchanging the (new) middle
+; and outermost loop would clone that condition and leave the lcssa phi with a
+; stale incoming block, producing invalid IR. Make sure the second interchange
+; is rejected instead of crashing, even though the outermost latch has a single
+; predecessor.
+
+define void @t(i32 %b) {
+; CHECK-LABEL: define void @t(
+; CHECK-SAME: i32 [[B:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: br label %[[OUTER_HEADER:.*]]
+; CHECK: [[OUTER_HEADER]]:
+; CHECK-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[I_NEXT:%.*]], %[[OUTER_LATCH:.*]] ]
+; CHECK-NEXT: br label %[[INNER_HEADER_PREHEADER:.*]]
+; CHECK: [[MID_HEADER_PREHEADER:.*]]:
+; CHECK-NEXT: br label %[[MID_HEADER:.*]]
+; CHECK: [[MID_HEADER]]:
+; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[J_NEXT:%.*]], %[[MID_LATCH:.*]] ], [ 0, %[[MID_HEADER_PREHEADER]] ]
+; CHECK-NEXT: [[MWIDE:%.*]] = zext i32 [[B]] to i64
+; CHECK-NEXT: br label %[[INNER_LATCH:.*]]
+; CHECK: [[INNER_HEADER_PREHEADER]]:
+; CHECK-NEXT: br label %[[INNER_HEADER:.*]]
+; CHECK: [[INNER_HEADER]]:
+; CHECK-NEXT: [[K:%.*]] = phi i64 [ [[TMP0:%.*]], %[[INNER_LATCH_SPLIT:.*]] ], [ 0, %[[INNER_HEADER_PREHEADER]] ]
+; CHECK-NEXT: br label %[[MID_HEADER_PREHEADER]]
+; CHECK: [[INNER_LATCH]]:
+; CHECK-NEXT: [[K_NEXT:%.*]] = add nsw i64 [[K]], 1
+; CHECK-NEXT: [[EC_K:%.*]] = icmp eq i64 [[K_NEXT]], [[MWIDE]]
+; CHECK-NEXT: br label %[[MID_LATCH]]
+; CHECK: [[INNER_LATCH_SPLIT]]:
+; CHECK-NEXT: [[MWIDE_LCSSA:%.*]] = phi i64 [ [[MWIDE]], %[[MID_LATCH]] ]
+; CHECK-NEXT: [[TMP0]] = add nsw i64 [[K]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[TMP0]], [[MWIDE_LCSSA]]
+; CHECK-NEXT: br i1 [[TMP1]], label %[[OUTER_LATCH]], label %[[INNER_HEADER]]
+; CHECK: [[MID_LATCH]]:
+; CHECK-NEXT: [[J_NEXT]] = add nsw i64 [[J]], 1
+; CHECK-NEXT: [[EC_J:%.*]] = icmp eq i64 [[J_NEXT]], 100
+; CHECK-NEXT: br i1 [[EC_J]], label %[[INNER_LATCH_SPLIT]], label %[[MID_HEADER]]
+; CHECK: [[OUTER_LATCH]]:
+; CHECK-NEXT: [[I_NEXT]] = add nsw i64 [[I]], 1
+; CHECK-NEXT: [[EC_I:%.*]] = icmp eq i64 [[I_NEXT]], 100
+; CHECK-NEXT: br i1 [[EC_I]], label %[[EXIT:.*]], label %[[OUTER_HEADER]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %outer.header
+
+outer.header:
+ %i = phi i64 [ 0, %entry ], [ %i.next, %outer.latch ]
+ br label %mid.header
+
+mid.header:
+ %j = phi i64 [ 0, %outer.header ], [ %j.next, %mid.latch ]
+ %mwide = zext i32 %b to i64 ; non-induction value, middle-loop invariant
+ br label %inner.header
+
+inner.header:
+ %k = phi i64 [ 0, %mid.header ], [ %k.next, %inner.header ]
+ %k.next = add nsw i64 %k, 1
+ %ec.k = icmp eq i64 %k.next, %mwide ; inner exit uses the middle-header value
+ br i1 %ec.k, label %mid.latch, label %inner.header
+
+mid.latch:
+ %j.next = add nsw i64 %j, 1
+ %ec.j = icmp eq i64 %j.next, 100
+ br i1 %ec.j, label %outer.latch, label %mid.header
+
+outer.latch:
+ %i.next = add nsw i64 %i, 1
+ %ec.i = icmp eq i64 %i.next, 100
+ br i1 %ec.i, label %exit, label %outer.header
+
+exit:
+ ret void
+}
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