[llvm] [AMDGPU] Support global address in V/S_MOV_B64 lowering (PR #203527)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp --diff_from_common_commit
``````````

:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 94418f327..ee80b37a5 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -2100,13 +2100,13 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
     const GlobalValue *GV = SrcOp.getGlobal();
     int64_t Offset = SrcOp.getOffset();
     unsigned BaseFlags = SrcOp.getTargetFlags() &
-      ~(SIInstrInfo::MO_ABS32_LO | SIInstrInfo::MO_ABS32_HI);
+                         ~(SIInstrInfo::MO_ABS32_LO | SIInstrInfo::MO_ABS32_HI);
     BuildMI(MBB, MI, DL, get(MovOpc), DstLo)
-      .addGlobalAddress(GV, Offset, BaseFlags | SIInstrInfo::MO_ABS32_LO)
-      .addReg(Dst, RegState::Implicit | RegState::Define);
+        .addGlobalAddress(GV, Offset, BaseFlags | SIInstrInfo::MO_ABS32_LO)
+        .addReg(Dst, RegState::Implicit | RegState::Define);
     BuildMI(MBB, MI, DL, get(MovOpc), DstHi)
-      .addGlobalAddress(GV, Offset, BaseFlags | SIInstrInfo::MO_ABS32_HI)
-      .addReg(Dst, RegState::Implicit | RegState::Define);
+        .addGlobalAddress(GV, Offset, BaseFlags | SIInstrInfo::MO_ABS32_HI)
+        .addReg(Dst, RegState::Implicit | RegState::Define);
   };
 
   switch (MI.getOpcode()) {
@@ -2225,9 +2225,9 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
     assert(!SrcOp.isFPImm());
     if (ST.hasVMovB64Inst() && Mov64RC->contains(Dst)) {
       MI.setDesc(Mov64Desc);
-      if (SrcOp.isReg() ||
-          isInlineConstant(MI, 1) ||
-          (SrcOp.isImm() && (isUInt<32>(SrcOp.getImm()) || ST.has64BitLiterals())) ||
+      if (SrcOp.isReg() || isInlineConstant(MI, 1) ||
+          (SrcOp.isImm() &&
+           (isUInt<32>(SrcOp.getImm()) || ST.has64BitLiterals())) ||
           (SrcOp.isGlobal() && ST.has64BitLiterals()))
         break;
     }

``````````

</details>


https://github.com/llvm/llvm-project/pull/203527