[llvm] [AMDGPU] Accept sext addresses when folding image ops to a16 (PR #203189)

[Barbara Mitic via llvm-commits]

barbara-amd wrote:

Heads up on the relationship to #201529 
([InstCombine] Sink widening casts used only by extractelements):

This AMDGPU change stands on its own for scalar `sext i16` coordinates. The full win on packed vector coordinates needs that InstCombine PR too — it sinks the multi-use widening cast into its `extractelement` users (`extractelement(sext X)` → `sext(extractelement X)`), leaving a scalar `sext i16` per coordinate that this fold can match. End result on a 2D load:

    ; before
    v_ashrrev_i32_e32 v46, 16, v24
    v_bfe_i32         v47, v24, 0, 16
    image_load v[2:3], [v47, v46], ... d16
    ; after
    image_load v[2:3], v24, ... d16 a16

Once that PR lands, I'll need to update the test to add cases covering the combined behavior on packed vector coordinates (the 2D sext/zext example above). That can go in here before merge or as a small follow-up - whichever merges last I guess. Merge order is otherwise should be irrelevant.

https://github.com/llvm/llvm-project/pull/203189