[llvm] [AMDGPU][GISEL] Adding new reg bank select rules for G_DYN_STACKALLOC (PR #200369)

[Abhinav Garg via llvm-commits]

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@@ -1304,6 +1305,69 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI,
     }
     return true;
   }
+  case DynStackAlloc: {
+    const auto &TFI = *ST.getFrameLowering();
+    // Guard in case the stack growth direction ever changes with scratch
+    // instructions.
+    assert(TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp &&
+           "Stack grows upwards for AMDGPU");
+
+    Register Dst = MI.getOperand(0).getReg();
+    Register AllocSize = MI.getOperand(1).getReg();
+    Align Alignment = assumeAligned(MI.getOperand(2).getImm());
+
+    // After lowering Dst is used by another instruction, need to erase old MI
+    // to avoid hitting multiple Dst assert since we use CSE builder
+    B.setInsertPt(*MI.getParent(), std::next(MI.getIterator()));
+    MI.eraseFromParent();
+
+    const RegisterBank *SizeBank = MRI.getRegBank(AllocSize);
+    if (SizeBank != SgprRB) {
+      auto WaveReduction =
+          B.buildIntrinsic(Intrinsic::amdgcn_wave_reduce_umax, {SgprRB_S32})
+              .addUse(AllocSize)
+              .addImm(0);
+      AllocSize = WaveReduction.getReg(0);
+    }
+
+    LLT PtrTy = MRI.getType(Dst);
+    LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits());
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abhigargrepo wrote:

done


https://github.com/llvm/llvm-project/pull/200369