[llvm] [AMDGPU][GISEL] Adding new reg bank select rules for G_DYN_STACKALLOC (PR #200369)
Abhinav Garg via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 10 06:25:32 PDT 2026
https://github.com/abhigargrepo updated https://github.com/llvm/llvm-project/pull/200369
>From 985a53a2e66c8ab1aafcb730f9a216419295fbf0 Mon Sep 17 00:00:00 2001
From: Abhinav Garg <abhigarg at amd.com>
Date: Sat, 2 May 2026 18:25:08 +0000
Subject: [PATCH 1/3] Adding new reg bank select rules for G_DYN_STACKALLOC
---
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp | 51 ++++++++++++++++++
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 4 ++
.../AMDGPU/AMDGPURegBankLegalizeRules.h | 3 +-
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 3 ++
.../GlobalISel/dynamic-alloca-uniform.ll | 6 +--
.../AMDGPU/GlobalISel/non-entry-alloca.ll | 4 +-
.../regbankselect-dyn-stackalloc.mir | 54 +++++++++----------
llvm/test/CodeGen/AMDGPU/amdpal-callable.ll | 11 ++--
.../test/CodeGen/AMDGPU/dynamic_stackalloc.ll | 4 +-
9 files changed, 97 insertions(+), 43 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index db5573cb08cf8..88d3c2964505a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -18,6 +18,7 @@
#include "AMDGPURegBankLegalizeRules.h"
#include "AMDGPURegisterBankInfo.h"
#include "GCNSubtarget.h"
+#include "SIMachineFunctionInfo.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
@@ -1304,6 +1305,56 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI,
}
return true;
}
+ case DynStackAlloc: {
+ const auto &TFI = *ST.getFrameLowering();
+ // Guard in case the stack growth direction ever changes with scratch
+ // instructions.
+ assert(TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp &&
+ "Stack grows upwards for AMDGPU");
+
+ Register Dst = MI.getOperand(0).getReg();
+ Register AllocSize = MI.getOperand(1).getReg();
+ Align Alignment = assumeAligned(MI.getOperand(2).getImm());
+
+ // After lowering Dst is used by another instruction, need to erase old MI
+ // to avoid hitting multiple Dst assert since we use CSE builder
+ B.setInsertPt(*MI.getParent(), std::next(MI.getIterator()));
+ MI.eraseFromParent();
+
+ const RegisterBank *SizeBank = MRI.getRegBank(AllocSize);
+ if (SizeBank != SgprRB) {
+ auto WaveReduction =
+ B.buildIntrinsic(Intrinsic::amdgcn_wave_reduce_umax, {SgprRB_S32})
+ .addUse(AllocSize)
+ .addImm(0);
+ AllocSize = WaveReduction.getReg(0);
+ }
+
+ LLT PtrTy = MRI.getType(Dst);
+ LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits());
+ const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
+ Register SPReg = Info->getStackPtrOffsetReg();
+
+ auto WaveSize = B.buildConstant(SgprRB_S32, ST.getWavefrontSizeLog2());
+ auto ScaledSize = B.buildShl({SgprRB, IntPtrTy}, AllocSize, WaveSize);
+ auto OldSP = B.buildCopy({SgprRB, PtrTy}, SPReg);
+
+ if (Alignment > TFI.getStackAlign()) {
+ auto StackAlignMask =
+ (Alignment.value() << ST.getWavefrontSizeLog2()) - 1;
+ auto Tmp1 = B.buildPtrAdd({SgprRB, PtrTy}, OldSP,
+ B.buildConstant({SgprRB, IntPtrTy}, StackAlignMask));
+ auto MaskReg = B.buildConstant(
+ {SgprRB, IntPtrTy}, maskTrailingZeros<uint64_t>(Log2(Alignment) +
+ ST.getWavefrontSizeLog2()));
+ B.buildPtrMask(Dst, Tmp1, MaskReg);
+ } else {
+ B.buildCopy(Dst, OldSP);
+ }
+ auto PtrAdd = B.buildPtrAdd({SgprRB, PtrTy}, Dst, ScaledSize);
+ B.buildCopy(SPReg, PtrAdd);
+ break;
+ }
case WidenLoad: {
LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
if (DstTy == S96)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index e5bab2bbdfa25..1cb21271509d9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1287,6 +1287,10 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Any({{UniP3}, {{SgprP3}, {SgprP3, Sgpr32}}})
.Any({{DivP3}, {{VgprP3}, {VgprP3, Vgpr32}}});
+ addRulesForGOpcs({G_DYN_STACKALLOC})
+ .Any({{UniP5, UniS32}, {{SgprP5}, {Sgpr32}, DynStackAlloc}})
+ .Any({{UniP5, DivS32}, {{SgprP5}, {Vgpr32}, DynStackAlloc}});
+
addRulesForGOpcs({G_ABS}, Standard)
.Uni(S16, {{Sgpr32Trunc}, {Sgpr32SExt}})
.Div(S16, {{Vgpr16}, {Vgpr16}, AbsToNegMax})
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
index d7684d16676a0..5536d990e07ec 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
@@ -312,7 +312,8 @@ enum LoweringMethodID {
InsVecEltToSel,
InsVecEltTo32,
AbsToNegMax,
- AbsToS32
+ AbsToS32,
+ DynStackAlloc
};
enum FastRulesTypes {
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 3b72ba4bd4967..677fa64eae03c 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -10943,6 +10943,9 @@ SIInstrInfo::getGenericValueUniformity(const MachineInstr &MI) const {
if (Opcode == TargetOpcode::G_ADDRSPACE_CAST)
return HandleAddrSpaceCast(MI);
+ if (Opcode == TargetOpcode::G_DYN_STACKALLOC)
+ return ValueUniformity::AlwaysUniform;
+
if (auto *GI = dyn_cast<GIntrinsic>(&MI)) {
auto IID = GI->getIntrinsicID();
if (AMDGPU::isIntrinsicSourceOfDivergence(IID))
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
index aaff0fc4848ca..aad7c6e0c4f3f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck --check-prefix=GFX11 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck --check-prefix=GFX11 %s
@gv = external addrspace(4) constant i32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
index 8bef60523e9a7..391b07017c4a8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -amdgpu-load-store-vectorizer=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,DEFAULTSIZE %s
-; RUN: llc -global-isel -amdgpu-load-store-vectorizer=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-assume-dynamic-stack-object-size=1024 < %s | FileCheck -check-prefixes=GCN,ASSUME1024 %s
+; RUN: llc -global-isel -new-reg-bank-select -amdgpu-load-store-vectorizer=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,DEFAULTSIZE %s
+; RUN: llc -global-isel -new-reg-bank-select -amdgpu-load-store-vectorizer=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-assume-dynamic-stack-object-size=1024 < %s | FileCheck -check-prefixes=GCN,ASSUME1024 %s
; FIXME: Generated test checks do not check metadata at the end of the
; function, so this also includes manually added checks.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
index 10517a49e697c..616b0cbe3dd5e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
@@ -1,8 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=WAVE64 %s
-# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=WAVE64 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=WAVE32 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=WAVE32 %s
+# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=WAVE64 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=WAVE32 %s
---
@@ -348,20 +346,20 @@ body: |
; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_constant_align4
; WAVE64: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE64-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
- ; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
+ ; WAVE64-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 2048
; WAVE64-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY [[COPY]](p5)
- ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
+ ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[C2]](s32)
; WAVE64-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
;
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_constant_align4
; WAVE32: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE32-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
- ; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
+ ; WAVE32-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024
; WAVE32-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY [[COPY]](p5)
- ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
+ ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[C2]](s32)
; WAVE32-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
%0:_(s32) = G_CONSTANT i32 32
@@ -385,10 +383,10 @@ body: |
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE64-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
- ; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
+ ; WAVE64-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 2048
; WAVE64-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY [[COPY]](p5)
- ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
+ ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[C2]](s32)
; WAVE64-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
;
@@ -397,10 +395,10 @@ body: |
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE32-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
- ; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
+ ; WAVE32-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024
; WAVE32-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY [[COPY]](p5)
- ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
+ ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[C2]](s32)
; WAVE32-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
%0:_(s32) = G_CONSTANT i32 32
@@ -424,10 +422,10 @@ body: |
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE64-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
- ; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
+ ; WAVE64-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 2048
; WAVE64-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY [[COPY]](p5)
- ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
+ ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[C2]](s32)
; WAVE64-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
;
@@ -436,10 +434,10 @@ body: |
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE32-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
- ; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
+ ; WAVE32-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024
; WAVE32-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY [[COPY]](p5)
- ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
+ ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[C2]](s32)
; WAVE32-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
%0:_(s32) = G_CONSTANT i32 32
@@ -463,13 +461,13 @@ body: |
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE64-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
- ; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
+ ; WAVE64-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 2048
; WAVE64-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
- ; WAVE64-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 2047
- ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
- ; WAVE64-NEXT: [[C3:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -2048
- ; WAVE64-NEXT: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C3]](s32)
- ; WAVE64-NEXT: [[PTR_ADD1:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[PTRMASK]], [[SHL]](s32)
+ ; WAVE64-NEXT: [[C3:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 2047
+ ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[C3]](s32)
+ ; WAVE64-NEXT: [[C4:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -2048
+ ; WAVE64-NEXT: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C4]](s32)
+ ; WAVE64-NEXT: [[PTR_ADD1:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[PTRMASK]], [[C2]](s32)
; WAVE64-NEXT: $sp_reg = COPY [[PTR_ADD1]](p5)
; WAVE64-NEXT: S_ENDPGM 0, implicit [[PTRMASK]](p5)
;
@@ -478,13 +476,13 @@ body: |
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE32-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
- ; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
+ ; WAVE32-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024
; WAVE32-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
- ; WAVE32-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1023
- ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
- ; WAVE32-NEXT: [[C3:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -1024
- ; WAVE32-NEXT: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C3]](s32)
- ; WAVE32-NEXT: [[PTR_ADD1:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[PTRMASK]], [[SHL]](s32)
+ ; WAVE32-NEXT: [[C3:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1023
+ ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[C3]](s32)
+ ; WAVE32-NEXT: [[C4:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -1024
+ ; WAVE32-NEXT: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C4]](s32)
+ ; WAVE32-NEXT: [[PTR_ADD1:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[PTRMASK]], [[C2]](s32)
; WAVE32-NEXT: $sp_reg = COPY [[PTR_ADD1]](p5)
; WAVE32-NEXT: S_ENDPGM 0, implicit [[PTRMASK]](p5)
%0:_(s32) = G_CONSTANT i32 32
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-callable.ll b/llvm/test/CodeGen/AMDGPU/amdpal-callable.ll
index ffac4b8b4c944..cd92f8f60f6c4 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal-callable.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-callable.ll
@@ -1,6 +1,6 @@
; RUN: llc -mtriple=amdgcn--amdpal -mattr=-xnack -mattr=+dx10-clamp-and-ieee-mode < %s | FileCheck -check-prefixes=GCN,SDAG,GFX8 -enable-var-scope %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -mattr=-xnack < %s | FileCheck -check-prefixes=GCN,SDAG,GFX9 -enable-var-scope %s
-; RUN: llc -global-isel -mtriple=amdgcn--amdpal -mattr=-xnack -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GISEL,GFX9 -enable-var-scope %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn--amdpal -mattr=-xnack -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GISEL,GFX9 -enable-var-scope %s
declare amdgpu_gfx float @extern_func(float) #0
declare amdgpu_gfx float @extern_func_many_args(<64 x float>) #0
@@ -142,8 +142,7 @@ attributes #0 = { nounwind }
; GCN: amdpal.pipelines:
; GCN-NEXT: - .registers:
-; SDAG-NEXT: '0x2e12 (COMPUTE_PGM_RSRC1)': 0xaf01ca{{$}}
-; GISEL-NEXT: '0x2e12 (COMPUTE_PGM_RSRC1)': 0xaf01ca{{$}}
+; GCN-NEXT: '0x2e12 (COMPUTE_PGM_RSRC1)': 0xaf01ca{{$}}
; GCN-NEXT: '0x2e13 (COMPUTE_PGM_RSRC2)': 0x8001{{$}}
; GCN-NEXT: .shader_functions:
; GCN-NEXT: dynamic_stack:
@@ -156,11 +155,9 @@ attributes #0 = { nounwind }
; GCN-NEXT: dynamic_stack_loop:
; GCN-NEXT: .backend_stack_size: 0x10{{$}}
; GCN-NEXT: .lds_size: 0{{$}}
-; SDAG-NEXT: .sgpr_count: 0x25{{$}}
-; GISEL-NEXT: .sgpr_count: 0x26{{$}}
+; GCN-NEXT: .sgpr_count: 0x25{{$}}
; GCN-NEXT: .stack_frame_size_in_bytes: 0x10{{$}}
-; SDAG-NEXT: .vgpr_count: 0x3{{$}}
-; GISEL-NEXT: .vgpr_count: 0x4{{$}}
+; GCN-NEXT: .vgpr_count: 0x3{{$}}
; GCN-NEXT: multiple_stack:
; GCN-NEXT: .backend_stack_size: 0x24{{$}}
; GCN-NEXT: .lds_size: 0{{$}}
diff --git a/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll b/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
index 560ac268a6b10..f5ad46ef68e57 100644
--- a/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
+++ b/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11-GISEL %s
define amdgpu_kernel void @test_dynamic_stackalloc_kernel_uniform(i32 %n) #0 {
; GFX9-SDAG-LABEL: test_dynamic_stackalloc_kernel_uniform:
>From 4a3b6812e8cf5e335de4e108fe277896198572ac Mon Sep 17 00:00:00 2001
From: Abhinav Garg <abhigarg at amd.com>
Date: Fri, 5 Jun 2026 05:47:23 +0000
Subject: [PATCH 2/3] Fixing ClangFormat issues and including changes from
PR#201142
---
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp | 33 +++++++++++++------
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 3 --
2 files changed, 23 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 88d3c2964505a..d40333c3a48ad 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -1335,23 +1335,36 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI,
const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
Register SPReg = Info->getStackPtrOffsetReg();
- auto WaveSize = B.buildConstant(SgprRB_S32, ST.getWavefrontSizeLog2());
- auto ScaledSize = B.buildShl({SgprRB, IntPtrTy}, AllocSize, WaveSize);
+ // When using flat-scratch, the stack offset is unscaled.
+ const bool HasFlatScratch = ST.hasFlatScratchEnabled();
+ const unsigned WavefrontSizeLog2 = ST.getWavefrontSizeLog2();
+
+ Register AdjustedSize = AllocSize;
+ if (!HasFlatScratch) {
+ auto WaveSize = B.buildConstant(SgprRB_S32, WavefrontSizeLog2);
+ AdjustedSize =
+ B.buildShl({SgprRB, IntPtrTy}, AllocSize, WaveSize).getReg(0);
+ }
auto OldSP = B.buildCopy({SgprRB, PtrTy}, SPReg);
-
+
if (Alignment > TFI.getStackAlign()) {
- auto StackAlignMask =
- (Alignment.value() << ST.getWavefrontSizeLog2()) - 1;
- auto Tmp1 = B.buildPtrAdd({SgprRB, PtrTy}, OldSP,
- B.buildConstant({SgprRB, IntPtrTy}, StackAlignMask));
+ const uint64_t EffectiveAlignment =
+ HasFlatScratch ? Alignment.value()
+ : (Alignment.value() << WavefrontSizeLog2);
+ const uint64_t StackAlignMask = EffectiveAlignment - 1;
+ auto Tmp1 =
+ B.buildPtrAdd({SgprRB, PtrTy}, OldSP,
+ B.buildConstant({SgprRB, IntPtrTy}, StackAlignMask));
auto MaskReg = B.buildConstant(
- {SgprRB, IntPtrTy}, maskTrailingZeros<uint64_t>(Log2(Alignment) +
- ST.getWavefrontSizeLog2()));
+ {SgprRB, IntPtrTy},
+ maskTrailingZeros<uint64_t>(HasFlatScratch ? Log2(Alignment)
+ : Log2(Alignment) +
+ WavefrontSizeLog2));
B.buildPtrMask(Dst, Tmp1, MaskReg);
} else {
B.buildCopy(Dst, OldSP);
}
- auto PtrAdd = B.buildPtrAdd({SgprRB, PtrTy}, Dst, ScaledSize);
+ auto PtrAdd = B.buildPtrAdd({SgprRB, PtrTy}, Dst, AdjustedSize);
B.buildCopy(SPReg, PtrAdd);
break;
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 677fa64eae03c..3b72ba4bd4967 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -10943,9 +10943,6 @@ SIInstrInfo::getGenericValueUniformity(const MachineInstr &MI) const {
if (Opcode == TargetOpcode::G_ADDRSPACE_CAST)
return HandleAddrSpaceCast(MI);
- if (Opcode == TargetOpcode::G_DYN_STACKALLOC)
- return ValueUniformity::AlwaysUniform;
-
if (auto *GI = dyn_cast<GIntrinsic>(&MI)) {
auto IID = GI->getIntrinsicID();
if (AMDGPU::isIntrinsicSourceOfDivergence(IID))
>From 80fb849b5d41bb61434ad9d36651189e1a1d4bd5 Mon Sep 17 00:00:00 2001
From: Abhinav Garg <abhigarg at amd.com>
Date: Wed, 10 Jun 2026 13:14:24 +0000
Subject: [PATCH 3/3] Addressing minor comments
---
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp | 36 +++----
.../regbankselect-dyn-stackalloc.mir | 100 +++++++-----------
2 files changed, 54 insertions(+), 82 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index d40333c3a48ad..bab85bfb3ff67 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -18,8 +18,8 @@
#include "AMDGPURegBankLegalizeRules.h"
#include "AMDGPURegisterBankInfo.h"
#include "GCNSubtarget.h"
-#include "SIMachineFunctionInfo.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
+#include "SIMachineFunctionInfo.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
@@ -1316,13 +1316,12 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI,
Register AllocSize = MI.getOperand(1).getReg();
Align Alignment = assumeAligned(MI.getOperand(2).getImm());
- // After lowering Dst is used by another instruction, need to erase old MI
- // to avoid hitting multiple Dst assert since we use CSE builder
+ // Erase before building new instrs to avoid hitting multiple Dst assert
+ // with CSE.
B.setInsertPt(*MI.getParent(), std::next(MI.getIterator()));
MI.eraseFromParent();
- const RegisterBank *SizeBank = MRI.getRegBank(AllocSize);
- if (SizeBank != SgprRB) {
+ if (MRI.getRegBank(AllocSize) != SgprRB) {
auto WaveReduction =
B.buildIntrinsic(Intrinsic::amdgcn_wave_reduce_umax, {SgprRB_S32})
.addUse(AllocSize)
@@ -1331,7 +1330,8 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI,
}
LLT PtrTy = MRI.getType(Dst);
- LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits());
+ assert(PtrTy.getSizeInBits() == 32 &&
+ "Expected 32-bit pointer for stack allocation");
const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
Register SPReg = Info->getStackPtrOffsetReg();
@@ -1342,31 +1342,23 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI,
Register AdjustedSize = AllocSize;
if (!HasFlatScratch) {
auto WaveSize = B.buildConstant(SgprRB_S32, WavefrontSizeLog2);
- AdjustedSize =
- B.buildShl({SgprRB, IntPtrTy}, AllocSize, WaveSize).getReg(0);
+ AdjustedSize = B.buildShl(SgprRB_S32, AllocSize, WaveSize).getReg(0);
}
- auto OldSP = B.buildCopy({SgprRB, PtrTy}, SPReg);
-
if (Alignment > TFI.getStackAlign()) {
const uint64_t EffectiveAlignment =
- HasFlatScratch ? Alignment.value()
- : (Alignment.value() << WavefrontSizeLog2);
- const uint64_t StackAlignMask = EffectiveAlignment - 1;
+ Alignment.value() << (HasFlatScratch ? 0 : WavefrontSizeLog2);
+ auto OldSP = B.buildCopy({SgprRB, PtrTy}, SPReg);
auto Tmp1 =
B.buildPtrAdd({SgprRB, PtrTy}, OldSP,
- B.buildConstant({SgprRB, IntPtrTy}, StackAlignMask));
- auto MaskReg = B.buildConstant(
- {SgprRB, IntPtrTy},
- maskTrailingZeros<uint64_t>(HasFlatScratch ? Log2(Alignment)
- : Log2(Alignment) +
- WavefrontSizeLog2));
- B.buildPtrMask(Dst, Tmp1, MaskReg);
+ B.buildConstant(SgprRB_S32, EffectiveAlignment - 1));
+ uint64_t Mask = maskTrailingZeros<uint64_t>(Log2_64(EffectiveAlignment));
+ B.buildPtrMask(Dst, Tmp1, B.buildConstant(SgprRB_S32, Mask));
} else {
- B.buildCopy(Dst, OldSP);
+ B.buildCopy(Dst, SPReg);
}
auto PtrAdd = B.buildPtrAdd({SgprRB, PtrTy}, Dst, AdjustedSize);
B.buildCopy(SPReg, PtrAdd);
- break;
+ return true;
}
case WidenLoad: {
LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
index 616b0cbe3dd5e..1416b0bc5d4ba 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
@@ -21,10 +21,9 @@ body: |
; WAVE64-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
- ; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sgpr(p5) = COPY [[COPY1]](p5)
- ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY2]], [[SHL]](s32)
+ ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE64-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
- ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY2]](p5)
+ ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
;
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_align1
; WAVE32: liveins: $sgpr0
@@ -33,10 +32,9 @@ body: |
; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
- ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sgpr(p5) = COPY [[COPY1]](p5)
- ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY2]], [[SHL]](s32)
+ ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE32-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
- ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY2]](p5)
+ ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
%0:_(s32) = COPY $sgpr0
%1:_(p5) = G_DYN_STACKALLOC %0, 1
S_ENDPGM 0, implicit %1
@@ -60,10 +58,9 @@ body: |
; WAVE64-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
- ; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sgpr(p5) = COPY [[COPY1]](p5)
- ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY2]], [[SHL]](s32)
+ ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE64-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
- ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY2]](p5)
+ ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
;
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_align2
; WAVE32: liveins: $sgpr0
@@ -72,10 +69,9 @@ body: |
; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
- ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sgpr(p5) = COPY [[COPY1]](p5)
- ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY2]], [[SHL]](s32)
+ ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE32-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
- ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY2]](p5)
+ ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
%0:_(s32) = COPY $sgpr0
%1:_(p5) = G_DYN_STACKALLOC %0, 2
S_ENDPGM 0, implicit %1
@@ -99,10 +95,9 @@ body: |
; WAVE64-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
- ; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sgpr(p5) = COPY [[COPY1]](p5)
- ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY2]], [[SHL]](s32)
+ ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE64-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
- ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY2]](p5)
+ ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
;
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_align4
; WAVE32: liveins: $sgpr0
@@ -111,10 +106,9 @@ body: |
; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
- ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sgpr(p5) = COPY [[COPY1]](p5)
- ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY2]], [[SHL]](s32)
+ ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE32-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
- ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY2]](p5)
+ ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
%0:_(s32) = COPY $sgpr0
%1:_(p5) = G_DYN_STACKALLOC %0, 4
S_ENDPGM 0, implicit %1
@@ -138,10 +132,9 @@ body: |
; WAVE64-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
- ; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sgpr(p5) = COPY [[COPY1]](p5)
- ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY2]], [[SHL]](s32)
+ ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE64-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
- ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY2]](p5)
+ ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
;
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_align8
; WAVE32: liveins: $sgpr0
@@ -150,10 +143,9 @@ body: |
; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
- ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sgpr(p5) = COPY [[COPY1]](p5)
- ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY2]], [[SHL]](s32)
+ ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE32-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
- ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY2]](p5)
+ ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
%0:_(s32) = COPY $sgpr0
%1:_(p5) = G_DYN_STACKALLOC %0, 8
S_ENDPGM 0, implicit %1
@@ -177,10 +169,9 @@ body: |
; WAVE64-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
- ; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sgpr(p5) = COPY [[COPY1]](p5)
- ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY2]], [[SHL]](s32)
+ ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE64-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
- ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY2]](p5)
+ ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
;
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_align16
; WAVE32: liveins: $sgpr0
@@ -189,10 +180,9 @@ body: |
; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
- ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sgpr(p5) = COPY [[COPY1]](p5)
- ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY2]], [[SHL]](s32)
+ ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE32-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
- ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY2]](p5)
+ ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
%0:_(s32) = COPY $sgpr0
%1:_(p5) = G_DYN_STACKALLOC %0, 16
S_ENDPGM 0, implicit %1
@@ -348,20 +338,18 @@ body: |
; WAVE64-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 2048
; WAVE64-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
- ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY [[COPY]](p5)
- ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[C2]](s32)
+ ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; WAVE64-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
- ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
+ ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY]](p5)
;
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_constant_align4
; WAVE32: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE32-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024
; WAVE32-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
- ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY [[COPY]](p5)
- ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[C2]](s32)
+ ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; WAVE32-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
- ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
+ ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY]](p5)
%0:_(s32) = G_CONSTANT i32 32
%1:_(p5) = G_DYN_STACKALLOC %0, 4
S_ENDPGM 0, implicit %1
@@ -385,10 +373,9 @@ body: |
; WAVE64-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 2048
; WAVE64-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
- ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY [[COPY]](p5)
- ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[C2]](s32)
+ ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; WAVE64-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
- ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
+ ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY]](p5)
;
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_constant_align8
; WAVE32: liveins: $sgpr0
@@ -397,10 +384,9 @@ body: |
; WAVE32-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024
; WAVE32-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
- ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY [[COPY]](p5)
- ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[C2]](s32)
+ ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; WAVE32-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
- ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
+ ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY]](p5)
%0:_(s32) = G_CONSTANT i32 32
%1:_(p5) = G_DYN_STACKALLOC %0, 8
S_ENDPGM 0, implicit %1
@@ -424,10 +410,9 @@ body: |
; WAVE64-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 2048
; WAVE64-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
- ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY [[COPY]](p5)
- ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[C2]](s32)
+ ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; WAVE64-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
- ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
+ ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY]](p5)
;
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_constant_align16
; WAVE32: liveins: $sgpr0
@@ -436,10 +421,9 @@ body: |
; WAVE32-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024
; WAVE32-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
- ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY [[COPY]](p5)
- ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[C2]](s32)
+ ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; WAVE32-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
- ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
+ ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY]](p5)
%0:_(s32) = G_CONSTANT i32 32
%1:_(p5) = G_DYN_STACKALLOC %0, 16
S_ENDPGM 0, implicit %1
@@ -509,10 +493,9 @@ body: |
; WAVE64-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[INTRINSIC_CONVERGENT]], [[C]](s32)
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
- ; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sgpr(p5) = COPY [[COPY1]](p5)
- ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY2]], [[SHL]](s32)
+ ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE64-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
- ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY2]](p5)
+ ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
;
; WAVE32-LABEL: name: test_dyn_stackalloc_vgpr_align4
; WAVE32: liveins: $vgpr0
@@ -522,10 +505,9 @@ body: |
; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[INTRINSIC_CONVERGENT]], [[C]](s32)
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
- ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sgpr(p5) = COPY [[COPY1]](p5)
- ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY2]], [[SHL]](s32)
+ ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE32-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
- ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY2]](p5)
+ ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
%0:_(s32) = COPY $vgpr0
%1:_(p5) = G_DYN_STACKALLOC %0, 4
S_ENDPGM 0, implicit %1
@@ -550,10 +532,9 @@ body: |
; WAVE64-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[INTRINSIC_CONVERGENT]], [[C]](s32)
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
- ; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sgpr(p5) = COPY [[COPY1]](p5)
- ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY2]], [[SHL]](s32)
+ ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE64-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
- ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY2]](p5)
+ ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
;
; WAVE32-LABEL: name: test_dyn_stackalloc_vgpr_align16
; WAVE32: liveins: $vgpr0
@@ -563,10 +544,9 @@ body: |
; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[INTRINSIC_CONVERGENT]], [[C]](s32)
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
- ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sgpr(p5) = COPY [[COPY1]](p5)
- ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY2]], [[SHL]](s32)
+ ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE32-NEXT: $sp_reg = COPY [[PTR_ADD]](p5)
- ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY2]](p5)
+ ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY1]](p5)
%0:_(s32) = COPY $vgpr0
%1:_(p5) = G_DYN_STACKALLOC %0, 16
S_ENDPGM 0, implicit %1
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