[llvm] [X86] Reuse AND flags for redundant TEST with known SF (PR #202918)

[Phoebe Wang via llvm-commits]

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@@ -1027,22 +1027,80 @@ inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
   return ShAmt < 4 && ShAmt > 0;
 }
 
+static std::optional<APInt> getANDImmediateMask(const MachineInstr &MI) {
+  unsigned BitWidth;
+  switch (MI.getOpcode()) {
+  default:
+    return std::nullopt;
+  case X86::AND8ri:
+  case X86::AND8ri_ND:
+    BitWidth = 8;
+    break;
+  case X86::AND16ri:
+  case X86::AND16ri_ND:
+    BitWidth = 16;
+    break;
+  case X86::AND32ri:
+  case X86::AND32ri_ND:
+    BitWidth = 32;
+    break;
+  case X86::AND64ri32:
+  case X86::AND64ri32_ND:
+    BitWidth = 64;
+    break;
+  }
+
+  for (const MachineOperand &MO : MI.explicit_operands()) {
+    if (!MO.isImm())
+      continue;
+    int64_t Imm = MO.getImm();
+    if (BitWidth == 64)
+      Imm = SignExtend64<32>(Imm);
+    return APInt(BitWidth, Imm, /*isSigned=*/true);
+  }
+
+  return std::nullopt;
+}
+
+static bool clearsSignBit(const std::optional<APInt> &Mask, unsigned BitWidth) {
+  if (!Mask)
+    return false;
+  assert(Mask->getBitWidth() >= BitWidth && "Unexpected mask width");
+  return !Mask->trunc(BitWidth).isSignBitSet();
+}
+
+static unsigned getTESTrrBitWidth(unsigned Opcode) {
+  switch (Opcode) {
+  default:
+    return 0;
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phoebewang wrote:

TEST32rr will return 0?

https://github.com/llvm/llvm-project/pull/202918