[llvm] [AArch64] Reserve `W30_HI` and `[BHSDQ]31_HI` (PR #202929)

[Nathan Corbyn via llvm-commits]

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@@ -499,22 +499,22 @@ AArch64RegisterInfo::getStrictlyReservedRegs(const MachineFunction &MF) const {
   Reserved.set(AArch64::WZR_HI);
   static_assert(AArch64::W30_HI - AArch64::W0_HI == 30,
                 "Unexpected order of registers");
-  Reserved.set(AArch64::W0_HI, AArch64::W30_HI);
+  Reserved.set(AArch64::W0_HI, AArch64::W30_HI + 1);
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cofibrant wrote:

As in, this piece of code was originally reserving `W0_HI`, `W1_HI`, ..., `W29_HI` but failing to reserve `W30_HI` because of an off-by-one (`Reserved.set()` uses an exclusive upper bound). None of these registers are aliases of one another, though, so I'm not sure I understand what you mean.

https://github.com/llvm/llvm-project/pull/202929