[llvm] [AArch64] Reserve `W30_HI` and `[BHSDQ]31_HI` (PR #202929)

[Matt Arsenault via llvm-commits]

================
@@ -499,22 +499,22 @@ AArch64RegisterInfo::getStrictlyReservedRegs(const MachineFunction &MF) const {
   Reserved.set(AArch64::WZR_HI);
   static_assert(AArch64::W30_HI - AArch64::W0_HI == 30,
                 "Unexpected order of registers");
-  Reserved.set(AArch64::W0_HI, AArch64::W30_HI);
+  Reserved.set(AArch64::W0_HI, AArch64::W30_HI + 1);
----------------
arsenm wrote:

I don't understand this, it's relying on enum math. Should this just be reserving all MCRegAliasIterator

https://github.com/llvm/llvm-project/pull/202929