[llvm] [AMDGPU][GlobalIsel] Adding new reg bank rules for amdgcn_s_quadmask, amdgcn_s_wqm (PR #201898)

[Chinmay Deshpande via llvm-commits]

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@@ -1744,6 +1744,12 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
   addRulesForIOpcs({amdgcn_readlane}, StandardB)
       .Uni(B32, {{SgprB32}, {IntrId, VgprB32, SgprB32_ReadFirstLane}});
 
+  addRulesForIOpcs({amdgcn_s_quadmask, amdgcn_s_wqm}, StandardB)
+      .Uni(B32, {{SgprB32}, {IntrId, SgprB32}})
+      .Div(B32, {{Sgpr32ToVgprDst}, {IntrId, SgprB32_ReadFirstLane}})
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chinmaydd wrote:

I think you are right. Result for either intrinsic is exclusively uniform.

Would something like https://github.com/llvm/llvm-project/pull/202704 work ?

https://github.com/llvm/llvm-project/pull/201898