[llvm] [AMDGPU][GlobalIsel] Adding new reg bank rules for amdgcn_s_quadmask, amdgcn_s_wqm (PR #201898)

[Petar Avramovic via llvm-commits]

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@@ -1744,6 +1744,12 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
   addRulesForIOpcs({amdgcn_readlane}, StandardB)
       .Uni(B32, {{SgprB32}, {IntrId, VgprB32, SgprB32_ReadFirstLane}});
 
+  addRulesForIOpcs({amdgcn_s_quadmask, amdgcn_s_wqm}, StandardB)
+      .Uni(B32, {{SgprB32}, {IntrId, SgprB32}})
+      .Div(B32, {{Sgpr32ToVgprDst}, {IntrId, SgprB32_ReadFirstLane}})
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petar-avramovic wrote:

I am suspecting that this is not correct, it should be always uniform most probably.
@OutOfCache any comment?

https://github.com/llvm/llvm-project/pull/201898