[llvm] [VirtRegMap] Coarsen lane mask when `getCoveringSubRegIndexes` fails (PR #201550)

[Igor Wodiany via llvm-commits]

================
@@ -698,14 +698,35 @@ void VirtRegRewriter::rewrite() {
                                                           PhysReg, MI);
                 if (LiveOutUndefLanes.any()) {
                   SmallVector<unsigned, 16> CoveringIndexes;
+                  const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
 
                   // TODO: Just use one super register def if none of the lanes
                   // are needed?
-                  if (!TRI->getCoveringSubRegIndexes(MRI->getRegClass(VirtReg),
-                                                     LiveOutUndefLanes,
-                                                     CoveringIndexes))
-                    llvm_unreachable(
-                        "cannot represent required subregister defs");
+                  if (!TRI->getCoveringSubRegIndexes(RC, LiveOutUndefLanes,
+                                                     CoveringIndexes)) {
+                    // LiveOutUndefLanes may contain bits at finer granularity
----------------
IgWod wrote:

You're right I don't think it's sound. I also think I misunderstood exactly what the function does. It's a weird problem. The code in question is:

```
16B            %37:sreg_64 = S_MOV_B64_IMM_PSEUDO 1900
...
80B          bb.1.while.body.i.i.i.i384.i.i.i:
...
96B            %1:sreg_64 = COPY %37:sreg_64
...
448B           undef %37.sub0:sreg_64 = S_AND_B32 %21:sreg_32, 2047, implicit-def dead $scc
```

It seems what happens is `LiveOutUndefLanes` ends up with `sub1_hi16` that is not a valid sub-register for SGPR with hi16 removed and that's why `getCoveringSubRegIndexes fails`. I think it this case we don't have to cover `sub1` at all, so coarsening approach is wrong. The problem is dealing with `sub1_hi16` that shouldn't be there.


https://github.com/llvm/llvm-project/pull/201550