[llvm] [VirtRegMap] Coarsen lane mask when `getCoveringSubRegIndexes` fails (PR #201550)

[Matt Arsenault via llvm-commits]

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@@ -698,14 +698,35 @@ void VirtRegRewriter::rewrite() {
                                                           PhysReg, MI);
                 if (LiveOutUndefLanes.any()) {
                   SmallVector<unsigned, 16> CoveringIndexes;
+                  const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
 
                   // TODO: Just use one super register def if none of the lanes
                   // are needed?
-                  if (!TRI->getCoveringSubRegIndexes(MRI->getRegClass(VirtReg),
-                                                     LiveOutUndefLanes,
-                                                     CoveringIndexes))
-                    llvm_unreachable(
-                        "cannot represent required subregister defs");
+                  if (!TRI->getCoveringSubRegIndexes(RC, LiveOutUndefLanes,
+                                                     CoveringIndexes)) {
+                    // LiveOutUndefLanes may contain bits at finer granularity
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arsenm wrote:

getCoveringSubRegs should do this of you. You should not need to figure out a fallback and try again.

I'm also not sure this is correct. If there's a live value in the low half, you aren't free to clobber it to perform this copy

https://github.com/llvm/llvm-project/pull/201550