[llvm] [AMDGPU] Remove definition of hi16 for scalar registers (PR #197467)
Igor Wodiany via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 2 03:10:04 PDT 2026
https://github.com/IgWod updated https://github.com/llvm/llvm-project/pull/197467
>From 44f8e60802716801d007a2765eba5d550e8a929e Mon Sep 17 00:00:00 2001
From: Igor Wodiany <igor.wodiany at amd.com>
Date: Mon, 13 Apr 2026 11:39:43 +0100
Subject: [PATCH 1/9] [AMDGPU] Remove definition of hi16 for scalar registers
The sub-register is not supported by the backend pipelines and will
eventually cause an assert. With this change machine verifier can
enforce that hi16 is not being used.
This is a follow up change on #188781.
Assisted-by: Claude Code
---
.../AMDGPU/AMDGPUInstructionSelector.cpp | 13 +++--
llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 8 ++-
.../branch-folding-implicit-def-subreg.ll | 2 +-
.../AMDGPU/branch-relax-indirect-branch.mir | 2 +-
.../AMDGPU/branch-relax-no-terminators.mir | 2 +-
llvm/test/CodeGen/AMDGPU/ipra-regmask.ll | 4 +-
.../AMDGPU/materialize-frame-index-sgpr.ll | 48 ++++++++--------
.../test/CodeGen/AMDGPU/peephole-fold-imm.mir | 57 -------------------
.../CodeGen/AMDGPU/phys-partial-liveness.mir | 8 +--
llvm/test/CodeGen/AMDGPU/wqm.ll | 1 -
10 files changed, 44 insertions(+), 101 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 463b8c40350b2..d3c8cefccf644 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -849,7 +849,8 @@ bool AMDGPUInstructionSelector::selectG_UNMERGE_VALUES(MachineInstr &MI) const {
ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SrcRC, DstSize / 8);
for (int I = 0, E = NumDst; I != E; ++I) {
MachineOperand &Dst = MI.getOperand(I);
- // hi16:sreg_32 is not allowed so explicitly shift upper 16-bits.
+ // SGPRs do not support hi16 subregister, so extract upper 16-bits with a
+ // shift and skip the subclass constraint step.
if (SrcBank->getID() == AMDGPU::SGPRRegBankID &&
SubRegs[I] == AMDGPU::hi16) {
BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_LSHR_B32), Dst.getReg())
@@ -858,12 +859,12 @@ bool AMDGPUInstructionSelector::selectG_UNMERGE_VALUES(MachineInstr &MI) const {
} else {
BuildMI(*BB, &MI, DL, TII.get(TargetOpcode::COPY), Dst.getReg())
.addReg(SrcReg, {}, SubRegs[I]);
- }
- // Make sure the subregister index is valid for the source register.
- SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubRegs[I]);
- if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))
- return false;
+ // Make sure the subregister index is valid for the source register.
+ SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubRegs[I]);
+ if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))
+ return false;
+ }
const TargetRegisterClass *DstRC =
TRI.getConstrainedRegClassForOperand(Dst, *MRI);
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
index a0a7fb62f9159..ff42d40fdbb50 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -143,11 +143,13 @@ multiclass SIRegLoHi16 <string n, bits<10> regIdx, bit ArtificialHigh = 1,
/* isHi16 */ 1> {
let isArtificial = ArtificialHigh;
}
- def "" : RegisterWithSubRegs<n, [!cast<Register>(NAME#"_LO16"),
- !cast<Register>(NAME#"_HI16")]>,
+ def "" : RegisterWithSubRegs<n, !if(!not(ArtificialHigh),
+ [!cast<Register>(NAME#"_LO16"),
+ !cast<Register>(NAME#"_HI16")],
+ [!cast<Register>(NAME#"_LO16")])>,
DwarfRegNum<DwarfEncodings> {
let Namespace = "AMDGPU";
- let SubRegIndices = [lo16, hi16];
+ let SubRegIndices = !if(!not(ArtificialHigh), [lo16, hi16], [lo16]);
let CoveredBySubRegs = !not(ArtificialHigh);
let HWEncoding{9-0} = regIdx;
diff --git a/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll b/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
index f9c7186831ee7..c03b778b92b4e 100644
--- a/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
@@ -572,7 +572,7 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.44:
; GFX90A-NEXT: successors: %bb.45(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr57, $vgpr62, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8, $sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $vgpr40, $vgpr61, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr20_sgpr21_sgpr22, $sgpr22_sgpr23, $sgpr24_sgpr25_sgpr26, $sgpr26_sgpr27, $vgpr56, $vgpr47, $vgpr2, $vgpr4, $vgpr5, $vgpr6, $vgpr46, $vgpr45, $vgpr44, $vgpr43, $vgpr42, $vgpr41, $vgpr58, $vgpr60, $vgpr63, $vgpr59
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr57, $vgpr62, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8, $sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $vgpr40, $vgpr61, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr20_sgpr21_sgpr22, $sgpr22_sgpr23, $sgpr24_sgpr25_sgpr26, $sgpr26_sgpr27, $vgpr47, $vgpr56, $vgpr2, $vgpr4, $vgpr5, $vgpr6, $vgpr45, $vgpr46, $vgpr43, $vgpr44, $vgpr41, $vgpr42, $vgpr58, $vgpr60, $vgpr63, $vgpr59
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr52_sgpr53 = COPY renamable $sgpr36_sgpr37
; GFX90A-NEXT: renamable $vgpr12_vgpr13 = IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir b/llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
index 45af2d557da1f..d00ead75b5589 100644
--- a/llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
+++ b/llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
@@ -99,7 +99,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.6:
; CHECK-NEXT: successors: %bb.4(0x80000000)
- ; CHECK-NEXT: liveins: $vcc_hi, $vcc_lo, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $sgpr96, $sgpr97, $sgpr98, $sgpr99, $sgpr100, $sgpr101, $vgpr0, $vgpr1, $vgpr2, $sgpr33
+ ; CHECK-NEXT: liveins: $vcc_hi, $vcc_lo, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $sgpr96, $sgpr97, $sgpr98, $sgpr99, $sgpr100, $sgpr101, $vgpr0, $vgpr1, $sgpr33, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $sgpr0 = V_READLANE_B32 $vgpr2, 0, implicit-def $sgpr0_sgpr1
; CHECK-NEXT: $sgpr1 = V_READLANE_B32 killed $vgpr2, 1
diff --git a/llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir b/llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
index b1d90e2cdcb95..efb41f4d24013 100644
--- a/llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
+++ b/llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
@@ -101,7 +101,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.6:
; CHECK-NEXT: successors: %bb.4(0x80000000)
- ; CHECK-NEXT: liveins: $vcc_hi, $vcc_lo, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $sgpr96, $sgpr97, $sgpr98, $sgpr99, $sgpr100, $sgpr101, $vgpr0, $vgpr1, $vgpr2, $sgpr33
+ ; CHECK-NEXT: liveins: $vcc_hi, $vcc_lo, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $sgpr96, $sgpr97, $sgpr98, $sgpr99, $sgpr100, $sgpr101, $vgpr0, $vgpr1, $sgpr33, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $sgpr0 = V_READLANE_B32 $vgpr2, 0, implicit-def $sgpr0_sgpr1
; CHECK-NEXT: $sgpr1 = V_READLANE_B32 killed $vgpr2, 1
diff --git a/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll b/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
index 283ebc30bf939..bd0f1c296cd42 100644
--- a/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
+++ b/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
@@ -31,13 +31,13 @@ define void @nothing() #0 {
ret void
}
-; CHECK-DAG: special_regs Clobbered Registers: $scc $m0 $m0_hi16 $m0_lo16 {{$}}
+; CHECK-DAG: special_regs Clobbered Registers: $scc $m0 $m0_lo16 {{$}}
define void @special_regs() #0 {
call void asm sideeffect "", "~{m0},~{scc}"() #0
ret void
}
-; CHECK-DAG: vcc Clobbered Registers: $vcc $vcc_hi $vcc_lo $vcc_hi_hi16 $vcc_hi_lo16 $vcc_lo_hi16 $vcc_lo_lo16 $sgpr76_1024 $sgpr92_512 $sgpr96_352 $sgpr96_384 $sgpr100_224 $sgpr100_256 $sgpr104_96 $sgpr104_128 {{$}}
+; CHECK-DAG: vcc Clobbered Registers: $vcc $vcc_hi $vcc_lo $vcc_hi_lo16 $vcc_lo_lo16 $sgpr76_1024 $sgpr92_512 $sgpr96_352 $sgpr96_384 $sgpr100_224 $sgpr100_256 $sgpr104_96 $sgpr104_128 {{$}}
define void @vcc() #0 {
call void asm sideeffect "", "~{vcc}"() #0
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll b/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
index edf020cce0fcc..52bdbb725dd00 100644
--- a/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
@@ -1136,37 +1136,39 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX7-NEXT: s_mov_b64 exec, s[4:5]
; GFX7-NEXT: v_writelane_b32 v23, s28, 17
; GFX7-NEXT: v_writelane_b32 v23, s29, 18
-; GFX7-NEXT: v_writelane_b32 v23, s33, 0
-; GFX7-NEXT: v_writelane_b32 v23, s34, 1
-; GFX7-NEXT: v_writelane_b32 v23, s35, 2
-; GFX7-NEXT: v_writelane_b32 v23, s36, 3
-; GFX7-NEXT: v_writelane_b32 v23, s37, 4
-; GFX7-NEXT: v_writelane_b32 v23, s38, 5
-; GFX7-NEXT: v_writelane_b32 v23, s39, 6
-; GFX7-NEXT: v_writelane_b32 v23, s48, 7
-; GFX7-NEXT: v_writelane_b32 v23, s49, 8
-; GFX7-NEXT: v_writelane_b32 v23, s50, 9
-; GFX7-NEXT: v_writelane_b32 v23, s51, 10
-; GFX7-NEXT: v_writelane_b32 v23, s52, 11
-; GFX7-NEXT: v_writelane_b32 v23, s53, 12
-; GFX7-NEXT: v_writelane_b32 v23, s54, 13
-; GFX7-NEXT: v_writelane_b32 v23, s55, 14
-; GFX7-NEXT: v_writelane_b32 v23, s30, 15
-; GFX7-NEXT: v_writelane_b32 v23, s31, 16
-; GFX7-NEXT: s_lshr_b32 s5, s32, 6
+; GFX7-NEXT: v_writelane_b32 v23, s30, 0
+; GFX7-NEXT: v_writelane_b32 v23, s31, 1
+; GFX7-NEXT: v_writelane_b32 v23, s33, 2
+; GFX7-NEXT: v_writelane_b32 v23, s34, 3
+; GFX7-NEXT: v_writelane_b32 v23, s35, 4
+; GFX7-NEXT: v_writelane_b32 v23, s36, 5
+; GFX7-NEXT: v_writelane_b32 v23, s37, 6
+; GFX7-NEXT: v_writelane_b32 v23, s38, 7
+; GFX7-NEXT: v_writelane_b32 v23, s39, 8
+; GFX7-NEXT: v_writelane_b32 v23, s48, 9
+; GFX7-NEXT: v_writelane_b32 v23, s49, 10
+; GFX7-NEXT: v_writelane_b32 v23, s50, 11
+; GFX7-NEXT: v_writelane_b32 v23, s51, 12
+; GFX7-NEXT: v_writelane_b32 v23, s52, 13
+; GFX7-NEXT: v_writelane_b32 v23, s53, 14
; GFX7-NEXT: v_lshr_b32_e64 v0, s32, 6
-; GFX7-NEXT: s_add_i32 s4, s5, 0x4240
-; GFX7-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane
+; GFX7-NEXT: v_writelane_b32 v23, s54, 15
; GFX7-NEXT: v_add_i32_e32 v0, vcc, 64, v0
-; GFX7-NEXT: v_writelane_b32 v22, s4, 0
-; GFX7-NEXT: s_and_b64 s[4:5], 0, exec
+; GFX7-NEXT: v_writelane_b32 v23, s55, 16
; GFX7-NEXT: ;;#ASMSTART
; GFX7-NEXT: ; use alloca0 v0
; GFX7-NEXT: ;;#ASMEND
; GFX7-NEXT: ;;#ASMSTART
; GFX7-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc
; GFX7-NEXT: ;;#ASMEND
-; GFX7-NEXT: v_readlane_b32 s54, v22, 0
+; GFX7-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane
+; GFX7-NEXT: v_writelane_b32 v22, vcc_lo, 0
+; GFX7-NEXT: v_writelane_b32 v22, vcc_hi, 1
+; GFX7-NEXT: s_lshr_b32 vcc_lo, s32, 6
+; GFX7-NEXT: s_add_i32 s54, vcc_lo, 0x4240
+; GFX7-NEXT: s_and_b64 vcc, 0, exec
+; GFX7-NEXT: v_readlane_b32 vcc_lo, v22, 0
+; GFX7-NEXT: v_readlane_b32 vcc_hi, v22, 1
; GFX7-NEXT: ;;#ASMSTART
; GFX7-NEXT: ; use s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], v[0:15], v[16:21], vcc, s54, scc
; GFX7-NEXT: ;;#ASMEND
diff --git a/llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir b/llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir
index e4fe3b951cf98..6960172e94bd2 100644
--- a/llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir
+++ b/llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir
@@ -210,21 +210,6 @@ body: |
...
----
-name: fold_sreg_64_hi16_to_sgpr_lo16
-body: |
- bb.0:
-
- ; GCN-LABEL: name: fold_sreg_64_hi16_to_sgpr_lo16
- ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 1125912791875585
- ; GCN-NEXT: $sgpr0 = S_MOV_B32 2
- ; GCN-NEXT: SI_RETURN_TO_EPILOG $sgpr0_lo16
- %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 1125912791875585
- $sgpr0_lo16 = COPY killed %0.hi16
- SI_RETURN_TO_EPILOG $sgpr0_lo16
-
-...
-
---
name: fold_sreg_64_sub1_lo16_to_sgpr_lo16
body: |
@@ -240,21 +225,6 @@ body: |
...
----
-name: fold_sreg_64_sub1_hi16_to_sgpr_lo16
-body: |
- bb.0:
-
- ; GCN-LABEL: name: fold_sreg_64_sub1_hi16_to_sgpr_lo16
- ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 1125912791875585
- ; GCN-NEXT: $sgpr0 = S_MOV_B32 4
- ; GCN-NEXT: SI_RETURN_TO_EPILOG $sgpr0_lo16
- %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 1125912791875585
- $sgpr0_lo16 = COPY killed %0.sub1_hi16
- SI_RETURN_TO_EPILOG $sgpr0_lo16
-
-...
-
---
name: fmac_sreg_64_sub0_src0_to_fmamk
tracksRegLiveness: true
@@ -820,20 +790,6 @@ body: |
%1:sgpr_lo16 = COPY killed %0.lo16
SI_RETURN_TO_EPILOG %1
-...
----
-name: fold_simm_16_sub_to_hi_from_mov_64_inline_imm_virt_sgpr16
-body: |
- bb.0:
-
- ; GCN-LABEL: name: fold_simm_16_sub_to_hi_from_mov_64_inline_imm_virt_sgpr16
- ; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 64
- ; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr_lo16 = COPY killed [[S_MOV_B64_]].hi16
- ; GCN-NEXT: SI_RETURN_TO_EPILOG [[COPY]]
- %0:sreg_64 = S_MOV_B64 64
- %1:sgpr_lo16 = COPY killed %0.hi16
- SI_RETURN_TO_EPILOG %1
-
...
---
@@ -850,20 +806,7 @@ body: |
SI_RETURN_TO_EPILOG $sgpr0_lo16
...
----
-name: fold_simm_16_sub_to_hi_from_mov_64_inline_imm_phys_sgpr16_lo
-body: |
- bb.0:
-
- ; GCN-LABEL: name: fold_simm_16_sub_to_hi_from_mov_64_inline_imm_phys_sgpr16_lo
- ; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 64
- ; GCN-NEXT: $sgpr0 = S_MOV_B32 0
- ; GCN-NEXT: SI_RETURN_TO_EPILOG $sgpr0_lo16
- %0:sreg_64 = S_MOV_B64 64
- $sgpr0_lo16 = COPY killed %0.hi16
- SI_RETURN_TO_EPILOG $sgpr0_lo16
-...
---
# Test that foldImmediate correctly handles kill flags when eliminating
# redundant instructions. Without the fix, kill flags are not cleared when
diff --git a/llvm/test/CodeGen/AMDGPU/phys-partial-liveness.mir b/llvm/test/CodeGen/AMDGPU/phys-partial-liveness.mir
index d1cc5659f5ab5..cfdfddb421f6b 100644
--- a/llvm/test/CodeGen/AMDGPU/phys-partial-liveness.mir
+++ b/llvm/test/CodeGen/AMDGPU/phys-partial-liveness.mir
@@ -3,18 +3,14 @@
# REQUIRES: asserts
# CHECK: Computing live-in reg-units in ABI blocks.
-# CHECK: 0B %bb.0 SGPR16_LO16#0 SGPR16_HI16#0
+# CHECK: 0B %bb.0 SGPR16_LO16#0
# CHECK: SGPR16_LO16 [0B,16r:0)[32r,144r:1) 0 at 0B-phi 1 at 32r
-# CHECK: SGPR16_HI16 [0B,16r:0)[32r,144r:1) 0 at 0B-phi 1 at 32r
# CHECK: Computing live-in reg-units in ABI blocks.
-# CHECK: 0B %bb.0 SGPR2_LO16#0 SGPR2_HI16#0 SGPR3_LO16#0 SGPR3_HI16#0 SGPR7_LO16#0 SGPR7_HI16#0
+# CHECK: 0B %bb.0 SGPR2_LO16#0 SGPR3_LO16#0 SGPR7_LO16#0
# CHECK: SGPR2_LO16 [0B,64r:0) 0 at 0B-phi
-# CHECK: SGPR2_HI16 [0B,64r:0) 0 at 0B-phi
# CHECK: SGPR3_LO16 [0B,16r:0)[48r,64r:1) 0 at 0B-phi 1 at 48r
-# CHECK: SGPR3_HI16 [0B,16r:0)[48r,64r:1) 0 at 0B-phi 1 at 48r
# CHECK: SGPR7_LO16 [0B,48r:0) 0 at 0B-phi
-# CHECK: SGPR7_HI16 [0B,48r:0) 0 at 0B-phi
---
name: phys_reg_partial_liveness_1
diff --git a/llvm/test/CodeGen/AMDGPU/wqm.ll b/llvm/test/CodeGen/AMDGPU/wqm.ll
index 219a46f37f415..49a95b9cd9ceb 100644
--- a/llvm/test/CodeGen/AMDGPU/wqm.ll
+++ b/llvm/test/CodeGen/AMDGPU/wqm.ll
@@ -1474,7 +1474,6 @@ define amdgpu_ps float @test_control_flow_1(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10-W32-NEXT: .LBB28_2: ; %Flow
; GFX10-W32-NEXT: s_or_saveexec_b32 s0, s13
; GFX10-W32-NEXT: s_and_b32 exec_lo, exec_lo, s12
-; GFX10-W32-NEXT: s_and_b32 s0, exec_lo, s0
; GFX10-W32-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX10-W32-NEXT: s_cbranch_execz .LBB28_4
; GFX10-W32-NEXT: ; %bb.3: ; %ELSE
>From 6fe4a8e9605ddadfe3c89639f768cbf7f08338db Mon Sep 17 00:00:00 2001
From: Igor Wodiany <igor.wodiany at amd.com>
Date: Wed, 13 May 2026 22:01:28 +0100
Subject: [PATCH 2/9] Separate classes + asm parser
---
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 5 +-
llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 120 ++++++++++--------
.../CodeGen/AMDGPU/asm-printer-check-vcc.mir | 2 +-
llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir | 4 +-
.../resource-usage-crash-unhandled-reg.mir | 3 +-
.../AMDGPU/sched-image-sample-post-RA.mir | 6 +-
.../CodeGen/AMDGPU/set-gpr-idx-peephole.mir | 32 ++---
llvm/test/MC/AMDGPU/gfx11_asm_t16_err.s | 6 +-
8 files changed, 93 insertions(+), 85 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index c27b96adf7d04..0dc439fd8dd80 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -2997,9 +2997,8 @@ MCRegister AMDGPUAsmParser::getRegularReg(RegisterKind RegKind, unsigned RegNum,
if (SubReg) {
Reg = TRI->getSubReg(Reg, SubReg);
- // Currently all regular registers have their .l and .h subregisters, so
- // we should never need to generate an error here.
- assert(Reg && "Invalid subregister!");
+ if(!Reg)
+ Error(Loc, "invalid subregister");
}
return Reg;
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
index ff42d40fdbb50..5aa35f103fe8f 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -135,22 +135,18 @@ class SIRegisterClass <string n, list<ValueType> rTypes, int Align, dag rList>
}
-multiclass SIRegLoHi16 <string n, bits<10> regIdx, bit ArtificialHigh = 1,
- bit isVGPR = 0, bit isAGPR = 0,
- list<int> DwarfEncodings = [-1, -1]> {
+multiclass SIRegWithSubRegs<string n, bits<10> regIdx,
+ bit isVGPR, bit isAGPR,
+ list<int> DwarfEncodings,
+ list<Register> subRegs,
+ list<SubRegIndex> subRegIndices,
+ bit coveredBySubRegs> {
def _LO16 : SIReg<n#".l", regIdx, isVGPR, isAGPR>;
- def _HI16 : SIReg<!if(ArtificialHigh, "", n#".h"), regIdx, isVGPR, isAGPR,
- /* isHi16 */ 1> {
- let isArtificial = ArtificialHigh;
- }
- def "" : RegisterWithSubRegs<n, !if(!not(ArtificialHigh),
- [!cast<Register>(NAME#"_LO16"),
- !cast<Register>(NAME#"_HI16")],
- [!cast<Register>(NAME#"_LO16")])>,
+ def "" : RegisterWithSubRegs<n, subRegs>,
DwarfRegNum<DwarfEncodings> {
let Namespace = "AMDGPU";
- let SubRegIndices = !if(!not(ArtificialHigh), [lo16, hi16], [lo16]);
- let CoveredBySubRegs = !not(ArtificialHigh);
+ let SubRegIndices = subRegIndices;
+ let CoveredBySubRegs = coveredBySubRegs;
let HWEncoding{9-0} = regIdx;
let HWEncoding{10} = isVGPR;
@@ -160,9 +156,27 @@ multiclass SIRegLoHi16 <string n, bits<10> regIdx, bit ArtificialHigh = 1,
}
}
+multiclass SIRegLoHi16 <string n, bits<10> regIdx,
+ bit isVGPR = 0, bit isAGPR = 0,
+ list<int> DwarfEncodings = [-1, -1]> {
+ def _HI16 : SIReg<n#".h", regIdx, isVGPR, isAGPR, /* isHi16 */ 1>;
+ defm "" : SIRegWithSubRegs<n, regIdx, isVGPR, isAGPR, DwarfEncodings,
+ [!cast<Register>(NAME#"_LO16"),
+ !cast<Register>(NAME#"_HI16")],
+ [lo16, hi16], /* coveredBySubRegs */ 1>;
+}
+
+multiclass SIRegLo16 <string n, bits<10> regIdx,
+ bit isVGPR = 0, bit isAGPR = 0,
+ list<int> DwarfEncodings = [-1, -1]> {
+ defm "" : SIRegWithSubRegs<n, regIdx, isVGPR, isAGPR, DwarfEncodings,
+ [!cast<Register>(NAME#"_LO16")],
+ [lo16], /* coveredBySubRegs */ 0>;
+}
+
// Special Registers
-defm VCC_LO : SIRegLoHi16<"vcc_lo", 106>;
-defm VCC_HI : SIRegLoHi16<"vcc_hi", 107>;
+defm VCC_LO : SIRegLo16<"vcc_lo", 106>;
+defm VCC_HI : SIRegLo16<"vcc_hi", 107>;
// Pseudo-registers: Used as placeholders during isel and immediately
// replaced, never seeing the verifier.
@@ -186,9 +200,8 @@ def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]> {
let CoveredBySubRegs = 1;
}
-defm EXEC_LO : SIRegLoHi16<"exec_lo", 126, /*ArtificialHigh=*/1, /*isVGPR=*/0,
- /*isAGPR=*/0, /*DwarfEncodings=*/[1, 1]>;
-defm EXEC_HI : SIRegLoHi16<"exec_hi", 127>;
+defm EXEC_LO : SIRegLo16<"exec_lo", 126, /*isVGPR=*/ 0, /*isAGPR=*/0, /*DwarfEncodings=*/[1, 1]>;
+defm EXEC_HI : SIRegLo16<"exec_hi", 127>;
def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, DwarfRegNum<[17, 1]> {
let Namespace = "AMDGPU";
@@ -198,9 +211,9 @@ def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, DwarfRegNum<[17, 1]>
// 32-bit real registers, for MC only.
// May be used with both 32-bit and 64-bit operands.
-defm SRC_VCCZ : SIRegLoHi16<"src_vccz", 251>;
-defm SRC_EXECZ : SIRegLoHi16<"src_execz", 252>;
-defm SRC_SCC : SIRegLoHi16<"src_scc", 253>;
+defm SRC_VCCZ : SIRegLo16<"src_vccz", 251>;
+defm SRC_EXECZ : SIRegLo16<"src_execz", 252>;
+defm SRC_SCC : SIRegLo16<"src_scc", 253>;
// 1-bit pseudo register, for codegen only.
// Should never be emitted.
@@ -208,15 +221,15 @@ def SCC : SIReg<"scc">;
// Encoding changes between subtarget generations.
// See also Utils/AMDGPUBaseInfo.cpp MAP_REG2REG.
-defm M0_gfxpre11 : SIRegLoHi16 <"m0", 124>;
-defm M0_gfx11plus : SIRegLoHi16 <"m0", 125>;
-defm M0 : SIRegLoHi16 <"m0", 0>;
+defm M0_gfxpre11 : SIRegLo16 <"m0", 124>;
+defm M0_gfx11plus : SIRegLo16 <"m0", 125>;
+defm M0 : SIRegLo16 <"m0", 0>;
-defm SGPR_NULL_gfxpre11 : SIRegLoHi16 <"null", 125>;
-defm SGPR_NULL_gfx11plus : SIRegLoHi16 <"null", 124>;
+defm SGPR_NULL_gfxpre11 : SIRegLo16 <"null", 125>;
+defm SGPR_NULL_gfx11plus : SIRegLo16 <"null", 124>;
let isConstant = true in {
-defm SGPR_NULL : SIRegLoHi16 <"null", 0>;
-defm SGPR_NULL_HI : SIRegLoHi16 <"", 0>;
+defm SGPR_NULL : SIRegLo16 <"null", 0>;
+defm SGPR_NULL_HI : SIRegLo16 <"", 0>;
} // isConstant = true
def SGPR_NULL64 :
@@ -238,7 +251,7 @@ def SGPR_NULL64 :
// need them, we need to do a 64 bit load and extract the bits manually.
multiclass ApertureRegister<string name, bits<10> regIdx> {
let isConstant = true in {
- defm _LO : SIRegLoHi16 <name, regIdx>;
+ defm _LO : SIRegLo16 <name, regIdx>;
def "" : RegisterWithSubRegs<name, [!cast<Register>(NAME#_LO)]> {
let Namespace = "AMDGPU";
let SubRegIndices = [sub0];
@@ -254,8 +267,8 @@ defm SRC_PRIVATE_BASE : ApertureRegister<"src_private_base", 237>;
defm SRC_PRIVATE_LIMIT : ApertureRegister<"src_private_limit", 238>;
let isConstant = true in {
- defm SRC_FLAT_SCRATCH_BASE_LO : SIRegLoHi16<"src_flat_scratch_base_lo", 230>;
- defm SRC_FLAT_SCRATCH_BASE_HI : SIRegLoHi16<"src_flat_scratch_base_hi", 231>;
+ defm SRC_FLAT_SCRATCH_BASE_LO : SIRegLo16<"src_flat_scratch_base_lo", 230>;
+ defm SRC_FLAT_SCRATCH_BASE_HI : SIRegLo16<"src_flat_scratch_base_hi", 231>;
// Using src_flat_scratch_base_lo in a 64-bit context gets the full 64-bit
// hi:lo value.
@@ -269,7 +282,7 @@ let isConstant = true in {
}
}
-defm SRC_POPS_EXITING_WAVE_ID : SIRegLoHi16<"src_pops_exiting_wave_id", 239>;
+defm SRC_POPS_EXITING_WAVE_ID : SIRegLo16<"src_pops_exiting_wave_id", 239>;
// Not addressable
def MODE : SIReg <"mode", 0>;
@@ -285,8 +298,8 @@ def LDS_DIRECT : SIReg <"src_lds_direct", 254> {
let isArtificial = 1;
}
-defm XNACK_MASK_LO : SIRegLoHi16<"xnack_mask_lo", 104>;
-defm XNACK_MASK_HI : SIRegLoHi16<"xnack_mask_hi", 105>;
+defm XNACK_MASK_LO : SIRegLo16<"xnack_mask_lo", 104>;
+defm XNACK_MASK_HI : SIRegLo16<"xnack_mask_hi", 105>;
def XNACK_MASK :
RegisterWithSubRegs<"xnack_mask", [XNACK_MASK_LO, XNACK_MASK_HI]> {
@@ -296,8 +309,8 @@ def XNACK_MASK :
}
// Trap handler registers
-defm TBA_LO : SIRegLoHi16<"tba_lo", 108>;
-defm TBA_HI : SIRegLoHi16<"tba_hi", 109>;
+defm TBA_LO : SIRegLo16<"tba_lo", 108>;
+defm TBA_HI : SIRegLo16<"tba_hi", 109>;
def TBA : RegisterWithSubRegs<"tba", [TBA_LO, TBA_HI]> {
let Namespace = "AMDGPU";
@@ -305,8 +318,8 @@ def TBA : RegisterWithSubRegs<"tba", [TBA_LO, TBA_HI]> {
let HWEncoding = TBA_LO.HWEncoding;
}
-defm TMA_LO : SIRegLoHi16<"tma_lo", 110>;
-defm TMA_HI : SIRegLoHi16<"tma_hi", 111>;
+defm TMA_LO : SIRegLo16<"tma_lo", 110>;
+defm TMA_HI : SIRegLo16<"tma_hi", 111>;
def TMA : RegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]> {
let Namespace = "AMDGPU";
@@ -315,15 +328,15 @@ def TMA : RegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]> {
}
foreach Index = 0...15 in {
- defm TTMP#Index#_vi : SIRegLoHi16<"ttmp"#Index, !add(112, Index)>;
- defm TTMP#Index#_gfx9plus : SIRegLoHi16<"ttmp"#Index, !add(108, Index)>;
- defm TTMP#Index : SIRegLoHi16<"ttmp"#Index, 0>;
+ defm TTMP#Index#_vi : SIRegLo16<"ttmp"#Index, !add(112, Index)>;
+ defm TTMP#Index#_gfx9plus : SIRegLo16<"ttmp"#Index, !add(108, Index)>;
+ defm TTMP#Index : SIRegLo16<"ttmp"#Index, 0>;
}
multiclass FLAT_SCR_LOHI_m <string n, bits<10> ci_e, bits<10> vi_e> {
- defm _ci : SIRegLoHi16<n, ci_e>;
- defm _vi : SIRegLoHi16<n, vi_e>;
- defm "" : SIRegLoHi16<n, 0>;
+ defm _ci : SIRegLo16<n, ci_e>;
+ defm _vi : SIRegLo16<n, vi_e>;
+ defm "" : SIRegLo16<n, 0>;
}
class FlatReg <Register lo, Register hi, bits<16> encoding> :
@@ -343,27 +356,24 @@ def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT_SCR_HI, 0>;
// SGPR registers
foreach Index = 0...105 in {
defm SGPR#Index :
- SIRegLoHi16 <"s"#Index, Index, /*ArtificialHigh=*/1,
- /*isVGPR=*/0, /*isAGPR=*/0, /*DwarfEncodings=*/
- [!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024)),
- !if(!le(Index, 63), !add(Index, 32), !add(Index, 1024))]>;
+ SIRegLo16 <"s"#Index, Index, /*isVGPR=*/0, /*isAGPR=*/0, /*DwarfEncodings=*/
+ [!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024)),
+ !if(!le(Index, 63), !add(Index, 32), !add(Index, 1024))]>;
}
// VGPR registers
foreach Index = 0...1023 in {
defm VGPR#Index :
- SIRegLoHi16 <"v"#Index, Index, /*ArtificialHigh=*/ 0,
- /*isVGPR=*/ 1, /*isAGPR=*/ 0, /*DwarfEncodings=*/
- [!if(!le(Index, 511), !add(Index, 2560), -1),
- !if(!le(Index, 511), !add(Index, 1536), !add(Index, !sub(3584, 512)))]>;
+ SIRegLoHi16 <"v"#Index, Index, /*isVGPR=*/ 1, /*isAGPR=*/ 0, /*DwarfEncodings=*/
+ [!if(!le(Index, 511), !add(Index, 2560), -1),
+ !if(!le(Index, 511), !add(Index, 1536), !add(Index, !sub(3584, 512)))]>;
}
// AccVGPR registers
foreach Index = 0...255 in {
defm AGPR#Index :
- SIRegLoHi16 <"a"#Index, Index, /*ArtificialHigh=*/ 1,
- /*isVGPR=*/ 0, /*isAGPR=*/ 1, /*DwarfEncodings=*/
- [!add(Index, 3072), !add(Index, 2048)]>;
+ SIRegLo16 <"a"#Index, Index, /*isVGPR=*/ 0, /*isAGPR=*/ 1, /*DwarfEncodings=*/
+ [!add(Index, 3072), !add(Index, 2048)]>;
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/AMDGPU/asm-printer-check-vcc.mir b/llvm/test/CodeGen/AMDGPU/asm-printer-check-vcc.mir
index 813b2238e5446..352f17da03527 100644
--- a/llvm/test/CodeGen/AMDGPU/asm-printer-check-vcc.mir
+++ b/llvm/test/CodeGen/AMDGPU/asm-printer-check-vcc.mir
@@ -16,7 +16,7 @@ frameInfo:
hasCalls: true
body: |
bb.0:
- BUNDLE implicit-def $vcc, implicit-def $vcc_lo, implicit-def $vcc_lo_lo16, implicit-def $vcc_lo_hi16, implicit-def $vcc_hi, implicit-def $vcc_hi_lo16, implicit-def $vcc_hi_hi16, implicit-def $scc {
+ BUNDLE implicit-def $vcc, implicit-def $vcc_lo, implicit-def $vcc_lo_lo16, implicit-def $vcc_hi, implicit-def $vcc_hi_lo16, implicit-def $scc {
$vcc = S_GETPC_B64
$vcc_lo = S_ADD_U32 internal $vcc_lo, target-flags(amdgpu-rel32-lo) @bar + 4, implicit-def $scc
$vcc_hi = S_ADDC_U32 internal $vcc_hi, target-flags(amdgpu-rel32-hi) @bar + 12, implicit-def $scc, implicit internal $scc
diff --git a/llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir b/llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
index 3c1a98fac932f..8c95e64e930f7 100644
--- a/llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
+++ b/llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
@@ -1081,7 +1081,7 @@ body: |
; GCN-LABEL: name: test_call_consuming_cvt_scalef32_hazard
; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
; GCN-NEXT: {{ $}}
- ; GCN-NEXT: BUNDLE implicit-def $sgpr0_sgpr1, implicit-def $sgpr0, implicit-def $sgpr0_lo16, implicit-def $sgpr0_hi16, implicit-def $sgpr1, implicit-def $sgpr1_lo16, implicit-def $sgpr1_hi16, implicit-def $scc {
+ ; GCN-NEXT: BUNDLE implicit-def $sgpr0_sgpr1, implicit-def $sgpr0, implicit-def $sgpr0_lo16, implicit-def $sgpr1, implicit-def $sgpr1_lo16, implicit-def $scc {
; GCN-NEXT: $sgpr0_sgpr1 = S_GETPC_B64
; GCN-NEXT: $sgpr0 = S_ADD_U32 internal $sgpr0, target-flags(amdgpu-gotprel32-lo) @test_cvt_scalef32_hazard_pseudo + 4, implicit-def $scc
; GCN-NEXT: $sgpr1 = S_ADDC_U32 internal $sgpr1, target-flags(amdgpu-gotprel32-hi) @test_cvt_scalef32_hazard_pseudo + 12, implicit-def $scc, implicit internal $scc
@@ -1090,7 +1090,7 @@ body: |
; GCN-NEXT: renamable $vgpr2 = V_CVT_SCALEF32_PK_FP4_F16_e64 8, killed $vgpr0, 0, killed $vgpr1, 4, killed $vgpr2, 0, implicit $mode, implicit $exec
; GCN-NEXT: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr0_sgpr1, @test_cvt_scalef32_hazard_pseudo, csr_amdgpu_gfx90ainsts, implicit undef $sgpr4_sgpr5, implicit undef $sgpr6_sgpr7, implicit killed $sgpr8_sgpr9, implicit undef $sgpr10_sgpr11, implicit undef $sgpr12, implicit undef $sgpr13, implicit undef $sgpr14, implicit-def $sgpr15, implicit undef $vgpr31, implicit killed $vgpr2, implicit-def $vgpr2
; GCN-NEXT: SI_RETURN_TO_EPILOG killed $vgpr0
- BUNDLE implicit-def $sgpr0_sgpr1, implicit-def $sgpr0, implicit-def $sgpr0_lo16, implicit-def $sgpr0_hi16, implicit-def $sgpr1, implicit-def $sgpr1_lo16, implicit-def $sgpr1_hi16, implicit-def $scc {
+ BUNDLE implicit-def $sgpr0_sgpr1, implicit-def $sgpr0, implicit-def $sgpr0_lo16, implicit-def $sgpr1, implicit-def $sgpr1_lo16, implicit-def $scc {
$sgpr0_sgpr1 = S_GETPC_B64
$sgpr0 = S_ADD_U32 internal $sgpr0, target-flags(amdgpu-gotprel32-lo) @test_cvt_scalef32_hazard_pseudo + 4, implicit-def $scc
$sgpr1 = S_ADDC_U32 internal $sgpr1, target-flags(amdgpu-gotprel32-hi) @test_cvt_scalef32_hazard_pseudo + 12, implicit-def $scc, implicit internal $scc
diff --git a/llvm/test/CodeGen/AMDGPU/resource-usage-crash-unhandled-reg.mir b/llvm/test/CodeGen/AMDGPU/resource-usage-crash-unhandled-reg.mir
index bc185bb5156f3..66ae2da7741be 100644
--- a/llvm/test/CodeGen/AMDGPU/resource-usage-crash-unhandled-reg.mir
+++ b/llvm/test/CodeGen/AMDGPU/resource-usage-crash-unhandled-reg.mir
@@ -1,6 +1,6 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=amdgpu-resource-usage -verify-machineinstrs %s -o -
-# Checks that ResourceUsageAnalysis does not assert if it sees agpr_lo16, agpr_hi16 or TTMP regs.
+# Checks that ResourceUsageAnalysis does not assert if it sees agpr_lo16 or TTMP regs.
---
name: test
@@ -16,7 +16,6 @@ body: |
$vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8 = COPY $ttmp0_ttmp1_ttmp2_ttmp3_ttmp4_ttmp5_ttmp6_ttmp7
$vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16 = COPY $ttmp0_ttmp1_ttmp2_ttmp3_ttmp4_ttmp5_ttmp6_ttmp7_ttmp8_ttmp9_ttmp10_ttmp11_ttmp12_ttmp13_ttmp14_ttmp15
$agpr1_lo16 = IMPLICIT_DEF
- $agpr1_hi16 = IMPLICIT_DEF
$sgpr2_sgpr3 = SI_CALL undef $sgpr0_sgpr1, 0, CustomRegMask()
S_ENDPGM 0
...
diff --git a/llvm/test/CodeGen/AMDGPU/sched-image-sample-post-RA.mir b/llvm/test/CodeGen/AMDGPU/sched-image-sample-post-RA.mir
index aeb54bc080d58..8e5d1340002a6 100644
--- a/llvm/test/CodeGen/AMDGPU/sched-image-sample-post-RA.mir
+++ b/llvm/test/CodeGen/AMDGPU/sched-image-sample-post-RA.mir
@@ -29,7 +29,7 @@ body: |
; TOPDOWN-NEXT: $sgpr9 = S_MOV_B32 killed $sgpr2
; TOPDOWN-NEXT: $sgpr15 = S_MOV_B32 killed $sgpr1
; TOPDOWN-NEXT: $exec = S_MOV_B64 killed renamable $sgpr16_sgpr17
- ; TOPDOWN-NEXT: BUNDLE implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23, implicit-def $sgpr16, implicit-def $sgpr16_lo16, implicit-def $sgpr16_hi16, implicit-def $sgpr17, implicit-def $sgpr17_lo16, implicit-def $sgpr17_hi16, implicit-def $sgpr18, implicit-def $sgpr18_lo16, implicit-def $sgpr18_hi16, implicit-def $sgpr19, implicit-def $sgpr19_lo16, implicit-def $sgpr19_hi16, implicit-def $sgpr20, implicit-def $sgpr20_lo16, implicit-def $sgpr20_hi16, implicit-def $sgpr21, implicit-def $sgpr21_lo16, implicit-def $sgpr21_hi16, implicit-def $sgpr22, implicit-def $sgpr22_lo16, implicit-def $sgpr22_hi16, implicit-def $sgpr23, implicit-def $sgpr23_lo16, implicit-def $sgpr23_hi16, implicit-def $sgpr16_sgpr17, implicit-def $sgpr16_sgpr17_sgpr18, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21, implicit-def $sgpr18_sgpr19, implicit-def $sgpr20_sgpr21, implicit-def $sgpr20_sgpr21_sgpr22, implicit-def $sgpr20_sgpr21_sgpr22_sgpr23, implicit-def $sgpr22_sgpr23, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $sgpr0, implicit-def $sgpr0_lo16, implicit-def $sgpr0_hi16, implicit-def $sgpr1, implicit-def $sgpr1_lo16, implicit-def $sgpr1_hi16, implicit-def $sgpr2, implicit-def $sgpr2_lo16, implicit-def $sgpr2_hi16, implicit-def $sgpr3, implicit-def $sgpr3_lo16, implicit-def $sgpr3_hi16, implicit-def $sgpr0_sgpr1, implicit-def $sgpr0_sgpr1_sgpr2, implicit-def $sgpr2_sgpr3, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, implicit-def $sgpr24, implicit-def $sgpr24_lo16, implicit-def $sgpr24_hi16, implicit-def $sgpr25, implicit-def $sgpr25_lo16, implicit-def $sgpr25_hi16, implicit-def $sgpr26, implicit-def $sgpr26_lo16, implicit-def $sgpr26_hi16, implicit-def $sgpr27, implicit-def $sgpr27_lo16, implicit-def $sgpr27_hi16, implicit-def $sgpr28, implicit-def $sgpr28_lo16, implicit-def $sgpr28_hi16, implicit-def $sgpr29, implicit-def $sgpr29_lo16, implicit-def $sgpr29_hi16, implicit-def $sgpr30, implicit-def $sgpr30_lo16, implicit-def $sgpr30_hi16, implicit-def $sgpr31, implicit-def $sgpr31_lo16, implicit-def $sgpr31_hi16, implicit-def $sgpr24_sgpr25, implicit-def $sgpr24_sgpr25_sgpr26, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29, implicit-def $sgpr26_sgpr27, implicit-def $sgpr28_sgpr29, implicit-def $sgpr28_sgpr29_sgpr30, implicit-def $sgpr28_sgpr29_sgpr30_sgpr31, implicit-def $sgpr30_sgpr31, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30, implicit-def $sgpr36_sgpr37_sgpr38_sgpr39, implicit-def $sgpr36, implicit-def $sgpr36_lo16, implicit-def $sgpr36_hi16, implicit-def $sgpr37, implicit-def $sgpr37_lo16, implicit-def $sgpr37_hi16, implicit-def $sgpr38, implicit-def $sgpr38_lo16, implicit-def $sgpr38_hi16, implicit-def $sgpr39, implicit-def $sgpr39_lo16, implicit-def $sgpr39_hi16, implicit-def $sgpr36_sgpr37, implicit-def $sgpr36_sgpr37_sgpr38, implicit-def $sgpr38_sgpr39, implicit killed $sgpr14_sgpr15 {
+ ; TOPDOWN-NEXT: BUNDLE implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23, implicit-def $sgpr16, implicit-def $sgpr16_lo16, implicit-def $sgpr17, implicit-def $sgpr17_lo16, implicit-def $sgpr18, implicit-def $sgpr18_lo16, implicit-def $sgpr19, implicit-def $sgpr19_lo16, implicit-def $sgpr20, implicit-def $sgpr20_lo16, implicit-def $sgpr21, implicit-def $sgpr21_lo16, implicit-def $sgpr22, implicit-def $sgpr22_lo16, implicit-def $sgpr23, implicit-def $sgpr23_lo16, implicit-def $sgpr16_sgpr17, implicit-def $sgpr16_sgpr17_sgpr18, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21, implicit-def $sgpr18_sgpr19, implicit-def $sgpr20_sgpr21, implicit-def $sgpr20_sgpr21_sgpr22, implicit-def $sgpr20_sgpr21_sgpr22_sgpr23, implicit-def $sgpr22_sgpr23, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $sgpr0, implicit-def $sgpr0_lo16, implicit-def $sgpr1, implicit-def $sgpr1_lo16, implicit-def $sgpr2, implicit-def $sgpr2_lo16, implicit-def $sgpr3, implicit-def $sgpr3_lo16, implicit-def $sgpr0_sgpr1, implicit-def $sgpr0_sgpr1_sgpr2, implicit-def $sgpr2_sgpr3, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, implicit-def $sgpr24, implicit-def $sgpr24_lo16, implicit-def $sgpr25, implicit-def $sgpr25_lo16, implicit-def $sgpr26, implicit-def $sgpr26_lo16, implicit-def $sgpr27, implicit-def $sgpr27_lo16, implicit-def $sgpr28, implicit-def $sgpr28_lo16, implicit-def $sgpr29, implicit-def $sgpr29_lo16, implicit-def $sgpr30, implicit-def $sgpr30_lo16, implicit-def $sgpr31, implicit-def $sgpr31_lo16, implicit-def $sgpr24_sgpr25, implicit-def $sgpr24_sgpr25_sgpr26, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29, implicit-def $sgpr26_sgpr27, implicit-def $sgpr28_sgpr29, implicit-def $sgpr28_sgpr29_sgpr30, implicit-def $sgpr28_sgpr29_sgpr30_sgpr31, implicit-def $sgpr30_sgpr31, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30, implicit-def $sgpr36_sgpr37_sgpr38_sgpr39, implicit-def $sgpr36, implicit-def $sgpr36_lo16, implicit-def $sgpr37, implicit-def $sgpr37_lo16, implicit-def $sgpr38, implicit-def $sgpr38_lo16, implicit-def $sgpr39, implicit-def $sgpr39_lo16, implicit-def $sgpr36_sgpr37, implicit-def $sgpr36_sgpr37_sgpr38, implicit-def $sgpr38_sgpr39, implicit killed $sgpr14_sgpr15 {
; TOPDOWN-NEXT: renamable $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23 = S_LOAD_DWORDX8_IMM renamable $sgpr14_sgpr15, 0, 0 :: (invariant load (s256))
; TOPDOWN-NEXT: renamable $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM renamable $sgpr14_sgpr15, 128, 0 :: (invariant load (s128))
; TOPDOWN-NEXT: renamable $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31 = S_LOAD_DWORDX8_IMM renamable $sgpr14_sgpr15, 96, 0 :: (invariant load (s256))
@@ -80,7 +80,7 @@ body: |
; BOTTOMUP-NEXT: $sgpr10 = S_MOV_B32 killed $sgpr3
; BOTTOMUP-NEXT: $sgpr15 = S_MOV_B32 killed $sgpr1
; BOTTOMUP-NEXT: $exec = S_MOV_B64 killed renamable $sgpr16_sgpr17
- ; BOTTOMUP-NEXT: BUNDLE implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23, implicit-def $sgpr16, implicit-def $sgpr16_lo16, implicit-def $sgpr16_hi16, implicit-def $sgpr17, implicit-def $sgpr17_lo16, implicit-def $sgpr17_hi16, implicit-def $sgpr18, implicit-def $sgpr18_lo16, implicit-def $sgpr18_hi16, implicit-def $sgpr19, implicit-def $sgpr19_lo16, implicit-def $sgpr19_hi16, implicit-def $sgpr20, implicit-def $sgpr20_lo16, implicit-def $sgpr20_hi16, implicit-def $sgpr21, implicit-def $sgpr21_lo16, implicit-def $sgpr21_hi16, implicit-def $sgpr22, implicit-def $sgpr22_lo16, implicit-def $sgpr22_hi16, implicit-def $sgpr23, implicit-def $sgpr23_lo16, implicit-def $sgpr23_hi16, implicit-def $sgpr16_sgpr17, implicit-def $sgpr16_sgpr17_sgpr18, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21, implicit-def $sgpr18_sgpr19, implicit-def $sgpr20_sgpr21, implicit-def $sgpr20_sgpr21_sgpr22, implicit-def $sgpr20_sgpr21_sgpr22_sgpr23, implicit-def $sgpr22_sgpr23, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $sgpr0, implicit-def $sgpr0_lo16, implicit-def $sgpr0_hi16, implicit-def $sgpr1, implicit-def $sgpr1_lo16, implicit-def $sgpr1_hi16, implicit-def $sgpr2, implicit-def $sgpr2_lo16, implicit-def $sgpr2_hi16, implicit-def $sgpr3, implicit-def $sgpr3_lo16, implicit-def $sgpr3_hi16, implicit-def $sgpr0_sgpr1, implicit-def $sgpr0_sgpr1_sgpr2, implicit-def $sgpr2_sgpr3, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, implicit-def $sgpr24, implicit-def $sgpr24_lo16, implicit-def $sgpr24_hi16, implicit-def $sgpr25, implicit-def $sgpr25_lo16, implicit-def $sgpr25_hi16, implicit-def $sgpr26, implicit-def $sgpr26_lo16, implicit-def $sgpr26_hi16, implicit-def $sgpr27, implicit-def $sgpr27_lo16, implicit-def $sgpr27_hi16, implicit-def $sgpr28, implicit-def $sgpr28_lo16, implicit-def $sgpr28_hi16, implicit-def $sgpr29, implicit-def $sgpr29_lo16, implicit-def $sgpr29_hi16, implicit-def $sgpr30, implicit-def $sgpr30_lo16, implicit-def $sgpr30_hi16, implicit-def $sgpr31, implicit-def $sgpr31_lo16, implicit-def $sgpr31_hi16, implicit-def $sgpr24_sgpr25, implicit-def $sgpr24_sgpr25_sgpr26, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29, implicit-def $sgpr26_sgpr27, implicit-def $sgpr28_sgpr29, implicit-def $sgpr28_sgpr29_sgpr30, implicit-def $sgpr28_sgpr29_sgpr30_sgpr31, implicit-def $sgpr30_sgpr31, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30, implicit-def $sgpr36_sgpr37_sgpr38_sgpr39, implicit-def $sgpr36, implicit-def $sgpr36_lo16, implicit-def $sgpr36_hi16, implicit-def $sgpr37, implicit-def $sgpr37_lo16, implicit-def $sgpr37_hi16, implicit-def $sgpr38, implicit-def $sgpr38_lo16, implicit-def $sgpr38_hi16, implicit-def $sgpr39, implicit-def $sgpr39_lo16, implicit-def $sgpr39_hi16, implicit-def $sgpr36_sgpr37, implicit-def $sgpr36_sgpr37_sgpr38, implicit-def $sgpr38_sgpr39, implicit killed $sgpr14_sgpr15 {
+ ; BOTTOMUP-NEXT: BUNDLE implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23, implicit-def $sgpr16, implicit-def $sgpr16_lo16, implicit-def $sgpr17, implicit-def $sgpr17_lo16, implicit-def $sgpr18, implicit-def $sgpr18_lo16, implicit-def $sgpr19, implicit-def $sgpr19_lo16, implicit-def $sgpr20, implicit-def $sgpr20_lo16, implicit-def $sgpr21, implicit-def $sgpr21_lo16, implicit-def $sgpr22, implicit-def $sgpr22_lo16, implicit-def $sgpr23, implicit-def $sgpr23_lo16, implicit-def $sgpr16_sgpr17, implicit-def $sgpr16_sgpr17_sgpr18, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21, implicit-def $sgpr18_sgpr19, implicit-def $sgpr20_sgpr21, implicit-def $sgpr20_sgpr21_sgpr22, implicit-def $sgpr20_sgpr21_sgpr22_sgpr23, implicit-def $sgpr22_sgpr23, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $sgpr0, implicit-def $sgpr0_lo16, implicit-def $sgpr1, implicit-def $sgpr1_lo16, implicit-def $sgpr2, implicit-def $sgpr2_lo16, implicit-def $sgpr3, implicit-def $sgpr3_lo16, implicit-def $sgpr0_sgpr1, implicit-def $sgpr0_sgpr1_sgpr2, implicit-def $sgpr2_sgpr3, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, implicit-def $sgpr24, implicit-def $sgpr24_lo16, implicit-def $sgpr25, implicit-def $sgpr25_lo16, implicit-def $sgpr26, implicit-def $sgpr26_lo16, implicit-def $sgpr27, implicit-def $sgpr27_lo16, implicit-def $sgpr28, implicit-def $sgpr28_lo16, implicit-def $sgpr29, implicit-def $sgpr29_lo16, implicit-def $sgpr30, implicit-def $sgpr30_lo16, implicit-def $sgpr31, implicit-def $sgpr31_lo16, implicit-def $sgpr24_sgpr25, implicit-def $sgpr24_sgpr25_sgpr26, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29, implicit-def $sgpr26_sgpr27, implicit-def $sgpr28_sgpr29, implicit-def $sgpr28_sgpr29_sgpr30, implicit-def $sgpr28_sgpr29_sgpr30_sgpr31, implicit-def $sgpr30_sgpr31, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30, implicit-def $sgpr36_sgpr37_sgpr38_sgpr39, implicit-def $sgpr36, implicit-def $sgpr36_lo16, implicit-def $sgpr37, implicit-def $sgpr37_lo16, implicit-def $sgpr38, implicit-def $sgpr38_lo16, implicit-def $sgpr39, implicit-def $sgpr39_lo16, implicit-def $sgpr36_sgpr37, implicit-def $sgpr36_sgpr37_sgpr38, implicit-def $sgpr38_sgpr39, implicit killed $sgpr14_sgpr15 {
; BOTTOMUP-NEXT: renamable $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23 = S_LOAD_DWORDX8_IMM renamable $sgpr14_sgpr15, 0, 0 :: (invariant load (s256))
; BOTTOMUP-NEXT: renamable $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM renamable $sgpr14_sgpr15, 128, 0 :: (invariant load (s128))
; BOTTOMUP-NEXT: renamable $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31 = S_LOAD_DWORDX8_IMM renamable $sgpr14_sgpr15, 96, 0 :: (invariant load (s256))
@@ -128,7 +128,7 @@ body: |
renamable $sgpr0_sgpr1 = S_GETPC_B64
$sgpr15 = S_MOV_B32 killed $sgpr1
$exec = S_MOV_B64 killed renamable $sgpr16_sgpr17
- BUNDLE implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23, implicit-def $sgpr16, implicit-def $sgpr16_lo16, implicit-def $sgpr16_hi16, implicit-def $sgpr17, implicit-def $sgpr17_lo16, implicit-def $sgpr17_hi16, implicit-def $sgpr18, implicit-def $sgpr18_lo16, implicit-def $sgpr18_hi16, implicit-def $sgpr19, implicit-def $sgpr19_lo16, implicit-def $sgpr19_hi16, implicit-def $sgpr20, implicit-def $sgpr20_lo16, implicit-def $sgpr20_hi16, implicit-def $sgpr21, implicit-def $sgpr21_lo16, implicit-def $sgpr21_hi16, implicit-def $sgpr22, implicit-def $sgpr22_lo16, implicit-def $sgpr22_hi16, implicit-def $sgpr23, implicit-def $sgpr23_lo16, implicit-def $sgpr23_hi16, implicit-def $sgpr16_sgpr17, implicit-def $sgpr16_sgpr17_sgpr18, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21, implicit-def $sgpr18_sgpr19, implicit-def $sgpr20_sgpr21, implicit-def $sgpr20_sgpr21_sgpr22, implicit-def $sgpr20_sgpr21_sgpr22_sgpr23, implicit-def $sgpr22_sgpr23, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $sgpr0, implicit-def $sgpr0_lo16, implicit-def $sgpr0_hi16, implicit-def $sgpr1, implicit-def $sgpr1_lo16, implicit-def $sgpr1_hi16, implicit-def $sgpr2, implicit-def $sgpr2_lo16, implicit-def $sgpr2_hi16, implicit-def $sgpr3, implicit-def $sgpr3_lo16, implicit-def $sgpr3_hi16, implicit-def $sgpr0_sgpr1, implicit-def $sgpr0_sgpr1_sgpr2, implicit-def $sgpr2_sgpr3, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, implicit-def $sgpr24, implicit-def $sgpr24_lo16, implicit-def $sgpr24_hi16, implicit-def $sgpr25, implicit-def $sgpr25_lo16, implicit-def $sgpr25_hi16, implicit-def $sgpr26, implicit-def $sgpr26_lo16, implicit-def $sgpr26_hi16, implicit-def $sgpr27, implicit-def $sgpr27_lo16, implicit-def $sgpr27_hi16, implicit-def $sgpr28, implicit-def $sgpr28_lo16, implicit-def $sgpr28_hi16, implicit-def $sgpr29, implicit-def $sgpr29_lo16, implicit-def $sgpr29_hi16, implicit-def $sgpr30, implicit-def $sgpr30_lo16, implicit-def $sgpr30_hi16, implicit-def $sgpr31, implicit-def $sgpr31_lo16, implicit-def $sgpr31_hi16, implicit-def $sgpr24_sgpr25, implicit-def $sgpr24_sgpr25_sgpr26, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29, implicit-def $sgpr26_sgpr27, implicit-def $sgpr28_sgpr29, implicit-def $sgpr28_sgpr29_sgpr30, implicit-def $sgpr28_sgpr29_sgpr30_sgpr31, implicit-def $sgpr30_sgpr31, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30, implicit-def $sgpr36_sgpr37_sgpr38_sgpr39, implicit-def $sgpr36, implicit-def $sgpr36_lo16, implicit-def $sgpr36_hi16, implicit-def $sgpr37, implicit-def $sgpr37_lo16, implicit-def $sgpr37_hi16, implicit-def $sgpr38, implicit-def $sgpr38_lo16, implicit-def $sgpr38_hi16, implicit-def $sgpr39, implicit-def $sgpr39_lo16, implicit-def $sgpr39_hi16, implicit-def $sgpr36_sgpr37, implicit-def $sgpr36_sgpr37_sgpr38, implicit-def $sgpr38_sgpr39, implicit $sgpr14_sgpr15 {
+ BUNDLE implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23, implicit-def $sgpr16, implicit-def $sgpr16_lo16, implicit-def $sgpr17, implicit-def $sgpr17_lo16, implicit-def $sgpr18, implicit-def $sgpr18_lo16, implicit-def $sgpr19, implicit-def $sgpr19_lo16, implicit-def $sgpr20, implicit-def $sgpr20_lo16, implicit-def $sgpr21, implicit-def $sgpr21_lo16, implicit-def $sgpr22, implicit-def $sgpr22_lo16, implicit-def $sgpr23, implicit-def $sgpr23_lo16, implicit-def $sgpr16_sgpr17, implicit-def $sgpr16_sgpr17_sgpr18, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21, implicit-def $sgpr18_sgpr19, implicit-def $sgpr20_sgpr21, implicit-def $sgpr20_sgpr21_sgpr22, implicit-def $sgpr20_sgpr21_sgpr22_sgpr23, implicit-def $sgpr22_sgpr23, implicit-def $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3, implicit-def $sgpr0, implicit-def $sgpr0_lo16, implicit-def $sgpr1, implicit-def $sgpr1_lo16, implicit-def $sgpr2, implicit-def $sgpr2_lo16, implicit-def $sgpr3, implicit-def $sgpr3_lo16, implicit-def $sgpr0_sgpr1, implicit-def $sgpr0_sgpr1_sgpr2, implicit-def $sgpr2_sgpr3, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, implicit-def $sgpr24, implicit-def $sgpr24_lo16, implicit-def $sgpr25, implicit-def $sgpr25_lo16, implicit-def $sgpr26, implicit-def $sgpr26_lo16, implicit-def $sgpr27, implicit-def $sgpr27_lo16, implicit-def $sgpr28, implicit-def $sgpr28_lo16, implicit-def $sgpr29, implicit-def $sgpr29_lo16, implicit-def $sgpr30, implicit-def $sgpr30_lo16, implicit-def $sgpr31, implicit-def $sgpr31_lo16, implicit-def $sgpr24_sgpr25, implicit-def $sgpr24_sgpr25_sgpr26, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29, implicit-def $sgpr26_sgpr27, implicit-def $sgpr28_sgpr29, implicit-def $sgpr28_sgpr29_sgpr30, implicit-def $sgpr28_sgpr29_sgpr30_sgpr31, implicit-def $sgpr30_sgpr31, implicit-def $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30, implicit-def $sgpr36_sgpr37_sgpr38_sgpr39, implicit-def $sgpr36, implicit-def $sgpr36_lo16, implicit-def $sgpr37, implicit-def $sgpr37_lo16, implicit-def $sgpr38, implicit-def $sgpr38_lo16, implicit-def $sgpr39, implicit-def $sgpr39_lo16, implicit-def $sgpr36_sgpr37, implicit-def $sgpr36_sgpr37_sgpr38, implicit-def $sgpr38_sgpr39, implicit $sgpr14_sgpr15 {
renamable $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23 = S_LOAD_DWORDX8_IMM renamable $sgpr14_sgpr15, 0, 0 :: (invariant load (s256))
renamable $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM renamable $sgpr14_sgpr15, 128, 0 :: (invariant load (s128))
renamable $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31 = S_LOAD_DWORDX8_IMM renamable $sgpr14_sgpr15, 96, 0 :: (invariant load (s256))
diff --git a/llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir b/llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir
index 131656975ec40..ffcd5c3ef12fe 100644
--- a/llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir
+++ b/llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir
@@ -393,20 +393,20 @@ name: simple_bundle
body: |
bb.0:
; GCN-LABEL: name: simple_bundle
- ; GCN: BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
+ ; GCN: BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $mode, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
; GCN-NEXT: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0
; GCN-NEXT: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $m0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GCN-NEXT: }
- ; GCN-NEXT: BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
+ ; GCN-NEXT: BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $mode, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
; GCN-NEXT: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit $m0, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GCN-NEXT: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode
; GCN-NEXT: }
- BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
+ BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $mode, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0
$vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $m0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode
}
- BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
+ BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $mode, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0
$vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit $m0, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode
@@ -418,22 +418,22 @@ name: salu_in_between_bundle
body: |
bb.0:
; GCN-LABEL: name: salu_in_between_bundle
- ; GCN: BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
+ ; GCN: BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $mode, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
; GCN-NEXT: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0
; GCN-NEXT: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $m0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GCN-NEXT: }
; GCN-NEXT: $sgpr0 = S_MOV_B32 $sgpr2
- ; GCN-NEXT: BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
+ ; GCN-NEXT: BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $mode, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
; GCN-NEXT: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit $m0, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GCN-NEXT: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode
; GCN-NEXT: }
- BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
+ BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $mode, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0
$vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $m0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode
}
$sgpr0 = S_MOV_B32 $sgpr2
- BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
+ BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $mode, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0
$vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit $m0, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode
@@ -445,24 +445,24 @@ name: valu_in_between_bundle
body: |
bb.0:
; GCN-LABEL: name: valu_in_between_bundle
- ; GCN: BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
+ ; GCN: BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $mode, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
; GCN-NEXT: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0
; GCN-NEXT: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $m0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GCN-NEXT: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode
; GCN-NEXT: }
; GCN-NEXT: $vgpr20 = V_MOV_B32_indirect_read 1, implicit $exec, implicit $m0
- ; GCN-NEXT: BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
+ ; GCN-NEXT: BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $mode, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
; GCN-NEXT: S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0
; GCN-NEXT: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit $m0, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GCN-NEXT: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode
; GCN-NEXT: }
- BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
+ BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $mode, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0
$vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $m0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode
}
$vgpr20 = V_MOV_B32_indirect_read 1, implicit $exec, implicit $m0
- BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
+ BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $mode, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0
$vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit $m0, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode
@@ -474,24 +474,24 @@ name: changed_index_bundle
body: |
bb.0:
; GCN-LABEL: name: changed_index_bundle
- ; GCN: BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
+ ; GCN: BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $mode, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
; GCN-NEXT: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0
; GCN-NEXT: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $m0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GCN-NEXT: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode
; GCN-NEXT: }
; GCN-NEXT: $sgpr2 = S_MOV_B32 1
- ; GCN-NEXT: BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
+ ; GCN-NEXT: BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $mode, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
; GCN-NEXT: S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0
; GCN-NEXT: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit $m0, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GCN-NEXT: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode
; GCN-NEXT: }
- BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
+ BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $mode, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0
$vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $m0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode
}
$sgpr2 = S_MOV_B32 1
- BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
+ BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $mode, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 {
S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0
$vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit $m0, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_t16_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_t16_err.s
index cc765fef0c51a..1f041eb69f702 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_t16_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_t16_err.s
@@ -2,10 +2,10 @@
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 %s -filetype=null 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
v_mov_b16 v0.l, a0.h
-// GFX11: :[[@LINE-1]]:17: error: invalid operand for instruction
+// GFX11: :[[@LINE-1]]:17: error: invalid subregister
v_mov_b16 v0.l, s0.h
-// GFX11: :[[@LINE-1]]:17: error: invalid operand for instruction
+// GFX11: :[[@LINE-1]]:17: error: invalid subregister
v_mov_b16 v0.l, ttmp0.h
-// GFX11: :[[@LINE-1]]:17: error: invalid operand for instruction
+// GFX11: :[[@LINE-1]]:17: error: invalid subregister
>From 50762d3c239c4d5d41e2f119265c2c069c083e27 Mon Sep 17 00:00:00 2001
From: Igor Wodiany <igor.wodiany at amd.com>
Date: Wed, 13 May 2026 22:25:58 +0100
Subject: [PATCH 3/9] clang-format
---
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 0dc439fd8dd80..9f64c3d86dd98 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -2997,7 +2997,7 @@ MCRegister AMDGPUAsmParser::getRegularReg(RegisterKind RegKind, unsigned RegNum,
if (SubReg) {
Reg = TRI->getSubReg(Reg, SubReg);
- if(!Reg)
+ if (!Reg)
Error(Loc, "invalid subregister");
}
>From 08f9513be315ddf52a08d9518e2ddb41d98ab8f5 Mon Sep 17 00:00:00 2001
From: Igor Wodiany <igor.wodiany at amd.com>
Date: Thu, 14 May 2026 09:50:01 +0100
Subject: [PATCH 4/9] fix unittests
---
llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp b/llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp
index ec8ed7f15b35a..fdfa274d5adeb 100644
--- a/llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp
+++ b/llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp
@@ -41,7 +41,7 @@ TEST_F(AMDGPUTestBase, TestWave64DwarfRegMapping) {
// Verify that subregisters have no dwarf encoding.
for (MCRegister LLSubReg :
- {AMDGPU::VGPR1_LO16, AMDGPU::AGPR1_HI16, AMDGPU::SGPR1_HI16}) {
+ {AMDGPU::VGPR1_LO16}) {
EXPECT_EQ(MRI->getDwarfRegNum(LLSubReg, false), -1);
}
@@ -81,7 +81,7 @@ TEST_F(AMDGPUTestBase, TestWave32DwarfRegMapping) {
// Verify that subregisters have no dwarf encoding.
for (MCRegister LLSubReg :
- {AMDGPU::VGPR1_LO16, AMDGPU::AGPR1_HI16, AMDGPU::SGPR1_HI16}) {
+ {AMDGPU::VGPR1_LO16}) {
EXPECT_EQ(MRI->getDwarfRegNum(LLSubReg, false), -1);
}
>From afe1f998761a0dc1232a4d14f7f259a2bd3a918c Mon Sep 17 00:00:00 2001
From: Igor Wodiany <igor.wodiany at amd.com>
Date: Thu, 14 May 2026 09:50:46 +0100
Subject: [PATCH 5/9] clang-format
---
llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp b/llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp
index fdfa274d5adeb..c334b2380b101 100644
--- a/llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp
+++ b/llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp
@@ -40,8 +40,7 @@ TEST_F(AMDGPUTestBase, TestWave64DwarfRegMapping) {
}
// Verify that subregisters have no dwarf encoding.
- for (MCRegister LLSubReg :
- {AMDGPU::VGPR1_LO16}) {
+ for (MCRegister LLSubReg : {AMDGPU::VGPR1_LO16}) {
EXPECT_EQ(MRI->getDwarfRegNum(LLSubReg, false), -1);
}
@@ -80,8 +79,7 @@ TEST_F(AMDGPUTestBase, TestWave32DwarfRegMapping) {
}
// Verify that subregisters have no dwarf encoding.
- for (MCRegister LLSubReg :
- {AMDGPU::VGPR1_LO16}) {
+ for (MCRegister LLSubReg : {AMDGPU::VGPR1_LO16}) {
EXPECT_EQ(MRI->getDwarfRegNum(LLSubReg, false), -1);
}
>From 0a2a0f0fd3063d16c8df9f83805723f2f0763cc7 Mon Sep 17 00:00:00 2001
From: Igor Wodiany <igor.wodiany at amd.com>
Date: Mon, 1 Jun 2026 13:15:08 +0100
Subject: [PATCH 6/9] Move constrain register
---
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index d3c8cefccf644..ba5e5f4e38902 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -840,8 +840,6 @@ bool AMDGPUInstructionSelector::selectG_UNMERGE_VALUES(MachineInstr &MI) const {
const TargetRegisterClass *SrcRC =
TRI.getRegClassForSizeOnBank(SrcSize, *SrcBank);
- if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))
- return false;
// Note we could have mixed SGPR and VGPR destination banks for an SGPR
// source, and this relies on the fact that the same subregister indices are
@@ -850,7 +848,7 @@ bool AMDGPUInstructionSelector::selectG_UNMERGE_VALUES(MachineInstr &MI) const {
for (int I = 0, E = NumDst; I != E; ++I) {
MachineOperand &Dst = MI.getOperand(I);
// SGPRs do not support hi16 subregister, so extract upper 16-bits with a
- // shift and skip the subclass constraint step.
+ // shift and skip the subclass step.
if (SrcBank->getID() == AMDGPU::SGPRRegBankID &&
SubRegs[I] == AMDGPU::hi16) {
BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_LSHR_B32), Dst.getReg())
@@ -862,10 +860,11 @@ bool AMDGPUInstructionSelector::selectG_UNMERGE_VALUES(MachineInstr &MI) const {
// Make sure the subregister index is valid for the source register.
SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubRegs[I]);
- if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))
- return false;
}
+ if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))
+ return false;
+
const TargetRegisterClass *DstRC =
TRI.getConstrainedRegClassForOperand(Dst, *MRI);
if (DstRC && !RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI))
>From ea6820a7387b5f56507a258c83bdc683f2dec0a5 Mon Sep 17 00:00:00 2001
From: Igor Wodiany <igor.wodiany at amd.com>
Date: Mon, 1 Jun 2026 13:30:39 +0100
Subject: [PATCH 7/9] Clean up assign
---
llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
index 5aa35f103fe8f..cfaf062c85ee1 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -159,11 +159,11 @@ multiclass SIRegWithSubRegs<string n, bits<10> regIdx,
multiclass SIRegLoHi16 <string n, bits<10> regIdx,
bit isVGPR = 0, bit isAGPR = 0,
list<int> DwarfEncodings = [-1, -1]> {
- def _HI16 : SIReg<n#".h", regIdx, isVGPR, isAGPR, /* isHi16 */ 1>;
+ def _HI16 : SIReg<n#".h", regIdx, isVGPR, isAGPR, isHi16 = true>;
defm "" : SIRegWithSubRegs<n, regIdx, isVGPR, isAGPR, DwarfEncodings,
[!cast<Register>(NAME#"_LO16"),
!cast<Register>(NAME#"_HI16")],
- [lo16, hi16], /* coveredBySubRegs */ 1>;
+ [lo16, hi16], coveredBySubRegs = true>;
}
multiclass SIRegLo16 <string n, bits<10> regIdx,
@@ -171,7 +171,7 @@ multiclass SIRegLo16 <string n, bits<10> regIdx,
list<int> DwarfEncodings = [-1, -1]> {
defm "" : SIRegWithSubRegs<n, regIdx, isVGPR, isAGPR, DwarfEncodings,
[!cast<Register>(NAME#"_LO16")],
- [lo16], /* coveredBySubRegs */ 0>;
+ [lo16], coveredBySubRegs = false>;
}
// Special Registers
@@ -200,7 +200,7 @@ def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]> {
let CoveredBySubRegs = 1;
}
-defm EXEC_LO : SIRegLo16<"exec_lo", 126, /*isVGPR=*/ 0, /*isAGPR=*/0, /*DwarfEncodings=*/[1, 1]>;
+defm EXEC_LO : SIRegLo16<"exec_lo", 126, isVGPR= false, isAGPR = false, DwarfEncodings = [1, 1]>;
defm EXEC_HI : SIRegLo16<"exec_hi", 127>;
def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, DwarfRegNum<[17, 1]> {
@@ -356,7 +356,7 @@ def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT_SCR_HI, 0>;
// SGPR registers
foreach Index = 0...105 in {
defm SGPR#Index :
- SIRegLo16 <"s"#Index, Index, /*isVGPR=*/0, /*isAGPR=*/0, /*DwarfEncodings=*/
+ SIRegLo16 <"s"#Index, Index, isVGPR = false, isAGPR = false, DwarfEncodings =
[!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024)),
!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024))]>;
}
@@ -364,7 +364,7 @@ foreach Index = 0...105 in {
// VGPR registers
foreach Index = 0...1023 in {
defm VGPR#Index :
- SIRegLoHi16 <"v"#Index, Index, /*isVGPR=*/ 1, /*isAGPR=*/ 0, /*DwarfEncodings=*/
+ SIRegLoHi16 <"v"#Index, Index, isVGPR = true, isAGPR = false, DwarfEncodings =
[!if(!le(Index, 511), !add(Index, 2560), -1),
!if(!le(Index, 511), !add(Index, 1536), !add(Index, !sub(3584, 512)))]>;
}
@@ -372,7 +372,7 @@ foreach Index = 0...1023 in {
// AccVGPR registers
foreach Index = 0...255 in {
defm AGPR#Index :
- SIRegLo16 <"a"#Index, Index, /*isVGPR=*/ 0, /*isAGPR=*/ 1, /*DwarfEncodings=*/
+ SIRegLo16 <"a"#Index, Index, isVGPR = false, isAGPR = true, DwarfEncodings =
[!add(Index, 3072), !add(Index, 2048)]>;
}
>From f5623e73877b0036dd040e3eeff745e951b8305b Mon Sep 17 00:00:00 2001
From: Igor Wodiany <igor.wodiany at amd.com>
Date: Mon, 1 Jun 2026 13:34:28 +0100
Subject: [PATCH 8/9] fix test after rebase
---
.../AMDGPU/materialize-frame-index-sgpr.ll | 34 +++++++++----------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll b/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
index 52bdbb725dd00..765ece2ee0be2 100644
--- a/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
@@ -1136,25 +1136,25 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs_gep_i
; GFX7-NEXT: s_mov_b64 exec, s[4:5]
; GFX7-NEXT: v_writelane_b32 v23, s28, 17
; GFX7-NEXT: v_writelane_b32 v23, s29, 18
-; GFX7-NEXT: v_writelane_b32 v23, s30, 0
-; GFX7-NEXT: v_writelane_b32 v23, s31, 1
-; GFX7-NEXT: v_writelane_b32 v23, s33, 2
-; GFX7-NEXT: v_writelane_b32 v23, s34, 3
-; GFX7-NEXT: v_writelane_b32 v23, s35, 4
-; GFX7-NEXT: v_writelane_b32 v23, s36, 5
-; GFX7-NEXT: v_writelane_b32 v23, s37, 6
-; GFX7-NEXT: v_writelane_b32 v23, s38, 7
-; GFX7-NEXT: v_writelane_b32 v23, s39, 8
-; GFX7-NEXT: v_writelane_b32 v23, s48, 9
-; GFX7-NEXT: v_writelane_b32 v23, s49, 10
-; GFX7-NEXT: v_writelane_b32 v23, s50, 11
-; GFX7-NEXT: v_writelane_b32 v23, s51, 12
-; GFX7-NEXT: v_writelane_b32 v23, s52, 13
-; GFX7-NEXT: v_writelane_b32 v23, s53, 14
+; GFX7-NEXT: v_writelane_b32 v23, s33, 0
+; GFX7-NEXT: v_writelane_b32 v23, s34, 1
+; GFX7-NEXT: v_writelane_b32 v23, s35, 2
+; GFX7-NEXT: v_writelane_b32 v23, s36, 3
+; GFX7-NEXT: v_writelane_b32 v23, s37, 4
+; GFX7-NEXT: v_writelane_b32 v23, s38, 5
+; GFX7-NEXT: v_writelane_b32 v23, s39, 6
+; GFX7-NEXT: v_writelane_b32 v23, s48, 7
+; GFX7-NEXT: v_writelane_b32 v23, s49, 8
+; GFX7-NEXT: v_writelane_b32 v23, s50, 9
+; GFX7-NEXT: v_writelane_b32 v23, s51, 10
+; GFX7-NEXT: v_writelane_b32 v23, s52, 11
+; GFX7-NEXT: v_writelane_b32 v23, s53, 12
+; GFX7-NEXT: v_writelane_b32 v23, s54, 13
+; GFX7-NEXT: v_writelane_b32 v23, s55, 14
+; GFX7-NEXT: v_writelane_b32 v23, s30, 15
+; GFX7-NEXT: v_writelane_b32 v23, s31, 16
; GFX7-NEXT: v_lshr_b32_e64 v0, s32, 6
-; GFX7-NEXT: v_writelane_b32 v23, s54, 15
; GFX7-NEXT: v_add_i32_e32 v0, vcc, 64, v0
-; GFX7-NEXT: v_writelane_b32 v23, s55, 16
; GFX7-NEXT: ;;#ASMSTART
; GFX7-NEXT: ; use alloca0 v0
; GFX7-NEXT: ;;#ASMEND
>From 73d0fc15bce6f910f91e9a9aa222323f84550887 Mon Sep 17 00:00:00 2001
From: Igor Wodiany <igor.wodiany at amd.com>
Date: Mon, 1 Jun 2026 17:46:49 +0100
Subject: [PATCH 9/9] update test
---
llvm/test/CodeGen/AMDGPU/wqm.ll | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/test/CodeGen/AMDGPU/wqm.ll b/llvm/test/CodeGen/AMDGPU/wqm.ll
index 49a95b9cd9ceb..219a46f37f415 100644
--- a/llvm/test/CodeGen/AMDGPU/wqm.ll
+++ b/llvm/test/CodeGen/AMDGPU/wqm.ll
@@ -1474,6 +1474,7 @@ define amdgpu_ps float @test_control_flow_1(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10-W32-NEXT: .LBB28_2: ; %Flow
; GFX10-W32-NEXT: s_or_saveexec_b32 s0, s13
; GFX10-W32-NEXT: s_and_b32 exec_lo, exec_lo, s12
+; GFX10-W32-NEXT: s_and_b32 s0, exec_lo, s0
; GFX10-W32-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX10-W32-NEXT: s_cbranch_execz .LBB28_4
; GFX10-W32-NEXT: ; %bb.3: ; %ELSE
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