[llvm] [AMDGPU] Remove definition of hi16 for scalar registers (PR #197467)

[Igor Wodiany via llvm-commits]

IgWod wrote:

> > So, it looks like mask problems are related to liveness analysis - it looks like it relies on hi16 being available - but I haven't investigated in depth why that is. With that in mind I decided to keep hi16 for EXEC and VCC for now and that's something we can address in the future. Let me know if that works - we still get a verification for most of the registers and I think it's a step in the right direction in getting rid of artificial hi16 support.
> 
> What specifically is broken?

So, I think my initial analysis was wrong. I assumed it was liveness analysis causing `s_and` to be eliminated in `llvm/test/CodeGen/AMDGPU/wqm.ll`. But it seems `optimizeElseBranch` in `llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp` is a problem why the `wqm.ll` test was producing the incorrect code. It seems that the logic removing `s_and` starting on line 336 is being incorrectly executed. I'm going to revert the PR to the previous state and fix the root cause. Sorry, for all the confusion.

https://github.com/llvm/llvm-project/pull/197467