[llvm] [ISel] Introduce `llvm.pext` and `llvm.pdep` intrinsics (PR #200570)

[Pengcheng Wang via llvm-commits]

wangpc-pp wrote:

JFYI, I think there is no equivalent instruction in RVV or RISC-V scalar. The proposed sequences in https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2025/p3104r4.html#hardware-support can't simply be applied to `bits`.
<img width="1532" height="292" alt="image" src="https://github.com/user-attachments/assets/fac68fcf-f9ca-4c00-8e92-8c5d5024bb6c" />

We proposed the [[Proposal] Bit Compress & Bit Decompress Instructions for RVV](https://lists.riscv.org/g/sig-vector/topic/proposal_bit_compress_bit/113206944) one year ago but it got stuck because we received some negative feedbacks and we had more important things at that time.

https://github.com/llvm/llvm-project/pull/200570